rtd DM34216HR, User Manual

Page: 62 / 76

RTD Embedded Technologies, Inc.
| www.rtd.com
62 DM34216HR
User’s Manual
BDM-610010056 Rev A
6.6 BAR2: Capture Window
The capture window function block provides the ability to generate an arbitrary waveform that then can be place on the clock bus. Each window
has a delay counter register and a capture counter register. The delay counter register determines how many clock cycles to delay sampling for
and the capture counter register determines the how many clock cycles to capture data for.
6.6.1 F
UNCTION
B
LOCK
R
EGISTER
M
AP
Table 22: Capture Window Functional Block
Offset 0x03 0x02 0x01 0x00
H
ea
de
r FB + 0x00 FB_ID
FB + 0x04 FB_DMA_BUFFERS FB_DMA_CHANNELS FB_CONTROL_SIZE Reserved
C
on
trol
FB + 0x08 Reserved START_TRIG CLK_SRC MODE_STATUS
FB + 0x0C CLK_DIV
FB + 0x10 CLK_DIV_CNTR
FB + 0x14 Reserved
FB + 0x18 Reserved
FB + 0x1C SAMPLE_CNT
FB + 0x20 INT_ENA (Conversion, Start, Stop, Error, Channel)
FB + 0x24 INT_STAT Reserved
FB + 0x28 CLK_BUS3 CLK_BUS2 Reserved Reserved
FB + 0x2C CLK_BUS7 CLK_BUS6 CLK_BUS5 CLK_BUS4
FB + 0x30 CONFIG (Maskable register – 16-bit)
FB + 0x08 +
(FB_CONTROL_SIZE * 0x04) DELAY_COUNTER_0
FB + 0x0C +
(FB_CONTROL_SIZE * 0x04) CAPTURE_COUNTER_0
FB + 0x10 +
(FB_CONTROL_SIZE * 0x04) DELAY_COUNTER_1
FB + 0x14 +
(FB_CONTROL_SIZE * 0x04) CAPTURE_COUNTER_1
FB + 0x18 +
(FB_CONTROL_SIZE * 0x04) DELAY_COUNTER_2
FB + 0x1C +
(FB_CONTROL_SIZE * 0x04) CAPTURE_COUNTER_2
FB + 0x20 +
(FB_CONTROL_SIZE * 0x04) DELAY_COUNTER_3
FB + 0x24 +
(FB_CONTROL_SIZE * 0x04) CAPTURE_COUNTER_3
6.6.2 M
ODE
_S
TATUS
(R
EAD
/W
RITE
, R
EAD
-O
NLY
)
Selects the current mode of operation and indicates its triggering status.
B[3:0]: Mode
o
0x04: Uninitialized. This is the power-on state. No converter initialization has taken place. Sampling is stopped, and all
counters are reset and the triggering state machine is reset. Transition to any of the other Modes will start converter
initialization (sampling will not start until initialization is complete).
o
0x00: Reset. Sampling is stopped. All counters are reset and the triggering state machine is reset.
o
0x01: Paused. Sampling is stopped, but the counters and triggering state machine maintain their state.
o
0x02: Go, Single-Shot. After filling the buffer with the Post-Stop samples, capturing stops. The Mode must be set back
to RESET in order to capture more samples.
o
0x03: Go, Re-arm. After filling the buffer with the Post-Stop samples and the FIFO is empty, the triggering state machine
is restarted, i.e. FIFO is filled with Pre-Start samples and waits for a start trigger.