RTD Embedded Technologies, Inc.
|
www.rtd.com
55
DM34216HR
User’s Manual
BDM-610010056 Rev A
B[7:4]: Status
o
0x08: Uninitialized
–
The status when in the “Uninitialized” mode and the converter requires initiali
zation.
o
0x09: Initializing
o
0x00: Stopped
–
The status when in the “Reset” mode, or in the “Uninitialized” mode and the converter does not require
initialization.
o
0x01: Reserved
o
0x02: Waiting for start trigger
o
0x03: Running/Waiting for stop trigger
o
0x04: Reserved
o
0x05: Reserved
o
0x07: Done capturing
6.2.3
CLK_SRC
(R
EAD
/W
RITE
)
Selects the source for the clock of this function block.
0x00:
System clock/immediate
0x01:
Never
0x02:
CLK_BUS2
0x03:
CLK_BUS3
0x04:
CLK_BUS4
0x05:
CLK_BUS5
0x06:
CLK_BUS6
0x07:
CLK_BUS7
0x08:
Reserved
0x09:
Reserved
0x0A:
CLK_BUS2 Inverted
0x0B:
CLK_BUS3 Inverted
0x0C:
CLK_BUS4 Inverted
0x0D:
CLK_BUS5 Inverted
0x0E:
CLK_BUS6 Inverted
0x0F:
CLK_BUS7 Inverted
6.2.4
START_TRIG
(R
EAD
/W
RITE
)
Selects the start trigger from the clock bus. CLK_DIV will start counting after the start trigger, unless PRE_START_COUNT is non-zero in
which case CLK_DIV will start counting immediately.
Refer to
section above, for list of valid values.
6.2.5
STOP_TRIG
(R
EAD
/W
RITE
)
Selects the stop trigger from the clock bus.
Refer to
section above, for list of valid values.
6.2.6
CLK_DIV
(R
EAD
/W
RITE
)
Divider for the pacer clock. Pacer Clock Frequency = (Clk_Src_Frequency) / (1 + CLK_DIV). If synchronizing with the pacer clock from
another Function Block (by using one of the CLK_BUS signals), this is typically set to 0.
6.2.7
CLK_DIV_CNTR
(R
EAD
O
NLY
)
The current value of the Clock Divide Counter. This counter starts at a value of CLK_DIV, and counts down. When it reaches zero, a sample
is taken. This is useful when using a slow sample clock.
6.2.8
PRE_START_COUNT
(R
EAD
/W
RITE
)
Number of samples to collect before the Start Trigger. The length is limited by the FIFO size
–
writing a value larger than the FIFO size will
have indeterminate results.