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rtd DM34216HR User Manual Download Page 54

 

RTD Embedded Technologies, Inc. 

| 

www.rtd.com

 

 

54

 

DM34216HR

 

User’s Manual

 

 

 

BDM-610010056 Rev A

  

6.2

 

BAR2: Incremental Encoder 

This function block provides interface to the Incremental Encoder function block.  

6.2.1

 

F

UNCTION 

B

LOCK 

R

EGISTER 

M

AP

 

Table 18: Incremental Encoder Functional Block 

 

Offset 

0x03 

0x02 

0x01 

0x00 

H

ea

de

r  FB + 0x00 

FB_ID 

FB + 0x04 

FB_DMA_BUFFERS 

FB_DMA_CHANNELS  FB_CONTROL_SIZE 

Reserved

 

In

cr

em

en

ta

l En

cod

er

 C

on

trol

  FB + 0x08 

STOP_TRIG 

START_TRIG 

CLK_SRC 

MODE_STATUS 

FB + 0x0C 

CLK_DIV 

FB + 0x10 

CLK_DIV_CNTR 

FB + 0x14 

PRE_START_COUNT (limited by FIFO size) 

FB + 0x18 

POST_STOP_COUNT 

FB + 0x1C 

SAMPLE_CNT 

FB + 0x20 

INT_ENA (Sample, Start, Stop, Threshold, Pacer Tick, etc) 

FB + 0x24 

INT_STAT 

Reserved 

FB + 0x28 

CLK_BUS3 

CLK_BUS2 

Reserved 

Reserved

 

FB + 0x2C 

CLK_BUS7 

CLK_BUS6 

CLK_BUS5 

CLK_BUS4 

In

cr

em

en

ta

l En

cod

er

 C

ha

nn

el

 

FB + 0x08 + 
(FB_CONTROL_SIZE * 0x04)  

MODE_CONFIG (Maskable register 

–

 16-bit) 

FB + 0x0C + 
(FB_CONTROL_SIZE * 0x04)  

FIFO_DATA_CNT 

FB + 0x10 + 
(FB_CONTROL_SIZE * 0x04)  

MAX_FIFO_SIZE 

FB + 0x14 + 

(FB_CONTROL_SIZE * 0x04)  

THRESH_LOW 

FB + 0x1C + 

(FB_CONTROL_SIZE * 0x04)  

THRESH_HIGH 

FB + 0x20 + 

(FB_CONTROL_SIZE * 0x04)  

INCENC_VALUE 

FB + 0x24 + 
(FB_CONTROL_SIZE * 0x04)  

FIFO_ACCESS 

 

6.2.2

 

 

M

ODE

_S

TATUS 

(R

EAD

/W

RITE

,

 

R

EAD

-O

NLY

) 

Selects the current mode of operation and indicates its triggering status. 

B[3:0]: Mode 

o

 

0x04: Uninitialized.  This is the power-on state.  No converter initialization has taken place.  Sampling is stopped, and all 
counters are reset and the triggering state machine is reset.  Transition to any of the other Modes will start converter 
initialization (sampling will not start until initialization is complete). 

o

 

0x00: Reset.  Counting is stopped.  All counters are reset and the triggering state machine is reset. 

o

 

0x01: Paused.  Counting is stopped, but the counters and triggering state machine maintain their state. 

o

 

0x02: Go, Single-Shot.  After filling the buffer with the Post-Stop samples, capturing stops.  The Mode must be set back 
to RESET in order to capture more samples. 

o

 

0x03: Go, Re-arm. After filling the buffer with the Post-Stop samples and the FIFO is empty, the triggering state machine 
is restarted, i.e. FIFO is filled with Pre-Start samples and waits for a start trigger. 

Summary of Contents for DM34216HR

Page 1: ...RTD Embedded Technologies Inc AS9100 and ISO 9001 Certified DM34216HR 1 25MHz A D Digitizer User s Manual BDM 610010056 Rev A...

Page 2: ...c www rtd com ii DM34216HR User s Manual BDM 610010056 Rev A RTD Embedded Technologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales...

Page 3: ...ssions in this manual or for any loss damage or injury in connection with the use of this manual Copyright 2018 by RTD Embedded Technologies Inc All rights reserved Advanced Analog I O Advanced Digita...

Page 4: ...ard Handling Precautions 15 3 2 Physical Characteristics 15 3 3 Connectors and Jumpers 16 3 3 1 Bus Connectors 16 3 3 2 External I O Connectors 17 3 3 3 Jumpers 18 3 3 4 LEDs 18 3 4 Steps for Installi...

Page 5: ...6 6 2 9 FB_DMAm_Current_Buffer Read Only 36 6 2 10 FB_DMAm_COUNT Read Only 36 6 2 11 FB_DMAm_RD_FIFO_CNT Read Only 36 6 2 12 FB_DMAm_WR_FIFO_CNT Read Only 36 6 2 13 FB_DMAm_ADDRESSn Read Write 36 6 2...

Page 6: ...49 6 5 24 CH2_DATA DIG_DIR Read Write 49 6 5 25 CHn_FIFO_ACCESS Read Write 49 6 1 BAR2 PWM 50 6 1 1 Function Block Register Map 50 6 1 2 Mode_Status Read Write Read Only 50 6 1 3 CLK_SRC Read Write 5...

Page 7: ...6 6 8 INT_ENA Maskable Read Write 63 6 6 9 INT_STAT Read Clear 64 6 6 10 CLK_BUSn 64 6 6 11 CONFIG Maskable Read Write 65 6 6 12 DELAY_COUNTER_n Read Write 65 6 6 13 CAPTURE_COUNTER_n Read Write 65 6...

Page 8: ...rtd com viii DM34216HR User s Manual BDM 610010056 Rev A 6 8 17 CHn_FIFO_ACCESS Read Write 72 7 Troubleshooting 73 8 Additional Information 74 8 1 PC 104 Specifications 74 8 2 PCI and PCI Express Spec...

Page 9: ...al Characteristics 12 Table 4 Functional Characteristics 13 Table 5 CN3 Digital I O Pin out 17 Table 6 CN5 Pin out 18 Table 7 JP1 User ID Jumper 18 Table 8 IDAN DM34216 37 Pin High Density D Connector...

Page 10: ...mpling o 25 MSPS maximum input sampling rate o 16 bit resolution o Single ended inputs o Programmable 50 ohm or high impedance input o Programmable input full scale ranges in bipolar mode 1 667V 1 25V...

Page 11: ...st about any combination with other IDAN building blocks to create a simple but rugged 104 stack This module can also be incorporated in a custom built RTD HiDAN or HiDANplus High Reliability Intellig...

Page 12: ...nt Active 1 76 A PCIe 104 Bus Differential Output Voltage 0 8 1 2 V DC Differential TX Impedance 80 120 Differential Input Voltage 0 175 1 2 V DC Differential RX Impedance 80 120 Electrical Idle Detec...

Page 13: ...tional Characteristics Table 4 Functional Characteristics Symbol Parameter Value Unit GBC_SYS_CLK_FREQ System Clock Frequency 100 MHz Analog to Digital FIFO Size 1023 D Words Advanced DIO FIFO Size 51...

Page 14: ...www rtd com 14 DM34216HR User s Manual BDM 610010056 Rev A In Figure 2 a coherent 250kHz sine wave signal was attached to input Channel 0 3 in the 0 4167V 50 mode The FFT was generated using 500000 s...

Page 15: ...ystem When removing it from the bag hold the board at the edges and do not touch the components or connectors Handle the board in an antistatic environment and use a grounded workbench for testing and...

Page 16: ...nd can only connect to either Type 2 PCIe 104 connector CN16 Top CN17 Bottom Two Bank Connector The Two Bank connector is a high speed board to board interconnect Currently the only feature the two ba...

Page 17: ...C_A INC_ENC_B DIO0 15 16 15 DIO0 14 INC_ENC_B GND 18 17 GND INC_ENC_ Index DIO0 17 20 19 DIO0 16 INC_ENC_ Index DIO0 19 22 21 DIO0 18 DIO0 21 24 23 DIO0 20 DIO0 23 26 25 DIO0 22 DIO0 25 28 27 DIO0 24...

Page 18: ...umper results in a logic high and an open jumper results in a logic low Table 7 JP1 User ID Jumper Position Description 1 2 User ID bit 0 3 4 User ID bit 1 4 5 User ID bit 2 7 8 User ID bit 3 3 3 4 LE...

Page 19: ...or are properly positioned 6 Check the stacking order make sure all of the busses used by the peripheral cards are connected to the cpuModule 7 Hold the module by its edges and orient it so the bus co...

Page 20: ...re ready to install it into your system When removing it from the bag hold the module by the aluminum enclosure and do not touch the components or connectors Handle the module in an antistatic environ...

Page 21: ...phenol 901 9877 RFX Digital I O Connector 37 pin High Density D Female Connector Connector Part AMP 1658610 1 Example Mating Connector TYCO 1658608 1 Table 8 IDAN DM34216 37 Pin High Density D Connect...

Page 22: ...0 9 CN4 10 25 DIO0 11 CN4 12 26 DIO0 13 CN4 14 27 DIO0 15 CN4 16 28 GND CN4 18 29 DIO0 17 CN4 20 30 DIO0 19 CN4 22 31 DIO0 21 CN4 24 32 DIO0 23 CN4 26 33 DIO0 25 CN4 28 34 DIO0 27 CN4 30 35 DIO0 29 CN...

Page 23: ...ed by the peripheral cards are connected to the cpuModule 6 Hold the module by its edges and orient it so the bus connector pins line up with the matching connector on the stack 7 Gently and evenly pr...

Page 24: ...FPGA Each DMA channel also features a 64 bit PCI addressing and a 16MB maximum buffer for memory accessing 5 3 Programmable Clock The DM34216HR features 2 programmable clock functional block The progr...

Page 25: ...he master will drive a 10MHz clock on SyncBus3 to synchronize all the boards set as inputs or slaves Once boards are synchronized the PLL_LOCKED register will be set to 1 indicating it is now stable a...

Page 26: ...input or output On power cycle all digital I O lines are programmed as inputs meaning that the digital I O line s initial state is undetermined If the digital I O lines must power up to a known state...

Page 27: ...HR features a 32 bit incremental encoder functional block with DMA An Incremental Encoder is used to detect the relative position of a shaft or linear actuator A typical implementation is a slotted wh...

Page 28: ...ternal clocking function block This feature allows the user to input a clock to drive a CLK_BUSn signal or output a CLK_BUSn signal The CLK_SRCn are used to drive the CLK_BUSn signal which are part of...

Page 29: ...ipeline type the corresponding digital code will be delayed by 8 cycles from when taken by the converter This module provides 6 5V 4 5V overvoltage protection to the analog input with the attenuator i...

Page 30: ...shows the front end circuit for the DM34216HR It also shows the names of the FPGA registers in bold and the different ways the front end can be configured for different modes of operation Figure 10 A...

Page 31: ...FPGA registers for a single ended unipolar signal with a gain of 1 Also provided are graphs showing the difference between the input vs output to the differential amp 6V 4V Analog Input Gain Control C...

Page 32: ...n the upper word and a 16 bit mask value in the lower word For each bit in the data field it is only written to the register if the corresponding bit in the mask field is 1 Sticky Registers This is a...

Page 33: ...OFFSET_DMA 0x3C reserved 0x20 0x10 n FBn_ID 0x24 0x10 n FBn_OFFSET 0x28 0x10 n FBn_OFFSET_DMA 0x2C 0x10 n reserved 0x3F0 FB61_ID 0x3F4 FB61_OFFSET 0x3F8 FB61_OFFSET_DMA 0x3FC reserved 6 1 1 GBC_FMT RE...

Page 34: ...be generated again 6 1 9 GBC_DIRQ_STATUS READ CLEAR This is a 64 bit interrupt status register for DMA interrupts Each bit in this register corresponds to one of the Function Blocks bit 0 corresponds...

Page 35: ...stopped but all internal registers maintain their state During PAUSE you will still receive Stat_Underflow and Stat_Overflow interrupts After PAUSE you may transition to GO or CLEAR 0x03 Halt Buffer...

Page 36: ...occurred on the FIFO 6 2 8 FB_DMAM_STAT_COMPLETE READ WRITE This register is used to determine the source of a DMA interrupt The bits are cleared by writing 0x00 to the byte B0 Buffer_Complete R C Se...

Page 37: ...B1 Terminated R C DMA engine sets to 1 to indicate that this buffer was terminated early at the request of the associated Function Block 6 3 BAR2 Functional Block Header Registers Each Functional Blo...

Page 38: ...E 0x04 FRONT_END_CONFIG Maskable register 16 bit FB 0x0C FB_CONTROL_SIZE 0x04 FIFO_DATA_CNT FB 0x10 FB_CONTROL_SIZE 0x04 MAX_FIFO_SIZE FB 0x14 FB_CONTROL_SIZE 0x04 INT_ENA INT_STAT FILTER Reserved FB...

Page 39: ...clock sources and the register value needed to select the source B 7 0 o 0x00 System clock immediate o 0x01 Never o 0x02 CLK_BUS2 o 0x03 CLK_BUS3 o 0x04 CLK_BUS4 o 0x05 CLK_BUS5 o 0x06 CLK_BUS6 o 0x07...

Page 40: ...les to collect after the Stop Trigger 6 4 10 SAMPLE_CNT READ ONLY Total number of samples collected This does not increment in while in the Waiting For Start Trigger state It also continues counting a...

Page 41: ...ost o 0x87 Pacer The pacer clock has ticked 6 4 14 AD_CONFIG MASKABLE READ WRITE Not used 6 4 15 FRONT_END_CONFIG MASKABLE READ WRITE Refer to section 5 8 2 for more information about the front end ci...

Page 42: ...each ORDER Value ORDER 3 dB Cutoff 0 n a 1 0 114791 fs 2 0 045995 fs 3 0 021236 fs 4 0 010255 fs 5 0 005042 fs 6 0 002501 fs 7 0 001246 fs 6 4 19 INT_STAT READ CLEAR This is the status register for th...

Page 43: ...t or clock can be generated until the signal goes below this value The 3 least significant bits are ignored from the actual threshold value NOTE The threshold value should not exceed the ADC range If...

Page 44: ...6 bit FB 0x44 PERIPH_SEL_BIT_3 PERIPH_SEL_BIT_2 PERIPH_SEL_BIT_1 PERIPH_SEL_BIT_0 FB 0x48 PERIPH_SEL_BIT_7 PERIPH_SEL_BIT_6 PERIPH_SEL_BIT_5 PERIPH_SEL_BIT_4 FB 0x4C PERIPH_SEL_BIT_11 PERIPH_SEL_BIT_1...

Page 45: ...ples and waits for a start trigger B 7 4 Status o 0x08 Uninitialized The status when in the Uninitialized mode and the converter requires initialization o 0x09 Initializing o 0x00 Stopped The status w...

Page 46: ...nt in while in the Waiting For Start Trigger state It also continues counting after a Re Arm 6 5 11 INT_ENA MASKABLE READ WRITE Each bit corresponds to an interrupt source A value of 1 enables the sou...

Page 47: ...owing expression is true DIG_IN xor ADV_INT_COMP and not ADV_INT_MASK 0 o 0x2 Event Mode An Event interrupt is generated when any un masked input port bit changes This is when the following expression...

Page 48: ...DIG_OUT 28 27 30 DIG_OUT 27 26 29 DIG_OUT 26 25 28 DIG_OUT 25 24 27 DIG_OUT 24 23 26 DIG_OUT 23 22 25 DIG_OUT 22 21 24 DIG_OUT 21 20 23 DIG_OUT 20 19 22 DIG_OUT 19 18 21 DIG_OUT 18 17 20 DIG_OUT 17 1...

Page 49: ...he last value sent to the Digital Output For each bit a 0 causes the output to be low and a value 1 causes the output to be high Bit assignments are the same as DIG_IN This register defaults to all 0...

Page 50: ..._WIDTH FB 0x14 FB_CONTROL_SIZE 0x04 FB_CHANNEL_SIZE 0x04 n CHn_FIFO_ACCESS Note n in the offset stands for the channel number 6 1 2 MODE_STATUS READ WRITE READ ONLY Selects the current mode of operati...

Page 51: ...S7 Inverted 6 1 4 START_TRIG READ WRITE Selects the start trigger from the clock bus CLK_DIV will start counting after the start trigger unless PRE_START_COUNT is non zero in which case CLK_DIV will s...

Page 52: ...r The pacer clock has ticked 6 1 11 CLK_BUSN Selects a source to drive onto Clock Bus N That clock bus can then be used by a different function block as a clock source or trigger A function block can...

Page 53: ...affected until the next period Note that with Pacer Clock Frequency sets the maximum value for this register a 100 duty cycle is not possible This will result in the non inverted output to be low and...

Page 54: ...FB_CONTROL_SIZE 0x04 THRESH_LOW FB 0x1C FB_CONTROL_SIZE 0x04 THRESH_HIGH FB 0x20 FB_CONTROL_SIZE 0x04 INCENC_VALUE FB 0x24 FB_CONTROL_SIZE 0x04 FIFO_ACCESS 6 2 2 MODE_STATUS READ WRITE READ ONLY Sele...

Page 55: ...6 2 4 START_TRIG READ WRITE Selects the start trigger from the clock bus CLK_DIV will start counting after the start trigger unless PRE_START_COUNT is non zero in which case CLK_DIV will start countin...

Page 56: ...ned from 0xFFFFFFFF to 0x00000000 B9 Negative rollover Indicates channel has transitioned from 0x00000000 to 0xFFFFFFFF B10 High threshold crossed B11 Low threshold crossed 6 2 13 CLK_BUSN Selects a s...

Page 57: ...ister shows the max number of samples that the interval counter FIFO can hold 6 2 17 THRESH_LOW READ WRITE Unsigned 32 bit value indicating the low threshold If the count value goes below the threshol...

Page 58: ...alue on the External Clocking lines The bits in the register correspond with the External Clocking pins as follows Bit CN3 Pin CLK_BUS Signal 5 11 7 EXT_CLK_7 4 9 6 EXT_CLK_6 3 7 5 EXT_CLK_5 2 5 4 EXT...

Page 59: ...stay high 6 3 7 EXT_CLKN_CFG READ WRITE Selects clocking method B 7 0 o 0x00 Disables External Clocking o 0x80 Not Gated CLK_BUSn will be inputted outputted independent of the EXT_CLK_GATEn correspond...

Page 60: ...lue to temperature 0 0078125 Temperature C Register Value 150 0x4B00 125 0x3E80 25 0x0C80 0 0625 0x0008 0 0x0000 0 0625 0xFFF8 25 0xF380 55 0xE480 6 5 BAR2 Clock Generator This function block provides...

Page 61: ...ference 0 Clock is not present 1 Clock is present B2 Loss of Signal 1 LOS1 Indicates the loss of the onboard 10MHz reference this should always be 1 0 Clock is not present 1 Clock is present 6 5 4 CLK...

Page 62: ...x04 CAPTURE_COUNTER_0 FB 0x10 FB_CONTROL_SIZE 0x04 DELAY_COUNTER_1 FB 0x14 FB_CONTROL_SIZE 0x04 CAPTURE_COUNTER_1 FB 0x18 FB_CONTROL_SIZE 0x04 DELAY_COUNTER_2 FB 0x1C FB_CONTROL_SIZE 0x04 CAPTURE_COUN...

Page 63: ...nverted o 0x0C CLK_BUS4 Inverted o 0x0D CLK_BUS5 Inverted o 0x0E CLK_BUS6 Inverted o 0x0F CLK_BUS7 Inverted 6 6 4 START_TRIG READ WRITE Selects the start trigger from the clock bus CLK_DIV will start...

Page 64: ...3 Start Trigger B4 Reserved B5 Reserved B6 Reserved B7 Reserved 6 6 10 CLK_BUSN Selects a source to drive onto Clock Bus N That clock bus can then be used by a different function block as a clock sour...

Page 65: ...r n Delay Counter DELAY_COUNTER_n Pacer Clock 6 6 13 CAPTURE_COUNTER_N READ WRITE Sets the width of capture counter n Capture Counter CAPTURE_COUNTER_n Pacer Clock Capture Windows Start Trigger Delay...

Page 66: ...ock is using the local clock or the SyncBus clock If the SyncBus PLL loses its lock this register will revert back to the local clock B0 Select main clock input 0 local clock 1 SyncBus clock 6 7 3 PLL...

Page 67: ...0D CLK_BUS5 Inverted o 0x0E CLK_BUS6 Inverted o 0x0F CLK_BUS7 Inverted 6 7 7 DIRECTION READ WRITE Selects the direction of SYNCBUS_N NOTE When synchronizing multiple boards enabling multiple outputs o...

Page 68: ...0 SYNC0p n for SyncBus mode 1 GPIO mode 6 7 11 DIG_IN READ ONLY When the SyncBus is configured for GPIO mode with the SYNCBUS_MODE register the contents of the given DIG_IN register bit will display...

Page 69: ...04 Uninitialized This is the power on state No converter initialization has taken place Sampling is stopped and all counters are reset and the triggering state machine is reset Transition to any of th...

Page 70: ...r from the clock bus Refer to CLK_SRC Read Write section above for list of valid values 6 8 6 CLK_DIV READ WRITE Divider for the pacer clock Pacer Clock Frequency Clk_Src_Frequency 1 CLK_DIV If synchr...

Page 71: ...art Trigger o 0x84 Stop Trigger o 0x85 Reserved o 0x86 Reserved o 0x87 Reserved 6 8 12 MODE_CONFIG MASKABLE READ WRITE This register provides configuration for Programmable Clock function block B 1 In...

Page 72: ...610010056 Rev A 6 8 17 CHN_FIFO_ACCESS READ WRITE This register provides direct access to the DMA FIFO It can be used to access the data without the use of the DMA engine The DMA engine for this chann...

Page 73: ...th the least number of modules in the system possible Swap Components Try replacing parts in the system one at a time with similar parts to determine if a part is faulty or if a type of part is config...

Page 74: ...1 PC 104 Specifications A copy of the latest PC 104 specifications can be found on the webpage for the PC 104 Embedded Consortium www pc104 org 8 2 PCI and PCI Express Specification A copy of the late...

Page 75: ...of God or other contingencies beyond the control of RTD Embedded Technologies or as a result of service or modification by anyone other than RTD Embedded Technologies Except as expressly set forth ab...

Page 76: ...ologies Inc 103 Innovation Boulevard State College PA 16803 USA Telephone 814 234 8087 Fax 814 234 5218 www rtd com sales rtd com techsupport rtd com Copyright 2018 by RTD Embedded Technologies Inc Al...

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