rtd DM34216HR, User Manual, Page: 40 / 76

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40 DM34216HR
User’s Manual
BDM-610010056 Rev A
𝑆𝑎𝑚𝑝𝑙𝑒 𝐶𝑙𝑜𝑐𝑘 𝐷𝑒𝑙𝑎𝑦 = 150𝑝𝑠 × 𝐶𝐿𝐾_𝐷𝐸𝐿𝐴𝑌
Maximum clock delay is 2250ps, CLK_DELAY = 0xF
Minimum clock delay is 0ps, CLK_DIV = 0x0
6.4.7 CLK_READY
This register is used to tell the status of the ADC clock. When changing the CLK_DIV or CLK_DELAY register, checking this register will
indicate if the latest values have been set.
B7: Clock status 1 – Clock is ready; the latest values have been loaded 0 – Clock is not ready, still setting the latest values
6.4.8 PRE_TRIGGER_CAPTURE (R
EAD
/W
RITE
)
Number of samples to collect before the Start Trigger. The length is limited by the FIFO size – writing a value larger than the FIFO size will
have indeterminate results.
6.4.9 POST_STOP_CAPTURE (R
EAD
/W
RITE
)
Number of samples to collect after the Stop Trigger.
6.4.10 SAMPLE_CNT (R
EAD
O
NLY
)
Total number of samples col lected. This does not increment in while in the “Waiting For Start Trigger” state. It also continues counting after a
Re-Arm.
6.4.11 INT_ENA (M
ASKABLE
R
EAD
/W
RITE
)
Each bit corresponds to an interrupt source. A value of ‘1’ enables the source, and a value of ‘0’ disables it. See below for a description of the
sources.
6.4.12 INT_STAT (R
EAD
/C
LEAR
)
Each bit corresponds to an interrupt source. Reading a value of ‘1’ indicates that an event has occurred. Reading a value of ‘0’ indicates that
the event has not occurred. Writing a ‘1’ will clear that bit.
B0: Sample – A sample has been taken.
B1: Threshold – The ADC has exceeded the High or Low threshold. Check the THRESH_STAT register.
B2: Pre-Start Buffer Filled
B3: Start Trigger
B4: Stop Trigger
B5: Post-Stop Buffer Filled
B6: Sampling has completed, and the FIFO is empty (all data transferred to host)
B7: Pacer
– The pacer clock has ticked.