rtd DM34216HR, User Manual, Page: 30 / 76

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30 DM34216HR
User’s Manual
BDM-610010056 Rev A
5.8.1 I
NITIALIZING THE
ADC C
ONVERTER
The following is a list of the typical steps needed to initialize the ADC converter and begin sampling:
1. Set the ADC to the Uninitialized state ( Mode_Status )
2. Setup the DMA for the channel
3. Set the input mode ( FRONT_END_CONFIG )
4. Set the start and stop triggers ( START_TRIG , STOP_TRIG )
5. Set the sample rate ( CLK_DIV )
6. Set the Pre and/or Post Capture counters ( PRE_TRIGGER_CAPTURE , POST_STOP_CAPTURE )
7. Set the ADC to the Reset state ( Mode_Status )
8. Start the DMA
9. Start the ADC ( Mode_Status )
5.8.2 S
IMPLIFIED BLOCK DIAGRAM OF ANALOG INPUT
The following figure shows the front end circuit for the DM34216HR. It also shows the names of the FPGA registers in bold and the different
ways the front-end can be configured for different modes of operation.
Figure 10: Analog Front End
Table 10: ADC Full-Scale Settings
CHn_Front_End_Config
[GAIN]
CHn_Front_End_Config
[GAIN_05]
CHn_Front_End_Config
[IMPED]
Signal
Path
Gain
Unipolar
Mode
Bipolar
Mode
000 0 0 0.5 n/a ±5V
001 0
0 0.75 n/a ±3.3V
100 0
0 1 0-5V ±2.5V
101 0
0 1.5 0-3.3V ±1.667V
001 1
0/1 1.5 0-3.3V ±1.667V
100 1 0/1 2 0-2.5V ±1.25V
101 1
0/1 3 0-1.67V ±0.833V
110 1
0/1 4 0-1.25V ±0.625V
111 1
0/1 6 0-833V ±0.4167V
Refer to section 6.4.15 for more information about FPGA register control
+6V
-4V
Analog
Input
16bit 25MHz A/D
IN+
IN-
SDO
To FPGA
FPGA
DAC
Gain
Control
CHn_Front_End_Config
[GAIN_05]
CHn_Front_End_Config
[IMPED]
CHn_Front_End_Config
[GAIN]
OpAmp
OpAmp
Diff Amp
CHn_Front_End_Config
[UNI_BI]