RTD Embedded Technologies, Inc.
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67
DM34216HR
User’s Manual
BDM-610010056 Rev A
6.7.6
SB_
N
_CLK_SRC
(R
EAD
/W
RITE
)
Select source for SYNCBUS_N line output.
Below is the list of clock sources and the register value needed to select the source.
B[7:0]:
o
0x00: System clock/immediate
o
0x01: Never
o
0x02: CLK_BUS2
o
0x03: CLK_BUS3
o
0x04: CLK_BUS4
o
0x05: CLK_BUS5
o
0x06: CLK_BUS6
o
0x07: CLK_BUS7
o
0x08: N/A
o
0x09: N/A
o
0x0A: CLK_BUS2 Inverted
o
0x0B: CLK_BUS3 Inverted
o
0x0C: CLK_BUS4 Inverted
o
0x0D: CLK_BUS5 Inverted
o
0x0E: CLK_BUS6 Inverted
o
0x0F: CLK_BUS7 Inverted
6.7.7
DIRECTION
(R
EAD
/W
RITE
)
Selects the direction of SYNCBUS_N.
NOTE: When synchronizing multiple boards, enabling multiple outputs on a
SyncBus line may result in expected errors.
B0: Selects the direction SYNCBUS_0 line, 0 =Input, 1 = Output.
B1: Selects the direction SYNCBUS_1 line, 0 =Input, 1 = Output.
B2: Selects the direction SYNCBUS_2 line, 0 =Input, 1 = Output.
B3: Selects the direction SYNCBUS_3 (CLK) line, 0 =Input, 1 = Output.
6.7.8
CLK_BUS
N
Selects the source to drive onto Clock Bus signal N. Values are:
B[7:0] Clock Source Select
o
0x00: Disable Clock Source
o
0x80: CLK_EVENT_SYNCBUS_0
o
0x81: CLK_EVENT_SYNCBUS_1
o
0x82: CLK_EVENT_SYNCBUS_2