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41
DM34216HR
User’s Manual
BDM-610010056 Rev A
6.4.13
CLK_BUS
N
Selects a source to drive onto Clock Bus N. That clock bus can then be used by a different function block as a clock source or trigger.
A function block can drive multiple different Clock Buses. However, a Clock Bus N should not be driven by more than one function block at the
same time or the clock signal will be undefined.
B[7:0]:
o
0x00: Disables Clock Source
o
0x80: Sample
–
A sample has been taken.
o
0x81: Threshold
–
The ADC has exceeded the High or Low threshold. Check the THRESH_STAT register.
o
0x82: Pre-Start Buffer Filled
o
0x83: Start Trigger
o
0x84: Stop Trigger
o
0x85: Post-Stop Buffer Filled
o
0x86: Sampling has completed and the FIFO is empty (all data transferred to host)
o
0x87: Pacer
–
The pacer clock has ticked.
6.4.14
AD_CONFIG
(M
ASKABLE
R
EAD
/W
RITE
)
Not used.
6.4.15
FRONT_END_CONFIG
(M
ASKABLE
R
EAD
/W
RITE
)
Refer to section
for more information about the front-end circuit.
This register provides configuration to the Front End for the ADC.
B[8]: PACKED_DATA
0 = Data is unpacked
1 = Captured samples are packed (2 samples per 32-bit Sample)
B[7]: UNI_BI
0 = Bipolar Mode
1 = Unipolar Mode
B[6]: DITH
0 = Disable ADC dither
1 = Enables ADC dither
B[5]: IMPED
0 = High Impedance Input
1 = 50Ω Impedance Input
B[4]: GAIN_05
0 = gain *0.5 selected,
1 = gain *1 selected
Note: Gain_05 must be 1 when in 50Ω Impedance Mode
B[3:1]: GAIN
o
000: Gain of 1
o
001: Gain of 1.5
o
100: Gain of 2
o
101: Gain of 3
o
110: Gain of 4
o
111: Gain of 6
B[0]:Shutdown
0 = ADC is enabled 1 = ADC is disabled
6.4.16
FIFO_DATA_CNT
(R
EAD
)
This register shows the current sample count that is available in the ADC’s FIFO.
6.4.17
MAX_FIFO_SIZE
(R
EAD
)
This register shows the max number of samples that th
e ADC’s FIFO can hold.