rtd DM34216HR, User Manual, Page: 28 / 76

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28 DM34216HR
User’s Manual
BDM-610010056 Rev A
Separate interrupts are generated for positive and negative rollover. Positive rollover occurs when the counter is at its maximum value and
receives a signal to count up. Negative rollover occurs when the counter is at 0 and receives a signal to count down. Because separate
interrupts are generated, the counter can be easily expanded in software.
The Incremental Encoder inputs are show in the table below.
Table 9: Incremental Encoder Inputs
Pin
CN3 Pin #
A+ 13
A- 14
B+ 15
B- 16
Index + 19
Index - 20
Initializing the Incremental Encoder
The following is a list of typical steps needed to initialize the incremental encoder inputs.
1. Set the corresponding pins as input in the Advanced_DIO function block ( CH2_DATA )
2. Set the corresponding pins’ peripheral select to 0x00 ( PERIPH_SEL_BIT_n )
3. Set the Incremental Encoder function block to the Uninitialized state ( Mode_Status )
4. Setup the DMA for the Incremental Encoder channel
5. Pre-load with a known position ( INCENC_VALUE )
6. Set the mode/configuration ( MODE_CONFIG )
7. Set the start and stop triggers ( START_TRIG , STOP_TRIG )
8. Set the pacer clock ( CLK_SRC )
9. Set the Pre and/or Post Capture counters ( PRE_START_COUNT , POST_STOP_COUNT )
10. Set the Incremental Encoder function block to the Reset state ( Mode_Status )
11. Start the DMA
12. Start the Incremental Encoder function block ( Mode_Status )
5.6.3 E
XTERNAL
C
LOCKING
The DM34216HR features an external clocking function block. This feature allows the user to input a clock to drive a CLK_BUSn signal or
output a CLK_BUSn signal. The CLK_SRCn are used to drive the CLK_BUSn signal which are part of the most FPGA function blocks. The
CLK_BUSn signals are used as either sample clocks for function blocks or triggers for starting and stopping them.
There are 6 available CLK_BUSn, each is associated with a pin on CN3. Each can be configured to be either an input or an output. As an input
to a CLK_BUSn, the max input clock frequency is ½ system clock frequency. This value can be found in
GBC_SYS_CLK_FREQ on page 34.
As an output CLK_BUSn will generated on the associated pin. By default, this signal will be a pulse that is high for 10ns when the CLK_BUSn
signal goes high. The width of this pulse can be increased using
EXT_CLKn_PW on page 59.
Inputting an External Signal to the Clock Bus
The following is a list of typical steps needed to perform to input an external signal to the clock bus.
1. Connect the external signal to one of the external clocking pins EXT_CLK_2- EXT_CLK_7
2. Connect the gated signal to corresponding EXT_CLK_GATE_N, if gated signal is being used.
3. Set the corresponding pin as input in the Advanced_DIO function block ( CH2_DATA )
4. Set the corresponding pin’s peripheral select to 0x00 ( PERIPH_SEL_BIT_n )
5. Set the corresponding clock as input in the External Clocking function block ( EXT_CLK_DIR )
6. Set the corresponding clock’s edge detect ( EXT_CLK_EDGE )
7. Enable the external clock ( EXT_CLKn_CFG )
Outputting a Signal from the Clock Bus
The following is a list of typical steps needed to perform to output an external signal from the clock bus.