± 8g / 16g / 32g / 64g Tri-axis
Digital Accelerometer Technical
Reference Manual
PART NUMBER:
KX134-1211
Rev. 1.0
31-Jul-2019
36 Thornwood Dr.
–
Ithaca, NY 14850
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1.10 STATUS_REG (0X19)
This register reports the status of the interrupt.
R
R
R
R
R
R
R
R
0
0
0
INT
0
0
0
WAKE
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x19
INT
– reports the combined (OR) interrupt information according to interrupt setting.
0 = no interrupt event
1 = interrupt event has occurred
WAKE
– reports the wake/back to sleep state
0 = back-to-sleep state
1 = wake state
Note: Wake is the default state at power-up, shown in STATUS_REG register. For wake engine only
operation, set MAN_SLEEP bit to 1 in CNTL5 register to put KX134-1211 in sleep state for the first
time.
1.11 INT_REL (0X1A)
Interrupt latch release. Latched interrupt source information (INS1-INS3) is cleared and physical interrupt latched pin
is changed to its inactive state when this register is read.
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Address:
0x1A
Notes:
1. WMI and BFI are not cleared by this command.
2.
The latched interrupts are not cleared when INT_REL register is read using the auto
increment read mode in SPI communication, unless it is the starting address.
