R&S ZVL
Remote Control
Status Reporting System
Operating Manual 1303.6580.32-05
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3
QUEStionable status summary bit
This bit is set if an EVENt bit is set in the QUEStionable register and the associated ENABle bit is set to
1.
The bit indicates a questionable instrument status, which can be further pinned down by polling the
QUEStionable register.
5
ESB bit
Sum bit of the event status register. It is set if one of the bits in the event status register is set and
enabled in the event status enable register.
Setting of this bit implies an error or an event which can be further pinned down by polling the event
status register.
IST Flag and PPE
In analogy to the Service Request (SRQ), the IST flag combines the entire status information in a single
bit. It can be queried by means of a parallel poll.
The Parallel Poll Enable (PPE) register determines which bits of the STB contribute to the IST flag. The
bits of the STB are ANDed with the corresponding bits of the PPE, with bit 6 being used as well in contrast
to the SRE. The IST flag results from the ORing of all results.
Related common commands
The IST flag is queried using the command
*IST?
.
The PPE can be set using
*PRE
and read using command
*PRE?
.
ESR and ESE
The Event Status Register (ESR) indicates general instrument states. It is linked to the Event Status
Enable (ESE) register on a bit-by-bit basis.
The ESR corresponds to the CONDition part of an SCPI register, indicating the current instrument
state.
The ESE corresponds to the ENABle part of an SCPI register. If a bit is set in the ESE and the
associated bit in the ESR changes from 0 to 1, the ESB bit in the STatus Byte is set.
Related common commands
The Event Status Register (ESR) can be queried using
ESR?.
The Event Status Enable (ESE) register can be set using the command
*ESE
and read using
*ESE?
.
The bits in the ESR are defined as follows:
Bit No.
Meaning
0
Operation Complete
This bit is set on receipt of the command *OPC after all previous commands have been executed.
