Rohde & Schwarz M3SR Series 4100, Service Manual, Page: 49 / 138

Frontend - Function R&S M3SR Series 4100 HF Transceivers
1.13 6124.9007.82.01
1.3.2.3 Frontend - Function
General Function
(see Fig. 1.5)
The basic functions of the Frontend module are:
¾ in general:
• Data exchange with the Radio Controller (RC): IF-TX-data, IF-RX-data, AGC
¾ in receive:
• Mixing the antenna signal (10 kHz to 30 MHz) to the 48 kHz IF
• Filtering and amplifying the antenna signal
• Converting the 48 kHz IF to a digital data stream
¾ in transmit:
• Converting the digital IF-data (complex I/Q) to an analog 48 kHz signal
• Filtering and mixing this 48 kHz signal to the commanded transmit frequency
• Providing the exciter output signal (level +10 dBm PEP for SSB / +10 dBm for CW)
The RCB (radio control bus) is used for the main communication between Frontend and Radio
Controller. The ESSI (enhanced serial synchronous interface) realizes the communication between
Frontend and Radio Controller concerning timing critical signal processing data for TX and RX
operation.
Signal conversion RX and TX
Connector X1 serves as RX input as well as TX output. Connector X2 is provided for RX input signal
only. In RX mode a preamplifier increases the RX signal by 10 dB if it is not bypassed (0 dB gain). An
overvoltage detection acts as a relay every time RX input signal is too high. An input filter suppresses
unwanted signals with f > 30 MHz and improves IF rejection. The first mixer and crystal filter is used to
mix the antenna signal to the 1st IF of 40.048 MHz. The crystal filter contains a special form of quartz
crystal that provides a very precisely defined centre frequency, high quality factor Q and very steep
bandpass characteristics. The AGC amplifier with voltage controlled gain prevents the IF-A/D converter
against overdrive at large antenna signals. The second Mixer is used to mix the 1st IF (40.048 MHz) to
the 2nd IF (48 kHz). The 2nd 48 kHz IF signal is filtered, amplified and finally digitized. The IF A/D
converter delivers digital IF data, which are proceed in the FPGA and routed further to the Radio
Controller with a different data clock. A level detector delivers information for the AGC regulator. The
IF A/D converter requires a 12.288 MHz clock. This clock is synchronized to the 100 kHz radio
reference frequency, using a PLL circuit.