PowerFlex Digital DC Drive User Manual -
Publication 20P-UM001C-EN-P - July 2008
Application Notes
C-29
Fine Tuning the Speed Regulator
Follow the procedure below to fine tune and optimize the speed regulator:
1.
Configure the following Test Generator parameters:
❏
Set Par 58 [TstGen Output] = 4 “Ramp Ref”
❏
Set Par 59 [TstGen Frequency] = 0.2 Hz
❏
Set Par 60 [TstGen Amplitude] = 10 %
❏
Set Par 61 [TstGen Offset] = 20 %
2.
Measure the results on analog outputs 1 and 2 by setting:
❏
Par 66 [Anlg Out1 Sel] = 8 “Spd Reg Out”
❏
Par 67 [Anlg Out2 Sel] = 13 “Motor Curr”.
3.
Set Par 660 [Accel Time 1] = 0 sec.
4.
Set Par 662 [Decel Time 1] = 0 sec.
5.
Set Par 87 [Spd Reg Kp] = 0.00
6.
88 [Spd Reg Ki] = 0.00
7.
Start the drive.
8.
Increase the value of Par 87 [Spd Reg Kp] until the overshoot is lower than 4%
with the shortest possible acceleration or deceleration time.
9.
Increase the value of Par 88 [Spd Reg Ki] until the overshoot is higher than 4%.
Then, decrease the value of this parameter until its value becomes slightly
lower than 4%.
10. Stop the drive.
11. Set Par 58 [TstGen Output] = 0 “NotConnected”.
Important: When the “Bypass” function is enabled (Par 458 [SpdReg FB
Bypass] = 1 “Enabled”) the drive is automatically switched to
armature feedback when a “Speed fbk loss” fault occurs due to
an encoder or tachometer feedback loss. In this case, you must
repeat steps 1 - 9 of the “Fine Tuning the Speed Regulator”
procedure when the fault has been cleared. After an automatic
switch to armature feedback, the speed regulator works with
Pars 459 [SpdReg Kp Bypass] and 460 [SpdReg Ki Bypass]
and the D (derivative) part of the speed regulator is
automatically excluded.
When it is necessary to have different gains for the speed regulator above
the speed range, you can utilize the adaptive speed regulator. For further
information about this function refer to the Adaptive Speed Regulator block
diagram
