Renesas RL78/G1H, User Manual

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RL78/G1H CHAPTER 19 INTERRUPT FUNCTIONS
R01UH0575EJ0120 Rev. 1.20 Page 712 of 920
Dec 22, 2016
19.3.1 Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H)
The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is
executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or
upon reset signal generation.
When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt
routine is entered.
The IF0L, IF0H, IF1L, IF1H, IF2L, and IF2H registers can be set by a 1-bit or 8-bit memory manipulation
instruction. When the IF0L and IF0H registers, the IF1L and IF1H registers, and the IF2L and IF2H registers are
combined to form 16-bit registers IF0, IF1, and IF2, they can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark If an instruction that writes data to this register is executed, the number of instruction execution clocks
increases by 2 clocks.
Figure 19 - 2 Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (1/2)
Address: FFFE0H After reset: 00H R/W
Symbol 7 <6> <5> 4 3 <2> <1> <0>
IF0L
0 PIF4 PIF3 0 0 PIF0 LVIIF WDTIIF
Address: FFFE1H After reset: 00H R/W
Symbol <7> 6 5 4 3 <2> <1> <0>
IF0H TMIF01H 0 0 0 0 TMIF11H CSIIF21 CSIIF20
Address: FFFE2H After reset: 00H R/W
Symbol <7> <6> <5> <4> <3> <2> <1> <0>
IF1L TMIF03 TMIF02 TMIF01 TMIF00 IICAIF0
SREIF1
TMIF03H
SRIF1
STIF1
CSIIF10
Address: FFFE3H After reset: 00H R/W
Symbol <7> <6> <5> <4> 3 <2> <1> <0>
IF1H TMIF10 TRJIF0 SRIF3
STIF3
CSIIF30
0 ITIF RTCIF ADIF
Address: FFFD0H After reset: 00H R/W
Symbol <7> <6> 5 <4> <3> <2> <1> <0>
IF2L PIF10 PIF9 0 PIF7 PIF6 TMIF13 TMIF12 TMIF11