Renesas RL78/G1H, User Manual

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RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC)
R01UH0575EJ0120 Rev. 1.20 Page 535 of 920
Dec 22, 2016
16.5 Cautions for DTC
16.5.1 Setting DTC Control Data and Vector Table
• Do not access the DTC extended special function register (2nd SFR), the DTC control data area, the DTC
vector table area, or the general-register (FFEE0H to FFEFFH) space using a DTC transfer.
• Modify the DTC base address register (DTCBAR) while all DTC activation sources are set to activation
disabled.
• Do not rewrite the DTC base address register (DTCBAR) twice or more.
• Modify the data of the DTCCRj, DTBLSj, DTCCTj, DTRLDj, DTSARj, or DTDARj register when the
corresponding bit among bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 4) register is 0 (activation disabled).
• Modify the start address of the DTC control data area to be set in the vector table when the corresponding bit
among bits DTCENi0 to DTCENi7 in the DTCENi (i = 0 to 4) register is 0 (activation disabled).
• Do not allocate RAM addresses which are used as a DTC transfer destination/transfer source to the area
FFE20H to FFEDFH when performing self-programming and rewriting the data flash memory.
16.5.2 Allocation of DTC Control Data Area and DTC Vector Table Area
The areas where the DTC control data and vector table can be allocated differ, depending on the usage
conditions.
• It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as the DTC control data area or
DTC vector table area.
• Make sure the stack area, the DTC control data area, and the DTC vector table area do not overlap.
• The internal RAM area in the following products cannot be used as the DTC control data area or DTC vector
table area when using the self-programming and data-flash functions.
R5F11FLL: F3F00H to F4309H
• The internal RAM area in the following products cannot be used as the DTC control data area or DTC vector
table area when using the on-chip debugging trace function.
R5F11FLL: F4300H to F46FFH
• Initialize the DTRLD register to 00H even in normal mode when parity error resets are enabled (RPERDIS = 0)
using the RAM parity error detection function.