Renesas RL78/G1H, User Manual

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RL78/G1H CHAPTER 16 DATA TRANSFER CONTROLLER (DTC)
R01UH0575EJ0120 Rev. 1.20 Page 524 of 920
Dec 22, 2016
16.3.6 DTC block size register j (DTBLSj) (j = 0 to 23)
This register is used to set the block size of the data to be transferred by one activation.
Figure 16 - 7 Format of DTC block size register j (DTBLSj)
Caution Do not access the DTBLSj register using a DTC transfer.
16.3.7 DTC transfer count register j (DTCCTj) (j = 0 to 23)
This register is used to set the number of DTC data transfers. The value is decremented by 1 each time DTC
transfer is activated once.
Figure 16 - 8 Format of DTC transfer count register j (DTCCTj)
Caution Do not access the DTCCTj register using a DTC transfer.
Address: Refer to 16.3.2 Control Data Allocation . After reset: Undefined R/W
Symbol 7 6 5 4 3 2 1 0
DTBLSj DTBLSj7 DTBLSj6 DTBLSj5 DTBLSj4 DTBLSj3 DTBLSj2 DTBLSj1 DTBLSj0
DTBLSj Transfer Block Size
8-Bit Transfer 16-Bit Transfer
00H 256 bytes 512 bytes
01H 1 byte 2 bytes
02H 2 bytes 4 bytes
03H 3 bytes 6 bytes
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FDH 253 bytes 506 bytes
FEH 254 bytes 508 bytes
FFH 255 bytes 510 bytes
Address: Refer to 16.3.2 Control Data Allocation . After reset: Undefined R/W
Symbol 7 6 5 4 3 2 1 0
DTCCTj DTCCTj7 DTCCTj6 DTCCTj5 DTCCTj4 DTCCTj3 DTCCTj2 DTCCTj1 DTCCTj0
DTCCTj Number of Transfers
00H 256 times
01H Once
02H 2 times
03H 3 times
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• •
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FDH 253 times
FEH 254 times
FFH 255 times