CHAPTER 11 CLOCK OUTPUT/BUZZER OUTPUT CONTROLLER
Page 268 of 920
Figure 11 - 1 Block Diagram of Clock Output/Buzzer Output Controller
Note
For output frequencies available from PCLBUZ0 and PCLBUZ1, refer to 31.4
AC Characteristics
.
Prescaler
Clock/buzzer
controller
f
MAIN
f
SUB
PCLOE0
0
0
0
PCLOE0
5
3
Internal bus
CSEL0 CCS02 CCS01 CCS00
Output latch
(P141)
PM141
PM140
PCLOE1
0
0
0
CSEL1 CCS12 CCS11 CCS10
Prescaler
8
Internal bus
Clock/buzzer
controller
PCLOE1
8
Clock output select register 1 (CKS1)
Se
le
ct
o
r
Se
le
ct
o
r
f
MAIN
/2
11
to f
MAIN
/2
13
f
MAIN
to f
MAIN
/2
4
f
SUB
to f
SUB
/2
7
f
MAIN
/2
11
to f
MAIN
/2
13
f
MAIN
to f
MAIN
/2
4
f
SUB
to f
SUB
/2
7
Output latch
(P140)
PCLBUZ1
Note
/INTP7/P141
PCLBUZ0
Note
/INTP6/P140
Clock output select register 0 (CKS0)
Summary of Contents for RL78/G1H
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