Renesas RL78/G1H, User Manual

Page: 221 / 941

RL78/G1H CHAPTER 7 TIMER ARRAY UNIT
R01UH0575EJ0120 Rev. 1.20 Page 203 of 920
Dec 22, 2016
7.8.3 Operation as input pulse interval measurement
The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be
measured. In addition, the count value can be captured by using software operation (TSmn = 1) as a capture
trigger while the TEmn bit is set to 1.
The pulse interval can be calculated by the following expression.
Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of timer
mode register mn (TMRmn), so an error of up to one operating clock cycle occurs.
Timer count register mn (TCRmn) operates as an up counter in the capture mode.
When the channel start trigger bit (TSmn) of timer channel start register m (TSm) is set to 1, the TCRmn register
counts up from 0000H in synchronization with the count clock.
When the TImn pin input valid edge is detected, the count value of the TCRmn register is transferred (captured)
to timer data register mn (TDRmn) and, at the same time, the TCRmn register is cleared to 0000H, and the
INTTMmn is output. If the counter overflows at this time, the OVF bit of timer status register mn (TSRmn) is set to
1. If the counter does not overflow, the OVF bit is cleared. After that, the above operation is repeated.
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is
updated depending on whether the counter overflows during the measurement period. Therefore, the overflow
status of the captured value can be checked.
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF
bit of the TSRmn register is set to 1. However, a normal interval value cannot be measured for the OVF bit, if two
or more overflows occur.
Set the STSmn2 to STSmn0 bits of the TMRmn register to 001B to use the valid edges of TImn as a start trigger
and a capture trigger.
Figure 7 - 51 Block Diagram of Operation as Input Pulse Interval Measurement
Note When channels 1 and 3, the clock can be selected from CKm0, CKm1, CKm2 and CKm3.
Remark m: Unit number (m = 0), n: Channel number (n = 3)
TImn input pulse interval = Period of count clock × ((10000H × TSRmn: OVF) + (Capture value of TDRmn + 1))
Interrupt
controller
Interrupt signal
(INTTMmn) Timer data
register mn (TDRmn)
TSmn
Operation clock
Note
CKm0
CKm1
Edge
detection
Timer counter
register mn (TCRmn)
Cl
oc
k se
le
ct
io
n
T
ri
gg
er
se
le
ctio
n
TImn pin
Noise
filter
TNFENxx