Renesas RA Family
RA2 Quick Design Guide
R01AN6060EU0100 Rev.1.00
Page 37 of 44
Sep.14.21
Figure 28. RA2 MCU Bus Configuration
13.1 Bus Error Monitoring
The monitoring system monitors each individual area. Whenever it detects an error, it returns the error to the
requesting master IP using the AHB-Lite error response protocol.
13.1.1 Bus Error Types
The following types of errors can occur on each bus:
•
Illegal address access
•
Bus master MPU error
•
Bus slave MPU error
•
Timeout
13.1.2 Operation When a Bus Error Occurs
When a bus error occurs, operation is not guaranteed, and the error is returned to the requesting master IP.
The bus error information that occurred in each master is stored in the BUSnERRADD and BUSnERRSTAT
registers. These registers must be cleared by reset only. For more information, see section “Bus Error
Address Register (BUSnERRADD)” and “Bus Error Status Register (BUSnERRSTAT)” in the Hardware
User’s Manual.
Note:
The DTC do not receive bus errors, so their operation is not affected by bus errors.
14. 24-Bit Sigma-Delta A/D Converter (SDADC24)
The RA2A1 MCU Group includes one 24-bit Sigma-Delta A/D Converter. This is the only MCU Group in the
RA2 family that includes an SDADC. Figure 29 and Figure 30 list specifications of SDADC24 converter.
Refer to the “24-bit Sigma-Delta A/D Converter (SDADC24)” chapter in the RA2A1 MCU Hardware User’s
Manual for more details.