Renesas RA Family
RA2 Quick Design Guide
R01AN6060EU0100 Rev.1.00
Page 29 of 44
Sep.14.21
noise in these lines but are much too quick for filtering out long events like mechanical switch bounce.
Enabling filtering adds a short bit of latency (the filter time) to the hardware IRQ lines.
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Digital filtering can be enabled for each IRQ pin independently. This is done by setting the IRQ Pin Digital
Filter Enable (FLTEN) bit in the IRQCRi register for each IRQ.
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The clock rate for digital filtering is configurable for each IRQ pin independently. This is done by setting
the IRQ Pin Digital Filter Setting (FCLKSEL[1:0]) bits in the IRQCRi register for each IRQ.
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Figure 21 and Figure 22 show examples of enabling and configuring IRQ pins using Renesas FSP.
Figure 21. Enable P004 as IRQ03 input using Pin Configurator in Renesas FSP
