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Renesas R8C series, Hardware Manual

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Renesas R8C series Hardware Manual Download Page 21

R8C/18 Group, R8C/19 Group

1. Overview 

Rev.1.30

Apr 14, 2006

Page 6 of 233

REJ09B0222-0130

(D): Under Development

Figure 1.3

Type Number, Memory Size, and Package of R8C/19 Group

Table 1.4

Product Information for R8C/19 Group

Current of Apr. 2006

 Type No.

ROM Capacity

RAM 

Capacity

Package Type

Remarks

Program ROM

Data flash

R5F21191SP 

4 Kbytes

1 Kbyte × 2

384 bytes

PLSP0020JB-A

Flash memory version

R5F21192SP 

8 Kbytes

1 Kbyte × 2

512 bytes

PLSP0020JB-A

R5F21193SP 

12 Kbytes

1 Kbyte × 2

768 bytes

PLSP0020JB-A

R5F21194SP 16 

Kbytes

1 

Kbyte × 2

1 Kbyte

PLSP0020JB-A

R5F21191DSP (D)

4 Kbytes

1 Kbyte × 2

384 bytes

PLSP0020JB-A

D version

R5F21192DSP (D)

8 Kbytes

1 Kbyte × 2

512 bytes

PLSP0020JB-A

R5F21193DSP (D)

12 Kbytes

1 Kbyte × 2

768 bytes

PLSP0020JB-A

R5F21194DSP (D)

16 Kbytes

1 Kbyte × 2

1 Kbyte

PLSP0020JB-A

R5F21191DD

4 Kbytes

1 Kbyte × 2

384 bytes

PRDP0020BA-A Flash memory version

R5F21192DD

8 Kbytes

1 Kbyte × 2

512 bytes

PRDP0020BA-A

R5F21193DD

12 Kbytes

1 Kbyte × 2

768 bytes

PRDP0020BA-A

R5F21194DD

16 Kbytes

1 Kbyte × 2

1 Kbyte

PRDP0020BA-A

R5F21192NP

8 Kbytes

1 Kbyte × 2

512 bytes

PWQN0028KA-B Flash memory version

R5F21193NP

12 Kbytes

1 Kbyte × 2

768 bytes

PWQN0028KA-B

R5F21194NP

16 Kbytes

1 Kbyte × 2

1 Kbyte

PWQN0028KA-B

T y p e   N o .

R   5   F   2 1   1 9   4   D   S P

Package type:

SP: PLSP0020JB-A
DD: PRDP0020BA-A
NP: PWQN0028KA-B

Classification

D: Operating ambient temperature -40°C to 85°C

No Symbol: Operating ambient temperature  -20

°

C to 85°C

ROM capacity

2: 8 KB
3: 12 KB
4: 16 KB

R8C/19 Group

R8C/Tiny Series

Memory type

F: Flash memory

Renesas MCU

Renesas semiconductors

Summary of Contents for R8C series

Page 1: ...mation contained in these materials including products and product specifications represents information on the product at the time of publication and is subject to change by Renesas Technology Corp w...

Page 2: ...ribed here may contain technical inaccuracies or typographical errors Renesas Technology Corp assumes no responsibility for any damage liability or other loss rising from these inaccuracies or errors...

Page 3: ...supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is sup...

Page 4: ...tails The following documents apply to the R8C 18 Group R8C 19 Group Make sure to refer to the latest versions of these documents The newest versions of the documents listed may be obtained from the R...

Page 5: ...panied by the word register bit or pin to distinguish the three categories Examples the PM03 bit in the PM0 register P3_5 pin VCC pin 2 Notation of Numbers The indication b is appended to numeric valu...

Page 6: ...ue Operation is not guaranteed when a value is set Function varies according to the operating mode The function of the bit varies with the peripheral function mode Refer to the register diagram for in...

Page 7: ...ontroller GSM Global System for Mobile Communications Hi Z High Impedance IEBus Inter Equipment bus I O Input Output IrDA Infrared Data Association LSB Least Significant Bit MSB Most Significant Bit N...

Page 8: ...Table Register INTB 14 2 5 Program Counter PC 14 2 6 User Stack Pointer USP and Interrupt Stack Pointer ISP 14 2 7 Static Base Register SB 14 2 8 Flag Register FLG 14 2 8 1 Carry Flag C 14 2 8 2 Debug...

Page 9: ...al Functions 28 6 3 Pins Other than Programmable I O Ports 28 6 4 Port settings 35 6 5 Unassigned Pin Handling 39 7 Voltage Detection Circuit 40 7 1 VCC Input Voltage 46 7 1 1 Monitoring Vdet1 46 7 1...

Page 10: ...Generation Circuit 70 10 6 1 Stop Mode and Wait Mode 70 10 6 2 Oscillation Stop Detection Function 70 10 6 3 Oscillation Circuit Constants 70 10 6 4 High Speed On Chip Oscillator Clock 70 11 Protecti...

Page 11: ...de 107 14 1 3 Event Counter Mode 109 14 1 4 Pulse Width Measurement Mode 110 14 1 5 Pulse Period Measurement Mode 113 14 1 6 Notes on Timer X 116 14 2 Timer Z 117 14 2 1 Timer Mode 122 14 2 2 Programm...

Page 12: ...on 177 17 4 CPU Rewrite Mode 178 17 4 1 EW0 Mode 179 17 4 2 EW1 Mode 179 17 4 3 Software Commands 188 17 4 4 Status Register 192 17 4 5 Full Status Check 193 17 5 Standard Serial I O Mode 195 17 5 1 I...

Page 13: ...C 222 19 4 Notes on Serial Interface 223 19 5 Notes on Comparator 224 19 6 Notes on Flash Memory Version 225 19 6 1 CPU Rewrite Mode 225 19 7 Notes on Noise 227 19 7 1 Inserting a Bypass Capacitor bet...

Page 14: ...ge Detection Register 1 VCA1 43 0032h Voltage Detection Register 2 VCA2 43 0033h 0034h 0035h 0036h Voltage Monitor 1 Circuit Control Register VW1C 44 0037h Voltage Monitor 2 Circuit Control Register V...

Page 15: ...149 00A9h UART1 Bit Rate Register U1BRG 148 00AAh UART1 Transmit Buffer Register U1TB 148 00ABh 00ACh UART1 Transmit Receive Control Register 0 U1C0 150 00ADh UART1 Transmit Receive Control Register...

Page 16: ...HWQFN It implements sophisticated instructions for a high level of instruction efficiency With 1 Mbyte of address space they are capable of executing instructions at high speed Furthermore the R8C 19...

Page 17: ...hannel UART Comparator 1 bit comparator 1 circuit 4 channels Watchdog timer 15 bits 1 channel with prescaler Reset start selectable count source protection mode Interrupts Internal 10 sources External...

Page 18: ...scaler Reset start selectable count source protection mode Interrupts Internal 10 sources External 4 sources Software 4 sources Priority levels 7 levels Clock generation circuits 2 circuits Main clock...

Page 19: ...r C 16 bits Comparator 1 bit 4 channels System clock generator XIN XOUT High speed on chip oscillator Low speed on chip oscillator UART or clock synchronous serial I O 8 bits 1 channel Memory Watchdog...

Page 20: ...384 bytes PLSP0020JB A D version R5F21182DSP D 8 Kbytes 512 bytes PLSP0020JB A R5F21183DSP D 12 Kbytes 768 bytes PLSP0020JB A R5F21184DSP D 16 Kbytes 1 Kbyte PLSP0020JB A R5F21181DD 4 Kbytes 384 byte...

Page 21: ...0020JB A R5F21193DSP D 12 Kbytes 1 Kbyte 2 768 bytes PLSP0020JB A R5F21194DSP D 16 Kbytes 1 Kbyte 2 1 Kbyte PLSP0020JB A R5F21191DD 4 Kbytes 1 Kbyte 2 384 bytes PRDP0020BA A Flash memory version R5F21...

Page 22: ...iew Figure 1 4 Pin Assignments for PLSP0020JB A Package Top View 1 2 3 4 5 6 7 8 9 10 20 P3_4 CMP1_1 19 P3_3 TCIN INT3 CMP1_0 18 P1_0 KI0 AN8 CMP0_0 17 P1_1 KI1 AN9 CMP0_1 16 P4_2 VREF 15 P1_2 KI2 AN1...

Page 23: ...IN INT3 CMP1_0 18 P1_0 KI0 AN8 CMP0_0 17 P1_1 KI1 AN9 CMP0_1 16 P4_2 VREF 15 P1_2 KI2 AN10 CMP0_2 14 P1_3 KI3 AN11 TZOUT 13 P1_4 TXD0 12 P1_5 RXD0 CNTR01 INT11 11 P1_6 CLK0 P3_5 CMP1_2 P3_7 CNTR0 TXD1...

Page 24: ...XD1 MODE VCC AVCC P1_1 AN9 KI1 CMP0_1 P1_0 AN8 KI0 CMP0_0 PIN Assignment top view Package PWQN0028KA B 28PJW B R8C 18 Group R8C 19 Group NOTES 1 P4_7 is a port for the input 14 13 12 11 10 9 8 22 23 2...

Page 25: ...between the XIN and XOUT pins To use an external clock input it to the XIN pin and leave the XOUT pin open Main clock output XOUT O INT interrupt INT0 INT1 INT3 I INT interrupt input pins Key input in...

Page 26: ...n Functions for Peripheral Modules Interrupt Timer Serial Interface Comparator 1 P3_5 CMP1_2 2 P3_7 CNTR0 TXD1 3 RESET 4 XOUT P4_7 5 VSS AVSS 6 XIN P4_6 7 VCC AVCC 8 MODE 9 P4_5 INT0 RXD1 10 P1_7 INT1...

Page 27: ...nterrupt Timer Serial Interface Comparator 1 NC 2 XOUT P4_7 3 VSS AVSS 4 NC 5 NC 6 XIN P4_6 7 NC 8 VCC AVCC 9 MODE 10 P4_5 INT0 RXD1 11 P1_7 INT10 CNTR00 12 P1_6 CLK0 13 P1_5 INT11 CNTR01 RXD0 14 P1_4...

Page 28: ...INTBL FB Frame base register 1 The 4 high order bits of INTB are INTBH and the 16 low bits of INTB are INTBL Interrupt table register b19 b0 USP Program counter ISP SB User stack pointer Interrupt sta...

Page 29: ...icates the start address of an interrupt vector table 2 5 Program Counter PC PC is 20 bits wide indicates the address of the next instruction to be executed 2 6 User Stack Pointer USP and Interrupt St...

Page 30: ...ck Pointer Select Flag U ISP is selected when the U flag is set to 0 USP is selected when the U flag is set to 1 The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT ins...

Page 31: ...egisters SFRs are allocated addresses 00000h to 002FFh The peripheral function control registers are allocated here All addresses within the SFR which have nothing allocated are reserved for future us...

Page 32: ...allocated addresses 00000h to 002FFh The peripheral function control registers are allocated here All addresses within the SFR which have nothing allocated are reserved for future use and cannot be ac...

Page 33: ...nterrupt Enable Register AIER 00h 000Ah Protect Register PRCR 00h 000Bh 000Ch Oscillation Stop Detection Register OCD 00000100b 000Dh Watchdog Timer Reset Register WDTR XXh 000Eh Watchdog Timer Start...

Page 34: ...00b 0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b 0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b 0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b 0055h...

Page 35: ...h 0096h External Input Enable Register INTEN 00h 0097h 0098h Key Input Enable Register KIEN 00h 0099h 009Ah Timer C Control Register 0 TCC0 00h 009Bh Timer C Control Register 1 TCC1 00h 009Ch Capture...

Page 36: ...trol Register 1 ADCON1 00h 00D8h 00D9h 00DAh 00DBh 00DCh 00DDh 00DEh 00DFh 00E0h 00E1h Port P1 Register P1 XXh 00E2h 00E3h Port P1 Direction Register PD1 00h 00E4h 00E5h Port P3 Register P3 XXh 00E6h...

Page 37: ...t VCC falls monitor voltage Vdet1 Voltage monitor 2 reset VCC falls monitor voltage Vdet2 Watchdog timer reset Underflow of watchdog timer Software reset Write 1 to PM03 bit in PM0 register RESET Powe...

Page 38: ...ter INTB Program counter PC User stack pointer USP Interrupt stack pointer ISP Static base register SB Content of addresses 0FFFEh to 0FFFCh Flag register FLG C IPL D Z S B O I U b15 b0 b15 b0 b15 b0...

Page 39: ...ters SFRs for the state of the SFRs after reset The internal RAM is not reset If the RESET pin is pulled L while writing to the internal RAM is in progress the contents of internal RAM will be undefin...

Page 40: ...e Reset Circuit Usage Example of External Supply Voltage Detection Circuit and Operation RESET VCC VCC RESET 2 7 V 0V 0 2 VCC or below td P R 500 s or more 0V NOTE 1 Refer to 18 Electrical Characteris...

Page 41: ...by 8 is automatically selected as the CPU after reset Refer to 4 Special Function Registers SFRs for the status of the SFR after power on reset The voltage monitor 1 reset is enabled after power on r...

Page 42: ...d the program beginning with the address indicated by the reset vector is executed After reset the low speed on chip oscillator clock divided by 8 is automatically selected as the CPU clock The voltag...

Page 43: ..._6 and PD4_7 6 2 Effect on Peripheral Functions Programmable I O ports function as I O ports for peripheral functions Refer to Table 1 6 Pin Name Information by Pin Number of PLSP0020JB A PRDP0020BA A...

Page 44: ...ot exceed VCC P1_0 to P1_3 1 Analog input Port latch Direction register Data bus Pull up selection Input to individual peripheral function Drive capacity selection P1_4 1 Port latch Direction register...

Page 45: ...up selection Digital filter P3_4 P3_5 P3_7 1 Port latch Direction register Data bus Pull up selection 1 Output from individual peripheral function 1 Output from individual peripheral function Output...

Page 46: ...Pull up selection Digital filter P4_6 XIN Data bus Clocked inverter 1 P4_7 XOUT Data bus Note 2 Note 3 NOTES 1 When CM05 1 CM10 1 or CM13 0 the clocked inverter is cut off 2 When CM10 1 or CM13 0 the...

Page 47: ...ts Rev 1 30 Apr 14 2006 Page 32 of 233 REJ09B0222 0130 Figure 6 4 Configuration of I O Pins MODE MODE signal input Note 1 RESET RESET signal input Note 1 NOTES 1 symbolizes a parasitic diode Ensure th...

Page 48: ...register are unavailable on this MCU If it is necessary to set bits PD3_0 to PD3_2 and PD3_6 set to 0 input mode When read the content is 0 Port Pi Register i 1 3 4 1 2 Symbol Address After Reset P1...

Page 49: ...PU06 RW RW RW P1_4 to P1_7 pull up 1 PU02 b5 b4 Pull Up Control Register 1 Symbol Address After Reset PUR1 00FDh XXXXXX0Xb Bit Symbol Bit Name Function RW NOTE 1 b0 When the PU11 bit is set to 1 pull...

Page 50: ...ut Table 6 5 Port P1_1 KI1 AN9 CMP0_1 Register PD1 PUR0 DRR KIEN ADCON0 TCOUT Function Bit PD1_1 PU02 DRR1 KI1EN CH2 CH1 CH0 ADGSEL0 TCOUT1 Setting Value 0 0 X X XXXX 0 Input port not pulled up 0 1 X...

Page 51: ...Output port X X 1 X XXXX 01b 1 Output port high drive X X X X XXXX 01b 0 TZOUT output X X X X XXXX 1Xb X TZOUT output Table 6 8 Port P1_4 TXD0 Register PD1 PUR0 U0MR U0C0 Function Bit PD1_4 PU03 SMD2...

Page 52: ...PUR0 TXMR UCON Function Bit PD1_7 PU03 TXMOD1 TXMOD0 CNTRSEL Setting Value 0 0 Other than 01b X Input port not pulled up 0 1 Other than 01b X Input port pulled up 0 0 Other than 01b 0 CNTR00 INT10 inp...

Page 53: ...port pulled up 1 X 000b 0 0X Output port X X 001b X 11b TXD1 output pin 100b 101b 110b X X 000b 1 XX CNTR0 output pin Table 6 16 Port XIN P4_6 XOUT P4_7 Register CM1 CM1 CM0 Circuit specification Func...

Page 54: ...e program should periodically repeat the setting of the direction registers 2 Connect these unassigned pins to the MCU using the shortest wire length 2 cm or less possible 3 When the power on reset fu...

Page 55: ...etection 1 Voltage Detection 2 VCC monitor Voltage to monitor Vdet1 Vdet2 Detection target Passing through Vdet1 by rising or falling Passing through Vdet2 by rising or falling Monitor None VCA13 bit...

Page 56: ...oltage detection 2 signal Voltage detection 1 signal Internal reference voltage 1 2 1 2 1 2 Voltage detection 1 circuit VCA26 VCC Internal reference voltage Voltage detection 1 signal is held H when V...

Page 57: ...1b 10b 11b VW2C1 VW2C2 bit is set to 0 not detected by writing 0 by a program When VCA27 bit is set to 0 voltage detection 2 circuit disabled VW2C2 bit is set to 0 VW2C2 VW2C7 VW2C3 Watchdog timer blo...

Page 58: ...er Reset 4 Symbol Address Hardw are reset 00h VCA2 0032h Pow er on reset voltage monitor 1 reset 01000000b Bit Symbol Bit Name Function RW NOTES 1 2 3 4 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 b5 b0 Reser...

Page 59: ...set to 1 voltage detection 1 circuit enabled Set the VW1C0 bit to 0 disable w hen the VCA26 bit is set to 0 voltage detection 1 circuit disabled VW1C7 Voltage monitor 1 reset generation condition sele...

Page 60: ...bled The VW2C7 bit is enabled w hen the VW2C1 bit is set to 1 digital filter disabled mode Bits VW2C2 and VW2C3 remain unchanged after a softw are reset w atchdog timer reset or voltage monitor 2 VW2C...

Page 61: ...gital Filter A digital filter can be used for monitoring the VCC input voltage When the VW1C1 bit in the VW1C register is set to 0 digital filter enabled for the voltage monitor 1 circuit and the VW2C...

Page 62: ...set to 0 digital filter enabled Vdet1 Voltage monitor 1 reset VCC Sampling timing VW2C2 bit in VW2C register Vdet2 Voltage monitor 2 interrupt Voltage monitor 2 interrupt request 1 Set to 0 by a progr...

Page 63: ...t in the VW1C register to 1 digital filter disabled 5 1 Set the VW1C6 bit in the VW1C register to 1 voltage monitor 1 reset mode 6 Set the VW1C2 bit in the VW1C register to 0 7 Set the CM14 bit in the...

Page 64: ...age Monitor 2 Reset Voltage Monitor 2 Interrupt Voltage Monitor 2 Reset 1 Set the VCA27 bit in the VCA2 register to 1 voltage detection 2 circuit enabled 2 Wait for td E A 3 2 Select the sampling cloc...

Page 65: ...4 cycles VW2C2 bit 0 1 When the VW2C1 bit is set to 0 digital filter enabled VW2C2 bit 0 1 When the VW2C1 bit is set to 1 digital filter disabled and the VW2C7 bit is set to 0 Vdet2 or above VCA13 Bit...

Page 66: ...rite enable before rew riting the PM0 register The MCU is reset w hen this bit is set to 1 When read the content is 0 RW b7 b4 PM03 Softw are reset bit Nothing is assigned If necessary set to 0 When...

Page 67: ...1 Bus Cycles by Access Space of the R8C 18 Group Access Area Bus Cycle SFR 2 cycles of CPU clock ROM RAM 1 cycle of CPU clock Table 9 2 Bus Cycles by Access Space of the R8C 19 Group Access Area Bus...

Page 68: ...ications of Clock Generation Circuit Item Main Clock Oscillation Circuit On Chip Oscillator High Speed On Chip Oscillator Low Speed On Chip Oscillator Applications CPU clock source Peripheral function...

Page 69: ...Main clock Forcible discharge when OCD0 1 0 Charge discharge circuit Oscillation stop detection interrupt generation circuit detection Watchdog timer interrupt OCD2 bit switch signal CM14 bit switch s...

Page 70: ...order a Set bits OCD1 and OCD0 in the OCD register to 00b oscillation stop detection function disabled b Set the OCD2 bit to 1 selects on chip oscillator clock To input an external clock set the CM05...

Page 71: ...7 RW b7 b6 0 0 No division mode 0 1 Divide by 2 mode 1 0 Divide by 4 mode 1 1 Divide by 16 mode System clock division select bits 1 3 CM16 RW When the CM10 bit is set to 1 stop mode or the CM05 bit in...

Page 72: ...is automatically set to 1 on chip oscillator clock selected if a main clock oscillation stop is detected w hile bits OCD1 to OCD0 are set to 11b oscillation stop detection function enabled If the OCD3...

Page 73: ...llator on High speed on chip oscillator select bit 2 0 Selects low speed on chip oscillator 3 1 Selects high speed on chip oscillator Change the HRA01 bit under the follow ing conditions HRA00 1 high...

Page 74: ...HRA1 register to a higher value maximum value FFh results in a low er frequency High Speed On Chip Oscillator Control Register 2 1 Symbol Address After Reset HRA2 0022h 00h Bit Symbol Bit Name Functio...

Page 75: ...lock source set the OCD2 bit in the OCD register to 0 selects main clock after the main clock is oscillating stably The power consumption can be reduced by setting the CM05 bit in the CM0 register to...

Page 76: ...lying the necessary clock for the MCU The frequency of the low speed on chip oscillator varies depending on the supply voltage and the operating ambient temperature Application products must be design...

Page 77: ...he clock fi i 1 2 4 8 and 32 is generated by the system clock divided by i The clock fi is used for timers X Y Z and C the serial interface and the comparator When the WAIT instruction is executed aft...

Page 78: ...tched over the new clock source needs to be oscillating and stable If the new clock source is the main clock allow sufficient wait time in a program until oscillation is stabilized before exiting NOTE...

Page 79: ...on fRING S can be used for the watchdog timer and voltage detection circuit 10 4 1 3 High Speed and Low Speed On Chip Oscillator Modes The on chip oscillator clock divided by 1 no division 2 4 8 or 1...

Page 80: ...l function interrupts to be used for exiting wait mode Set bits ILVL2 to ILVL0 of the peripheral function interrupts that are not to be used for exiting wait mode to 000b interrupt disabled 2 Set the...

Page 81: ...exits stop mode by a hardware reset or peripheral function interrupt When using a hardware reset to exit stop mode set bits ILVL2 to ILVL0 for the peripheral function interrupts to 000b interrupts di...

Page 82: ...ait mode 6 Stop mode CM05 Bit in CM0 register CM10 CM13 CM14 Bits in CM1 register OCD2 Bit in OCD register HRA00 HRA01 Bits in HRA0 register C M 1 4 0 H R A 0 1 0 O C D 2 1 C M 1 3 1 C M 0 5 0 O C D 2...

Page 83: ...Procedure for Switching Clock Source from Low Speed On Chip Oscillator to Main Clock To enter wait mode while using the oscillation stop detection function set the CM02 bit to 0 peripheral function cl...

Page 84: ...ce Bit Showing Interrupt Cause Oscillation stop detection a or b a OCD3 bit in OCD register 1 b Bits OCD1 to OCD0 in OCD register 11b and OCD2 bit 1 Watchdog timer VW2C3 bit in VW2C register 1 Voltage...

Page 85: ...llation stop detection function disabled in this case 10 6 3 Oscillation Circuit Constants Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system 10 6...

Page 86: ...sters protected by PRC3 bit Registers VCA2 VW1C and VW2C Figure 11 1 PRCR Register Protect Register Symbol Address After Reset PRCR 000Ah 00h Bit Symbol Bit Name Function RW b2 Reserved bit Set to 0 R...

Page 87: ...interrupt enable flag I flag does not enable or disable interrupts The interrupt priority order cannot be changed based on interrupt priority level Interrupt non maskable interrupts Hardware Software...

Page 88: ...enerated when the BRK instruction is executed 12 1 2 4 INT Instruction Interrupt An INT instruction interrupt is generated when the INT instruction is executed The INT instruction can select software...

Page 89: ...details of the voltage detection circuit refer to 7 Voltage Detection Circuit 12 1 3 4 Single Step Interrupt and Address Break Interrupt Do not use these interrupts They are for use by development to...

Page 90: ...use these interrupts They are for use by development tools only Table 12 1 Fixed Vector Tables Interrupt Source Vector Addresses Address L to H Remarks Reference Undefined instruction 0FFDCh to 0FFDF...

Page 91: ...h to 0037h 13 12 3 Key Input Interrupt Comparator conversion 56 to 59 0038h to 003Bh 14 16 Comparator Reserved 15 Compare 1 64 to 67 0040h to 0043h 16 14 3 Timer C UART0 transmit 68 to 71 0044h to 004...

Page 92: ...Dh XXXXX000b ADIC 004Eh XXXXX000b CMP1IC 0050h XXXXX000b S0TIC S1TIC 0051h 0053h XXXXX000b S0RIC S1RIC 0052h 0054h XXXXX000b TXIC 0056h XXXXX000b TZIC 0058h XXXXX000b INT1IC 0059h XXXXX000b INT3IC 005...

Page 93: ...t request bit 0 Requests no interrupt 1 Requests interrupt RW 1 ILVL0 RW Interrupt priority level select bits b2 b1 b0 0 0 0 Level 0 interrupt disable 0 0 1 Level 1 0 1 0 Level 2 0 1 1 Level 3 1 0 0 L...

Page 94: ...tings of Interrupt Priority Levels and Table 12 4 lists the Interrupt Priority Levels Enabled by IPL The following are conditions under which an interrupt is acknowledged I flag 1 IR bit 1 Interrupt p...

Page 95: ...terrupt sequence 3 The I D and U flags in the FLG register are set as follows The I flag is set to 0 interrupts disabled The D flag is set to 0 single step interrupt disabled The U flag is set to 0 IS...

Page 96: ...dged interrupt is set in the IPL When a software interrupt or special interrupt request is acknowledged the level listed in Table 12 5 is set in the IPL Table 12 5 lists the IPL Value When Software or...

Page 97: ...on Stack SP SP value before interrupt is generated Previous stack contents LSB MSB Address Previous stack contents m 4 m 3 m 2 m 1 m m 1 Stack state before interrupt request is acknowledged SP New SP...

Page 98: ...xecuted the interrupt with the higher priority is acknowledged Set bits ILVL2 to ILVL0 to select the desired priority level for maskable interrupts peripheral functions However if two or more maskable...

Page 99: ...Level Judgement Circuit Compare 0 INT3 Timer Z Timer X INT0 Timer C INT1 UART1 receive Compare 1 Comparator conversion UART1 transmit Key input IPL Priority level of each interrupt Level 0 default val...

Page 100: ...filter select bits b7 b3 b2 Set to 0 0 RW Reserved bit Nothing is assigned If necessary set to 0 When read the content is 0 b1 b0 0 0 No filter 0 1 Filter w ith f1 sampling 1 0 Filter w ith f8 samplin...

Page 101: ...re 12 13 shows an Operating Example of INT0 Input Filter Figure 12 12 Configuration of INT0 Input Filter Figure 12 13 Operating Example of INT0 Input Filter INT0F0 INT0F1 Bits in INT0F register INT0EN...

Page 102: ...R0 _______ select bit NOTES 1 2 3 R0EDG RW 0 Rising edge 1 Falling edge TXUND RW RW TXMOD2 Operating mode select bit 2 0 Other than pulse period measurement mode 1 Pulse period measurement mode RW TXM...

Page 103: ...8 clock cycle Figure 12 15 shows the TCC0 Register and Figure 12 16 shows the TCC1 Register Figure 12 15 TCC0 Register Timer C Control Register 0 Symbol Address After Reset TCC0 009Ah 00h Bit Symbol B...

Page 104: ...three times continuously the input is determined Compare 1 output mode select bits 3 b7 b6 0 0 CMPoutput remains unchanged even w hen compare 1 is matched 0 1 CMPoutput is reversed w hen compare 1 sig...

Page 105: ...0 to K13 is not detected as interrupts Also when H is input to the KIi pin which sets the KIiPL bit to 1 rising edge input to the other pins K10 to K13 is not detected as interrupts Figure 12 17 shows...

Page 106: ...2 RW KI2EN RW KI1PL KI1 input polarity select bit 0 Falling edge 1 Rising edge KI2 input enable bit 0 Disable 1 Enable b7 b6 b5 b4 b1 b0 The IR bit in the KUPIC register may be set to 1 requests inter...

Page 107: ...Change the content of the stack and use the REIT instruction Use an instruction such as POP to restore the stack as it was before the interrupt request was acknowledged Then use a jump instruction Ta...

Page 108: ...he content is 0 b7 b6 b5 b4 0 Disable 1 Enable RW b3 b2 b1 b0 Address match interrupt 0 enable bit 0 Disable 1 Enable RW AIER1 Address match interrupt 1 enable bit AIER0 Address Match Interrupt Regist...

Page 109: ...ch has the highest priority among the enabled interrupts is set to 0 This may cause the interrupt to be canceled or an unexpected interrupt to be generated 12 5 2 SP Setting Set any value in the SP be...

Page 110: ...rces Figure 12 20 Example of Procedure for Changing Interrupt Sources NOTES 1 Execute the above settings individually Do not execute two or more settings at once by one instruction 2 Use the I flag fo...

Page 111: ...rupt not requested it may not be set to 0 depending on the instruction used Therefore use the MOV instruction to set the IR bit to 0 c When disabling interrupts using the I flag set the I flag as show...

Page 112: ...de Item Count Source Protection Mode Disabled Count Source Protection Mode Enabled Count source CPU clock Low speed on chip oscillator clock Count operation Decrement Reset condition of watchdog timer...

Page 113: ...ite to the OFS register w ith a program ROM code protect bit 0 ROM code protect enabled 1 ROM code protect disabled RW b6 b4 Reserved bits Set to 1 RW ROMCP1 b1 RW Reserved bit Set to 1 ROMCR ROM code...

Page 114: ...protection mode is disabled and 0FFFh w hen count source protection mode is enabled 2 Function Watchdog Timer Start Register Symbol Address After Reset WDTS 000Eh Undefined RW WO Function The w atchdo...

Page 115: ...lue of watchdog timer 32768 1 CPU clock n 16 or 128 selected by WDC7 bit in WDC register Example When the CPU clock frequency is 16 MHz and prescaler divides by 16 the period is approximately 32 8 ms...

Page 116: ...he OFS register 0FFFFh selects the operation of the watchdog timer after a reset When the WDTON bit is set to 1 watchdog timer is in stop state after reset The watchdog timer and prescaler stop after...

Page 117: ...apture and output compare Count Decrement Decrement Increment Count sources f1 f2 f8 fRING f1 f2 f8 Timer X underflow f1 f8 f32 fRING fast Function Timer mode Provided Provided Not provided Pulse outp...

Page 118: ...nt source and outputs pulses which invert the polarity by underflow of the timer Event counter mode The timer counts external pulses Pulse width measurement mode The timer measures the pulse width of...

Page 119: ...nding on operating mode RW TXMOD2 TXUND RW TXMOD0 RW Operating mode select bits 0 1 b1 b0 0 0 Timer mode or pulse period measurement mode 0 1 Pulse output mode 1 0 Event counter mode 1 1 Pulse w idth...

Page 120: ...ounts internal count source 00h to FFh Event counter mode Counts input pulses from external clock 00h to FFh RW Timer X Register Symbol Address After Reset TX 008Dh FFh Setting Range RW RW 00h to FFh...

Page 121: ...TX and PREX are written while the count is stopped values are written to both the reload register and counter When registers TX and PREX are written during the count the value is written to each reloa...

Page 122: ...the TXMR register Count stop condition 0 count stops is written to the TXS bit in the TXMR register Interrupt request generation timing When timer X underflows timer X interrupt INT10 CNTR00 pin funct...

Page 123: ...Timer X for precautions regarding the TXS bit RW TXUND RW TXEDG The IR bit in the INT1IC register may be set to 1 requests interrupt w hen the R0EDG bit is rew ritten Refer to 12 5 5 Changing Interru...

Page 124: ...ters TX and PREX are written while the count is stopped values are written to both the reload register and counter When registers TX and PREX are written during the count the value is written to each...

Page 125: ...is written to the TXS bit in the TXMR register Interrupt request generation timing When timer X underflows timer X interrupt Rising or falling of the CNTR0 input end of measurement period INT1 interr...

Page 126: ...ting mode select bits 0 1 b1 b0 1 1 Pulse w idth measurement mode TXMOD1 RW 1 1 TXMOD0 b7 b6 b5 b4 0 0 0 0 RW b3 b2 CNTR0 0 Measures L level w idth 1 Measures H level w idth TXS Timer X count start fl...

Page 127: ...he contents of PREX register Count start Count stop Underflow Count stop Count start Period TXS bit in TXMR register 1 0 Measured pulse CNTR0i pin input 1 0 IR bit in INT1IC register 1 0 IR bit in TXI...

Page 128: ...dition 1 count starts is written to the TXS bit in the TXMR register Count stop condition 0 count stops is written to the TXS bit in the TXMR register Interrupt request generation timing When timer X...

Page 129: ...ive edge not received 1 Active edge received Timer X underflow flag 0 No underflow 1 Underflow RW The IR bit in the INT1IC register may be set to 1 requests interrupt w hen the R0EDG bit is rew ritten...

Page 130: ...are both set to 1 if timer X underflows and reloads on an active edge simultaneously In this case the validity of the TXUND bit should be determined by the contents of the read out buffer 7 If the pre...

Page 131: ...Write 0 to bits TXEDG and TXUND before the count starts The TXEDG bit may be set to 1 by the prescaler X underflow generated after the count starts When using the pulse period measurement mode leave t...

Page 132: ...of a given width successively Programmable one shot generation mode The timer outputs a one shot pulse Programmable wait one shot generation mode The timer outputs a delayed one shot pulse Figure 14...

Page 133: ...mode NOTE 1 0 TZMOD0 Timer Z operating mode bits b5 b4 0 0 Timer mode 0 1 Programmable w aveform generation mode 1 0 Programmable one shot generation mode 1 1 Programmable w ait one shot generation mo...

Page 134: ...s of prescaler Z counts one shot w idth 00h to FFh WO Programmable one shot generation mode Disabled Programmable w aveform generation mode WO 2 Counts underflow of prescaler Z 1 00h to FFh Disabled...

Page 135: ...n w hich changes this register w hen the TZOS bit is set to 1 during count the TZOS bit is automatically set to 0 one shot stop if the count is completed w hile the instruction is being executed If th...

Page 136: ...tion RW NOTE 1 b7 b6 Timer X count source select bits 1 Do not sw itch count sources during a count operation Stop the timer count before sw itching count sources RW Timer Z count source select bits 1...

Page 137: ...m 1 fi Count source frequency n Value set in PREZ register m value set in TZPR register Count start condition 1 count starts is written to the TZS bit in the TZMR register Count stop condition 0 count...

Page 138: ...ion RW NOTES 1 2 Refer to 14 2 5 Notes on Timer Z for precautions regarding the TZS bit RW TZMOD0 RW b3 b0 Reserved bits Timer Z count start flag 2 0 Stops counting 1 Starts counting 0 RW RW 0 Set to...

Page 139: ...ow Count operations Decrement When the timer underflows it reloads the contents of the primary reload and secondary reload registers alternately before the count is continued Width and period of outpu...

Page 140: ...puts H w hen the timer is stopped RW INOSEG RW Set to 0 in programmable w aveform generation mode Set to 0 in programmable w aveform generation mode Timer Z Mode Register Symbol Address After Reset TZ...

Page 141: ...r Z TZOUT pin output IR bit in TZIC register Set to 1 by program Set to 0 by program Set to 0 when interrupt request is acknowledged or set by program Waveform output starts Prescaler Z underflow sign...

Page 142: ...pletes and the TZOS bit is set to 0 one shot stops When the count stops the timer reloads the contents of the reload register before it stops One shot pulse output time n 1 m 1 fi fi Count source freq...

Page 143: ...1 INT0 _____ pin one shot trigger enabled set bits INT0F0 to INT0F1 RW INOSEG RW RW TZOPL RW 0 Falling edge trigger 1 Rising edge trigger Reserved bits Set to 0 Timer Z output level latch 0 Outputs on...

Page 144: ...OPL bit in PUM register 0 INOSTG bit 1 INT0 one shot trigger enabled INOSEG bit 1 rising edge trigger Prescaler Z underflow signal Count starts Timer Z primary reloads Waveform output ends TZS bit in...

Page 145: ...fer to Table 14 10 Programmable Wait One Shot Generation Mode Specifications When a trigger is generated from that point the timer outputs a pulse only once for a given length of time equal to the val...

Page 146: ...t in PREZ register p value set in TZSC register Count start conditions Set the TZOS bit in the TZOC register to 1 one shot starts 1 Input active trigger to the INT0 pin 2 Count stop conditions When re...

Page 147: ...w hen the INT0PL bit in the INTEN register is set to 0 one edge RW INOSEG RW RW TZOPL RW 0 Falling edge trigger 1 Rising edge trigger Reserved bits Set to 0 Timer Z output level latch 0 Outputs one s...

Page 148: ...applies under the following conditions PREZ 01h TZPR 01h TZSC 02h PUM register TZOPL bit 0 INOSTG bit 1 INT0 one shot trigger enabled INOSEG bit 1 rising edge trigger Prescaler Z underflow signal Time...

Page 149: ...ion mode read the timer count value before the timer stops The TZS bit in the TZMR register has a function to instruct timer Z to start or stop counting and a function to indicate that the count has s...

Page 150: ...Diagram of Timer C 01b 10b f8 f1 11b f32 TCC11 to TCC10 Digital filter TM0 register Data bus INT3 interrupt Other than 00b 00b Edge detection TCC07 0 TCC07 1 fRING128 Lower 8 bits Capture and compare...

Page 151: ...1b TCC15 to TCC14 T TCC15 Compare 0 interrupt signal TCC16 TCC17 R Reset Compare 1 interrupt signal Reverse CMP output internal signal Inverted TCOUT6 0 PD1_0 TCOUT0 TCOUT6 1 TCOUT0 1 TCOUT0 0 CMP0_0...

Page 152: ...pare mode b8 b0 b15 b7 b0 b7 0000h to FFFFh RW Store the value compared w ith timer C Capture and Compare 0 Register Symbol Address After Reset TM0 009Dh 009Ch 0000h 2 RW Function Setting Range RW NOT...

Page 153: ...NT3 _____ interrupt is generated is synchronization w ith the clock for the digital filter RW Change this bit w hen the TCC00 bit is set to 0 count stops The IR bit in the INT3IC register may be set t...

Page 154: ...g 1 1 Filter w ith f32 sampling 0 Selects capture input capture mode 3 1 Selects compare 0 output output compare mode RW RW RW TCC15 TCC10 TCC13 Compare 0 capture select bit 2 TCC12 TCC14 b7 b6 b5 b4...

Page 155: ...1_0 to CMP1_2 1 Inverts CMP output from CMP1_0 to CMP1_2 b3 b2 0 Disables CMP output from CMP0_2 1 Enables CMP output from CMP0_2 b1 b0 TCOUT1 TCOUT0 b7 b6 b5 b4 RW TCOUT2 RW RW CMP output enable bit...

Page 156: ...en the count stops Count start condition The TCC00 bit in the TCC0 register is set to 1 count starts Count stop condition The TCC00 bit in the TCC0 register is set to 0 count stops Interrupt request g...

Page 157: ...3 bits 01b capture input polarity is set for falling edge TCC07 0 INT3 TCIN input as capture input trigger Measurement value1 Measurement value 2 Set to 1 by program Transmit measured value 1 The dela...

Page 158: ...rupt When a match occurs in compare circuit 1 compare 1 interrupt When time C overflows timer C interrupt INT3 TCIN pin function Programmable I O port or INT3 interrupt input P1_0 to P1_2 pins and P3_...

Page 159: ...level is set to high at compare 0 match occurrence TCC17 to TCC16 bits in TCC1 register 10b CMP output level is set to low at compare 1 match occurrence TCOUT6 bit in TCOUT register 0 not inverted TC...

Page 160: ...3 3 Notes on Timer C Access registers TC TM0 and TM1 in 16 bit units The TC register can be read in 16 bit units This prevents the timer value from being updated between when the low order bytes and...

Page 161: ...ARTi Figure 15 1 UARTi i 0 or 1 Block Diagram 01b f8 f1 10b CLK1 to CLK0 00b RXD0 f32 1 16 1 16 1 2 1 n0 1 UART reception UART transmission Clock synchronous type when internal clock is selected Clock...

Page 162: ...ata bus low order bits D7 D6 D5 D4 D3 D2 D1 D0 UiTB register D8 TXDi 1SP 2SP SP SP PAR UARTi transmit register 0 i 0 or 1 SP Stop bit PAR Parity bit NOTE 1 Clock synchronous type is implemented in UAR...

Page 163: ...rror 1 Overrun error RO RO FER Framing error flag 2 0 No framing error 1 Framing error RO PER Parity error flag 2 0 No parity error 1 Parity error Read out the UiRB register in 16 bit units Bits SUM P...

Page 164: ...5 b4 RW Serial interface mode select bits 2 b2 b1 b0 0 0 0 Serial interface disabled 0 0 1 Clock synchronous serial I O mode 1 0 0 UART mode transfer data 7 bits long 1 0 1 UART mode transfer data 8 b...

Page 165: ...Selects f1 0 1 Selects f8 1 0 Selects f32 1 1 Do not set UFORM Transfer format select bit 0 LSB first 1 MSB first RW Reserved bit CLK polarity select bit 0 Transmit data is output at falling edge of...

Page 166: ...ous receive mode UART1 transmit interrupt source select bit 0 Transmit buffer empty TI 1 1 Transmit completed TXEPT 1 b3 b2 b3 b1 b0 0 U0RRM CNTR0 signal pin select bit 1 U1SEL0 RW UART1 pin P3_7 TXD1...

Page 167: ...fi f1 f8 f32 n value set in U0BRG register 00h to FFh The CKDIR bit is set to 1 external clock input from CLK0 pin Transmit start conditions Before transmission starts the following requirements must...

Page 168: ...ck U0C0 CLK1 to CLK0 Select the count source in the U0BRG register TXEPT Transmit register empty flag NCH Select TXD0 pin output mode CKPOL Select the transfer clock polarity UFORM Select the LSB firs...

Page 169: ...nterrupt request is acknowledged or set by a program Write dummy data to U0TB register Transfer from U0TB register to UART0 transmit register 1 fEXT D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 Receive data...

Page 170: ...rising edge of the transfer clock D1 D2 NOTES 1 When not transferring the CLK0 pin level is H 2 When not transferring the CLK0 pin level is L D3 D4 D5 D6 D7 D0 RXD0 D1 D2 D3 D4 D5 D6 D7 CLK0 2 D0 TXD...

Page 171: ...ve Mode Continuous receive mode is selected by setting the U0RRM bit in the UCON register to 1 enables continuous receive mode In this mode reading the U0RB register sets the TI bit in the U0C1 regist...

Page 172: ...equired TE bit in UiC1 register is set to 1 transmission enabled TI bit in UiC1 register is set to 0 data in UiTB register Receive start conditions Before reception starts the following are required R...

Page 173: ...er odd or even UiC0 CLK0 CLK1 Select the count source for the UiBRG register TXEPT Transmit register empty flag NCH Select TXDi pin output mode CKPOL Set to 0 UFORM LSB first or MSB first can be selec...

Page 174: ...cause the TE bit is set to 0 D0 TXDi Write data to UiTB register Transfer from UiTB register to UARTi transmit register TC D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP SP ST D0 D1 ST...

Page 175: ...INT11 pin UiBRG output Set to 0 when interrupt request is accepted or set by a program Example of receive timing when transfer data is 8 bits long parity disabled one stop bit The above timing diagra...

Page 176: ...92 0 16 2400 f8 64 40h 2403 85 0 16 25 19h 2403 85 0 16 4800 f8 32 20h 4734 85 1 36 12 0Ch 4807 69 0 16 9600 f1 129 81h 9615 38 0 16 51 33h 9615 38 0 16 14400 f1 86 56h 14367 82 0 22 34 22h 14285 71...

Page 177: ...register is read bits PER and FER in the U0RB register and the RI bit in the U0C1 register are set to 0 Example when reading receive buffer register MOV W 00A6H R0 Read the U0RB register When writing...

Page 178: ...agram Figures 16 2 and 16 3 show the Associated Comparator Registers NOTE 1 The AD frequency must be 10 MHz or below Table 16 1 Comparator Performance Item Performance Comparator conversion method Com...

Page 179: ...AN8 P1_1 AN9 P1_2 AN10 P1_3 AN11 ADGSEL0 1 ADGSEL0 0 f4 ADCAP 1 Software trigger ADCAP 0 Trigger Comparator CH0 to CH2 ADGSEL0 and CKS0 Bits in ADCON0 register CKS1 VCUT Bits in ADCON1 register Timer...

Page 180: ...H0 to CH2 ADST Comparator conversion start flag 0 Disables comparator conversion 1 Starts comparator conversion RW ADCAP Comparator conversion automatic start bit 0 Starts at softw are trigger ADST bi...

Page 181: ...t used 1 Used RW b0 0 0 0 b3 b2 b1 Reserved bits Set to 0 b7 b6 b5 b4 Set to 0 RW If the ADCON2 register is rew ritten during comparator conversion the conversion result is undefined b0 Reserved bit N...

Page 182: ...The input voltage on one pin selected by bits CH2 to CH0 is comparator converted once Start conditions When the ADCAP bit is set to 0 software trigger set the ADST bit to 1 comparator conversion star...

Page 183: ...1 Starts comparator conversion RW To use the comparator set the ADGSEL0 bit to 1 When changing comparator conversion operating mode set the analog input pin again Set the AD frequency to 10 MHz or be...

Page 184: ...m Specification Function The Input voltage on one pin selected by bits CH2 to CH0 and the ADGSEL0 bit is comparator converted repeatedly Start conditions When the ADCAP bit is set to 0 software trigge...

Page 185: ...ion start flag 0 Disables comparator conversion 1 Starts comparator conversion RW CH1 RW CH0 ADCAP Comparator conversion automatic start bit 0 Starts at softw are trigger ADST bit 1 Starts at capture...

Page 186: ...conversion is completed and the AD register is read The IR bit in the ADIC register or the ADST bit in the ADCON0 register can determine whether the comparator conversion is completed To use in repea...

Page 187: ...ay that all blank areas are used before performing an erase operation Avoid rewriting only particular blocks and try to average out the programming and erasure endurance of the blocks It is also advis...

Page 188: ...written by executing software commands from the CPU EW0 mode Rewritable in any area other than flash memory EW1 mode Rewritable in flash memory User ROM area is rewritten by a dedicated serial program...

Page 189: ...it is set to 0 rewrite enabled block 1 is rewritable The rewrite control program for standard serial I O mode is stored in the boot ROM area before shipment The boot ROM area and the user ROM area sha...

Page 190: ...ck 1 is rewritable only for CPU rewrite mode 2 This area is for storing the boot program provided by Renesas Technology 02400h 02BFFh 0D000h User ROM area 0DFFFh 0E000h 0FFFFh 02400h 02BFFh Block 1 8...

Page 191: ...st of 8 bits of data each the areas of which beginning with the first byte are 00FFDFh 00FFE3h 00FFEBh 00FFEFh 00FFF3h 00FFF7h and 00FFFBh Write programs in which the ID codes are set at these address...

Page 192: ...standard serial I O mode Figure 17 4 OFS Register Option Function Select Register 1 Symbol Address Before Shipment OFS 0FFFFh FFh 2 Bit Symbol Bit Name Function RW Reserved bit NOTES 1 2 If the block...

Page 193: ...de Item EW0 Mode EW1 Mode Operating mode Single chip mode Single chip mode Areas in which a rewrite control program can be located User ROM area User ROM area Areas in which a rewrite control program...

Page 194: ...1 bit to 1 CPU rewrite mode enabled The FMR0 register can be used to determine when program and erase operations complete Do not execute the read status register command in EW1 mode To enable the eras...

Page 195: ...le erasing or programming in EW0 mode FMR00 bit not reset to 1 ready When entering on chip oscillator mode main clock stops Figure 17 11 shows a flowchart to be followed before and after entering on c...

Page 196: ...then the MCU enters program suspend mode Set the FMR42 bit to 0 program restart when the auto program operation restarts 17 4 2 13 FMR43 Bit When the auto erase operation starts the FMR43 bit is set...

Page 197: ...U rew rite mode enabled When setting the FMR01 bit to 0 CPU rew rite mode disabled the FMR02 bit is set to 0 disables rew rite This bit is set to 0 by executing the clear status command This bit is en...

Page 198: ...rew rite 1 Disables rew rite When the FMR01 bit is set to 1 CPU rew rite mode enabled bits FMR15 and FMR16 can be w ritten to To set this bit to 0 set it to 0 immediately after setting it first to 1...

Page 199: ...0 FMR40 FMR42 FMR44 b7 b6 b5 b4 RW RW Erase suspend function enable bit 1 0 Disables reading 1 Enables reading Reserved bit 0 Disable 1 Enable Erase suspend request bit 2 0 Erase restart 1 Erase suspe...

Page 200: ...ramming ends Erasure restarts Erasure ends FMR46 bit in FMR4 register FMR44 bit in FMR4 register FMR43 bit in FMR4 register 1 0 1 0 1 0 1 0 Check that the FMR43 bit is set to 1 during erasure executio...

Page 201: ...te the read array command 3 Execute software commands Write 0 to the FMR01 bit CPU rewrite mode disabled Jump to a specified address in the flash memory Rewrite control program NOTES 1 Select 5 MHz or...

Page 202: ...the clock source for the CPU clock Turn XIN off Process in on chip oscillator mode main clock stops Write 0 to the FMR01 bit CPU rewrite mode disabled Jump to a specified address in the flash memory O...

Page 203: ...ead array mode until another command is written the contents of multiple addresses can be read continuously 17 4 3 2 Read Status Register Command The read status register command is used to read the s...

Page 204: ...en the FMR02 bit in the FMR0 register is set to 0 rewriting disabled or the FMR02 bit is set to 1 rewrite enabled and the FMR15 bit in the FMR1 register is set to 1 rewriting disabled program commands...

Page 205: ...ck erase commands targeting block 0 are not acknowledged When the FMR16 bit is set to 1 rewriting disable the block erase commands targeting block 1 are not acknowledged Do not use the block erase com...

Page 206: ...1 REIT No Yes FMR41 1 FMR41 0 Access flash memory Start Write the command code 20h Write D0h to any block address FMR00 1 Full status check Block erase completed No Yes EW1 Mode FMR40 1 Maskable inte...

Page 207: ...status bits indicate the operating status of the flash memory SR7 is set to 0 busy during auto programming and auto erasure and is set to 1 ready at the same time the operation completes 17 4 4 2 Eras...

Page 208: ...on FMR07 SR5 FMR06 SR4 1 1 Command sequence error When a command is not written correctly When invalid data other than that which can be written in the second bus cycle of the block erase command is w...

Page 209: ...ted No Yes Yes No Yes No Command sequence error Erase error Program error Command sequence error Execute the clear status register command set these status flags to 0 Check if command is properly inpu...

Page 210: ...sts the Pin Functions Flash Memory Standard Serial I O Mode 3 Figure 17 16 shows Pin Connections for Standard Serial I O Mode 3 After processing the pins shown in Table 17 8 and rewriting the flash me...

Page 211: ...ceramic resonator or crystal oscillator between pins XIN and XOUT when connecting external oscillator Apply H and L or leave the pin open when using as input port P4_7 XOUT P4_7 input clock output I O...

Page 212: ...Serial I O Mode 3 NOTE 1 It is not necessary to connect an oscillating circuit when operating with the on chip oscillator clock VSS MODE Connect oscillator circuit 1 Package PLSP0020JB A Mode Setting...

Page 213: ...Mode 3 1 In this example modes are switched between single chip mode and standard serial I O mode by controlling the MODE input with a switch 2 Connecting an oscillator is necessary Set the main clock...

Page 214: ...ry Use a parallel programmer which supports this MCU Contact the manufacturer of the parallel programmer for more information and refer to the user s manual of the parallel programmer for details on h...

Page 215: ...located in ROM 2 Do not use a non maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0 Table 17 9 EW0 Mode Interrupts Mode Status When Maskab...

Page 216: ...to erasure is suspended after td SR ES and interrupt handing is executed Auto erasure can be restarted by setting the FMR41 bit in the FMR4 register to 0 erase restart after interrupt handing complete...

Page 217: ...ture 65 to 150 C Table 18 2 Recommended Operating Conditions Symbol Parameter Conditions Standard Unit Min Typ Max VCC Supply voltage 2 7 5 5 V AVCC Analog supply voltage VCC V VSS Supply voltage 0 V...

Page 218: ...r below 3 If AVcc is less than 4 2 V divided f1 and ensure the comparator conversion operating clock frequency AD is f1 2 or below Figure 18 1 Port P1 P3 and P4 Measurement Circuit Table 18 3 Comparat...

Page 219: ...e performing an erase operation For example when programming groups of 16 bytes the effective number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operati...

Page 220: ...er of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation It is also advisable to retain data on the erase count of each block and limit the number of er...

Page 221: ...setting the VCA27 bit in the VCA2 register to 0 4 Ensure that Vdet2 Vdet1 Table 18 6 Voltage Detection 1 Circuit Electrical Characteristics Symbol Parameter Condition Standard Unit Min Typ Max Vdet1 V...

Page 222: ...C tw por2 0s 3 100 ms Table 18 9 Reset Circuit Electrical Characteristics When Not Using Voltage Monitor 1 Reset Symbol Parameter Condition Standard Unit Min Typ Max Vpor1 Power on reset valid voltag...

Page 223: ...s during power on 3 Time until CPU clock supply starts after the interrupt is acknowledged to exit stop mode Table 18 10 High speed On Chip Oscillator Circuit Electrical Characteristics Symbol Paramet...

Page 224: ...IOH 500 A VCC 2 0 VCC V VOL Output L voltage Except P1_0 to P1_3 XOUT IOL 5 mA 2 0 V IOL 200 A 0 45 V P1_0 to P1_3 Drive capacity HIGH IOL 15 mA 2 0 V Drive capacity LOW IOL 5 mA 2 0 V Drive capacity...

Page 225: ...cillator off Low speed on chip oscillator on 125 kHz Divide by 8 3 mA XIN 10 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz Divide by 8 2 mA High speed on ch...

Page 226: ...ove Figure 18 6 TCIN Input INT3 Input Timing Diagram when VCC 5 V Table 18 14 XIN Input Symbol Parameter Standard Unit Min Max tc XIN XIN input cycle time 50 ns tWH XIN XIN input H width 25 ns tWL XIN...

Page 227: ...ter clock frequency x 3 or the minimum value of standard whichever is greater Figure 18 8 External Interrupt INT0 Input Timing Diagram when VCC 5 V Table 18 17 Serial Interface Symbol Parameter Standa...

Page 228: ...ve capacity LOW IOH 50 A VCC 0 5 VCC V VOL Output L voltage Except P1_0 to P1_3 XOUT IOL 1mA 0 5 V P1_0 to P1_3 Drive capacity HIGH IOL 2 mA 0 5 V Drive capacity LOW IOL 1 mA 0 5 V XOUT Drive capacity...

Page 229: ...tor off Low speed on chip oscillator on 125 kHz Divide by 8 2 5 mA XIN 10 MHz square wave High speed on chip oscillator off Low speed on chip oscillator on 125 kHz Divide by 8 1 6 mA High speed on chi...

Page 230: ...Figure 18 11 TCIN Input INT3 Input Timing Diagram when VCC 3 V Table 18 21 XIN Input Symbol Parameter Standard Unit Min Max tc XIN XIN input cycle time 100 ns tWH XIN XIN input H width 40 ns tWL XIN...

Page 231: ...ter clock frequency x 3 or the minimum value of standard whichever is greater Figure 18 13 External Interrupt INT0 Input Timing Diagram when VCC 3 V Table 18 24 Serial Interface Symbol Parameter Stand...

Page 232: ...cillation stop detection function disabled in this case 19 1 3 Oscillation Circuit Constants Ask the manufacturer of the oscillator to specify the best oscillation circuit constants for your system 19...

Page 233: ...ich has the highest priority among the enabled interrupts is set to 0 This may cause the interrupt to be canceled or an unexpected interrupt to be generated 19 2 2 SP Setting Set any value in the SP b...

Page 234: ...urces Figure 19 1 Example of Procedure for Changing Interrupt Sources NOTES 1 Execute the above settings individually Do not execute two or more settings at once by one instruction 2 Use the I flag fo...

Page 235: ...rrupt not requested it may not be set to 0 depending on the instruction used Therefore use the MOV instruction to set the IR bit to 0 c When disabling interrupts using the I flag set the I flag as sho...

Page 236: ...re undefined Write 0 to bits TXEDG and TXUND before the count starts The TXEDG bit may be set to 1 by the prescaler X underflow generated after the count starts When using the pulse period measurement...

Page 237: ...counting and a function to indicate that the count has started or stopped 0 count stops can be read until the following count source is applied after 1 count starts is written to the TZS bit while the...

Page 238: ...ister is read bits PER and FER in the U0RB register and the RI bit in the U0C1 register are set to 0 Example when reading receive buffer register MOV W 00A6H R0 Read the U0RB register When writing dat...

Page 239: ...conversion is completed and the AD register is read The IR bit in the ADIC register or the ADST bit in the ADCON0 register can determine whether the comparator conversion is completed To use in repea...

Page 240: ...ed in ROM 2 Do not use a non maskable interrupt while block 0 is being automatically erased because the fixed vector is allocated in block 0 Table 19 1 EW0 Mode Interrupts Mode Status When Maskable In...

Page 241: ...asure is suspended after td SR ES and interrupt handing is executed Auto erasure can be restarted by setting the FMR41 bit in the FMR4 register to 0 erase restart after interrupt handing completes Onc...

Page 242: ...t Control Registers During rigorous noise testing or the like external noise mainly power supply system noise can exceed the capacity of the MCU s internal noise control circuitry In such cases the co...

Page 243: ...use from addresses OC000h address to OC7FFh because the on chip debugger uses these addresses 3 Do not set the address match interrupt registers AIER RMAD0 and RMAD1 and fixed vector tables in a user...

Page 244: ...3 Max Nom Min Dimension in Millimeters Symbol Reference 6 6 6 5 6 4 D 4 5 4 4 4 3 E 1 15 A2 6 6 6 4 6 2 1 45 A 0 2 0 1 0 0 7 0 5 0 3 L 10 0 c 0 65 e 0 10 y HE A1 0 53 0 77 2 028 1 528 4 5 A1 b3 15 e 1...

Page 245: ...8 7 1 28 22 21 15 F 1 7 8 15 21 22 28 y E D bp Lp D2 E 1 Previous Code JEITA Package Code RENESAS Code PWQN0028KA B 28PJW B MASS Typ 0 05g P HWQFN28 5x5 0 50 0 7 0 6 0 5 0 25 0 2 0 15 Max Nom Min Dim...

Page 246: ...nection Example with E8 Emulator R0E000080KCE00 VSS VCC RXD 4 7 VSS 1 VCC 10 M16C flash starter M3A 0806 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 R8C 18 Group R8C 19 Group RXD TXD TXD RESET...

Page 247: ...3 Example of Oscillation Evaluation Circuit Appendix Figure 3 1 shows an Example of Oscillation Evaluation Circuit Appendix Figure 3 1 Example of Oscillation Evaluation Circuit VSS Connect oscillation...

Page 248: ...KUPIC 77 O OCD 57 OFS 98 177 P P1 33 P3 33 P4 33 PD1 33 PD3 33 PD4 33 PM0 51 PM1 51 PRCR 71 PREX 105 PREZ 119 PUM 120 PUR0 34 PUR1 34 R RMAD0 93 RMAD1 93 S S0RIC 77 S0TIC 77 S1RIC 77 S1TIC 77 T TC 137...

Page 249: ...evised 159 Table 16 1 is partly revised 160 Figure 16 1 is partly revised 161 Figure 16 2 is partly revised 164 Figure 16 4 is partly revised 166 Figure 16 5 is partly revised 199 Table 18 4 is partly...

Page 250: ...167 Figure 16 4 is partly revised 169 Figure 16 5 is partly revised 183 Figure 17 7 is partly revised 185 Figure 17 9 is partly revised 186 Figure 17 11 is partly revised 190 Figure 17 14 is partly r...

Page 251: ...ed 1 20 Nov 01 2005 3 Table 1 2 Performance Outline of the R8C 19 Group Flash Memory Data area Data flash Program area Program ROM revised 4 Figure 1 1 Block Diagram Peripheral Function added System C...

Page 252: ...ter Note 3 partly deleted 60 10 2 1 Low speed On Chip Oscillator Clock The application products to accommodate the frequency range The application products for the frequency change revised 10 2 2 High...

Page 253: ...Table 15 5 Registers to Be Used and Settings in UART Mode UiBRG 0 to 7 revised 162 Table 16 1 Performance of Comparator Analog Input Voltage 0V to Vref 0V to AVCC revised 171 Table 17 1 Flash Memory...

Page 254: ...t is set to 1 revised 225 Table 19 2 Interrupt in EW1 Mode During automatic programming program suspend function enabled and During automatic programming program suspend function disabled revised 227...

Page 255: ...OTE 2 added 182 Figure 17 5 NOTE 6 added 192 Table 17 5 Value after Reset revised 194 Figure 17 15 revised 204 205 Table 18 4 Table 18 5 Ta Ambient temperature Conditions VCC 5 0 V at Topr 25 C delete...

Page 256: ...19 Group Hardware Manual Publication Data Rev 0 10 Feb 15 2005 Rev 1 30 Apr 14 2006 Published by Sales Strategic Planning Div Renesas Technology Corp 2006 Renesas Technology Corp All rights reserved...

Page 257: ...2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan R8C 18 Group R8C 19 Group Hardware Manual...

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