R8C/18 Group, R8C/19 Group
Rev.1.30
Apr 14, 2006
Page 108 of 233
REJ09B0222-0130
Figure 14.5
TXMR Register in Pulse Output Mode
Timer X Mode Register
Symbol
Address
After Reset
TXMR
008Bh
00h
Bit Symbol
Bit Name
Function
RW
INT1
_____
/CNTR0 signal
polarity sw itch bit
(1)
P3_7/CNTR0
________
select bit
0 : Port P3_7
1 : CNTR0
________
output
NOTES:
1.
2. Refer to
14.1.6 Notes on Tim er X
for precautions regarding the TXS bit.
RW
TXUND
RW
TXEDG
The IR bit in the INT1IC register may be set to 1 (requests interrupt) w hen the R0EDG bit is rew ritten.
Refer to
12.5.5 Changing Interrupt Sources
.
TXMOD2
Set to 0 in pulse output mode.
Set to 0 in pulse output mode.
Set to 0 in pulse output mode.
RW
b3 b2
0 : CNTR0 signal output starts at “H”.
1 : CNTR0 signal output starts at “L”.
TXS
Timer X count start flag
(2)
0 : Stops counting.
1 : Starts counting.
b1 b0
0 0 0
b7 b6 b5 b4
TXMOD0
RW
Operating mode select bits 0, 1
b1 b0
0 1 : Pulse output mode
TXMOD1
RW
1
0
R0EDG
RW
RW
TXOCNT
RW
