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Corp. website (http://www.renesas.com).

REJ09B0250-0200

16

R8C/20 

Group

, R8C/21 

Group

Hardware Manual

RENESAS MCU

R8C FAMILY / R8C/2x SERIES

Rev.2.00
Revision Date: Aug 27, 2008

Summary of Contents for R8C FAMILY

Page 1: ...ation and is subject to change by Renesas Technology Corp without notice Please review the latest information published by Renesas Technology Corp through various means including the Renesas Technology Corp website http www renesas com REJ09B0250 0200 16 R8C 20 Group R8C 21 Group Hardware Manual RENESAS MCU R8C FAMILY R8C 2x SERIES Rev 2 00 Revision Date Aug 27 2008 ...

Page 2: ... such as safety systems or equipment or systems for transportation and traffic healthcare combustion control aerospace and aeronautics nuclear power or undersea communication transmission If you are considering the use of our products for such purposes please contact a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above 8 Notwithstand...

Page 3: ...s supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified 3 Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited The reserved addresses are provi...

Page 4: ...ails The following documents apply to the R8C 20 Group and R8C 21 Group Make sure to refer to the latest versions of these documents The newest versions of the documents listed may be obtained from the Renesas Technology Web site Document Type Description Document Title Document No Datasheet Hardware overview and electrical characteristics R8C 20 Group R8C 21 Group Datasheet REJ03B0120 Hardware ma...

Page 5: ...mpanied by the word register bit or pin to distinguish the three categories Examples the PM03 bit in the PM0 register P3_5 pin VCC pin 2 Notation of Numbers The indication b is appended to numeric values given in binary format However nothing is appended to the values of single bits The indication h is appended to numeric values given in hexadecimal format Nothing is appended to numeric values giv...

Page 6: ...lue Operation is not guaranteed when a value is set Function varies according to the operating mode The function of the bit varies with the peripheral function mode Refer to the register diagram for information on the individual modes XXX Register Symbol Address After Reset XXX XXX 00h Bit Name Bit Symbol RW b7 b6 b5 b4 b3 b2 b1 b0 XXX bits 1 0 XXX 0 1 XXX 1 0 Do not set 1 1 XXX b1 b0 XXX1 XXX0 XX...

Page 7: ...edance IEBus Inter Equipment Bus I O Input Output IrDA Infrared Data Association LSB Least Significant Bit MSB Most Significant Bit NC Non Connect PLL Phase Locked Loop PWM Pulse Width Modulation SIM Subscriber Identity Module UART Universal Asynchronous Receiver Transmitter VCO Voltage Controlled Oscillator All trademarks and registered trademarks are the property of their respective owners All t...

Page 8: ...er FLG 11 2 8 1 Carry Flag C 11 2 8 2 Debug Flag D 11 2 8 3 Zero Flag Z 11 2 8 4 Sign Flag S 11 2 8 5 Register Bank Select Flag B 11 2 8 6 Overflow Flag O 11 2 8 7 Interrupt Enable Flag I 12 2 8 8 Stack Pointer Select Flag U 12 2 8 9 Processor Interrupt Priority Level IPL 12 2 8 10 Reserved Bit 12 3 Memory 13 3 1 R8C 20 Group 13 3 2 R8C 21 Group 14 4 Special Function Registers SFRs 15 5 Resets 21 ...

Page 9: ...ck 72 10 3 CPU Clock and Peripheral Function Clock 73 10 3 1 System Clock 73 10 3 2 CPU Clock 73 10 3 3 Peripheral Function Clock f1 f2 f4 f8 and f32 73 10 3 4 fOCO 73 10 3 5 fOCO40M 73 10 3 6 fOCO F 73 10 3 7 fOCO S 73 10 3 8 fOCO128 73 10 4 Power Control 74 10 4 1 Standard Operating Mode 74 10 4 2 Wait Mode 75 10 4 3 Stop Mode 79 10 5 Oscillation Stop Detection Function 82 10 5 1 How to Use Osci...

Page 10: ...tection Mode Disabled 116 13 2 Count Source Protection Mode Enabled 117 14 Timers 118 14 1 Timer RA 120 14 1 1 Timer Mode 124 14 1 2 Pulse Output Mode 126 14 1 3 Event Counter Mode 128 14 1 4 Pulse Width Measurement Mode 130 14 1 5 Pulse Period Measurement Mode 133 14 1 6 Notes on Timer RA 136 14 2 Timer RB 137 14 2 1 Timer Mode 141 14 2 2 Programmable Waveform Generation Mode 144 14 2 3 Programma...

Page 11: ...6 2 6 Operation in 4 Wire Bus Communication Mode 304 16 2 7 SCS Pin Control and Arbitration 310 16 2 8 Notes on Clock Synchronous Serial I O with Chip Select 311 16 3 I2C Bus Interface 312 16 3 1 Transfer Clock 322 16 3 2 Interrupt Requests 323 16 3 3 I2C Bus Interface Mode 324 16 3 4 Clock Synchronous Serial Mode 335 16 3 5 Noise Canceller 338 16 3 6 Bit Synchronization Circuit 339 16 3 7 Example...

Page 12: ...05 19 7 1 CPU Rewrite Mode 405 20 Electrical Characteristics 408 21 Usage Notes 428 21 1 Notes on Clock Generation Circuit 428 21 1 1 Stop Mode 428 21 1 2 Wait Mode 428 21 1 3 Oscillation Stop Detection Function 428 21 1 4 Oscillation Circuit Constants 428 21 2 Notes on Interrupts 429 21 2 1 Reading Address 00000h 429 21 2 2 SP Setting 429 21 2 3 External Interrupt and Key Input Interrupt 429 21 2...

Page 13: ...sure against Noise and Latch up 451 21 9 2 Countermeasures against Noise Error of Port Control Registers 451 22 Notes on On Chip Debugger 452 23 Notes on Emulator Debugger 453 Appendix 1 Package Dimensions 454 Appendix 2 Connection Examples between Serial Writer and On Chip Debugging Emulator 455 Appendix 3 Example of Oscillation Evaluation Circuit 456 Index 457 ...

Page 14: ...A2 31 70 0033h 0034h 0035h 0036h Voltage Monitor 1 Circuit Control Register VW1C 32 0037h Voltage Monitor 2 Circuit Control Register VW2C 33 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh Address Register Symbol Page 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h Timer RD0 Interrupt Control Register TRD0IC 93 0049h Timer RD1 Interrupt Control Register TRD1IC 93 004Ah Timer RE Interrupt Con...

Page 15: ...BCh SS Status Register IIC Bus Status Register SSSR ICSR 289 319 00BDh SS Mode Register 2 Slave Address Register SSMR2 SAR 290 320 00BEh SS Transmit Data Register IIC Bus Transmit Data Register SSTDR ICDRT 291 320 00BFh SS Receive Data Register IIC Bus Receive Data Register SSRDR ICDRR 291 321 Address Register Symbol Page 00C0h A D Register AD 363 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00...

Page 16: ...13Fh Timer RD Digital Filter Function Select Register 1 TRDDF1 175 Address Register Symbol Page 0140h Timer RD Control Register 0 TRDCR0 176 191 206 218 229 243 0141h Timer RD I O Control Register A0 TRDIORA0 177 192 0142h Timer RD I O Control Register C0 TRDIORC0 178 193 0143h Timer RD Status Register 0 TRDSR0 179 194 207 219 230 244 0144h Timer RD Interrupt Enable Register 0 TRDIER0 180 195 208 ...

Page 17: ... operates using sophisticated instructions featuring a high level of instruction efficiency With 1 Mbyte of address space it is capable of executing instructions at high speed This Furthermore the data flash 1 KB x 2 blocks is embedded in the R8C 21 Group The difference between R8C 20 and R8C 21 Groups is only the existence of the data flash Their peripheral functions are the same 1 1 Applications...

Page 18: ...ronous I O UART 1 channel UART1 UART Clock synchronous serial interface 1 channel I2C bus interface 2 Clock synchronous serial I O with chip select LIN module Hardware LIN 1 channel timer RA UART0 A D converter 10 bit A D converter 1 circuit 12 channels Watchdog timer 15 bits x 1 channel with prescaler Reset start selectable Interrupt Internal 11 sources External 5 sources Software 4 sources Prior...

Page 19: ...lock synchronous serial I O with chip select LIN module Hardware LIN 1 channel Timer RA UART0 A D converter 10 bit A D converter 1 circuit 12 channels Watchdog timer 15 bits x 1 channel with prescaler Reset start selectable Interrupts Internal 11 sources External 5 sources Software 4 sources Priority level 7 levels Clock generation circuits 2 circuits XIN clock generation circuit with on chip feed...

Page 20: ...ration circuit XIN XOUT High speed on chip oscillator Low speed on chip oscillator UART or clock synchronous serial I O 8 bits 1 channel Memory Watchdog timer 15 bits ROM 1 RAM 2 Multiplier R0H R0L R1H R2 R3 R1L A0 A1 FB SB USP ISP INTB PC FLG I O port NOTES 1 ROM size depends on MCU type 2 RAM size depends on MCU type I2 C bus interface or clock synchronous serial I O with chip select 8 bits 1 ch...

Page 21: ...ry version R5F21207JFP 48 Kbytes 2 5 Kbytes PLQP0048KB A R5F21208JFP 64 Kbytes 3 Kbytes PLQP0048KB A R5F2120AJFP 96 Kbytes 5 Kbytes PLQP0048KB A R5F2120CJFP 128 Kbytes 1 6 Kbytes PLQP0048KB A R5F21206KFP 32 Kbytes 2 Kbytes PLQP0048KB A K version R5F21207KFP 48 Kbytes 2 5 Kbytes PLQP0048KB A R5F21208KFP 64 Kbytes 3 Kbytes PLQP0048KB A R5F2120AKFP 96 Kbytes 5 Kbytes PLQP0048KB A R5F2120CKFP 128 Kbyt...

Page 22: ... Kbytes PLQP0048KB A R5F2121AJFP 96 Kbytes 1 Kbyte X 2 5 Kbytes PLQP0048KB A R5F2121CJFP 128 Kbytes 1 1 Kbyte X 2 6 Kbytes PLQP0048KB A R5F21216KFP 32 Kbytes 1 Kbyte X 2 2 Kbytes PLQP0048KB A K version R5F21217KFP 48 Kbytes 1 Kbyte X 2 2 5 Kbytes PLQP0048KB A R5F21218KFP 64 Kbytes 1 Kbyte X 2 3 Kbytes PLQP0048KB A R5F2121AKFP 96 Kbytes 1 Kbyte X 2 5 Kbytes PLQP0048KB A R5F2121CKFP 128 Kbytes 1 1 K...

Page 23: ...DCLK P1_7 TRAIO INT1 P1_6 CLK0 P1_5 RXD0 TRAIO INT1 2 P1_4 TXD0 P1_3 KI3 AN11 12 P2_7 TRDIOD1 11 VCC AVCC 10 P4_6 XIN 9 VSS AVSS 8 1 P4_7 XOUT 7 RESET 6 P4_4 5 P4_3 4 MODE 3 P3_4 SDA SCS 2 P3_3 SSI 1 P3_5 SCL SSCK 25 26 27 28 29 30 31 32 33 34 35 36 P4_5 INT0 P6_6 INT2 TXD1 P6_7 INT3 RXD1 P1_2 KI2 AN10 P1_1 KI1 AN9 P1_0 KI0 AN8 P3_1 TRBO P3_0 TRAO P6_5 P6_4 P6_3 P0_7 AN0 Pin assignments top view P...

Page 24: ...ut pins Key Input Interrupt KI0 to KI3 I Key input interrupt input pins Timer RA TRAIO I O Timer RA I O pin TRAO O Timer RA output pin Timer RB TRBO O Timer RB output pin Timer RD TRDIOA0 TRDIOA1 TRDIOB0 TRDIOB1 TRDIOC0 TRDIOC1 TRDIOD0 TRDIOD1 I O Timer RD I O ports TRDCLK I External clock input pin Timer RE TREO O Divided clock output pin Serial Interface CLK0 I O Transfer clock I O pin RXD0 RXD1...

Page 25: ... SCS SDA 4 MODE 5 P4_3 6 P4_4 7 RESET 8 XOUT P4_7 9 VSS AVSS 10 XIN P4_6 11 VCC AVCC 12 P2_7 TRDIOD1 13 P2_6 TRDIOC1 14 P2_5 TRDIOB1 15 P2_4 TRDIOA1 16 P2_3 TRDIOD0 17 P2_2 TRDIOC0 18 P2_1 TRDIOB0 19 P2_0 TRDIOA0 TRDCLK 20 P1_7 INT1 TRAIO 21 P1_6 CLK0 22 P1_5 INT1 1 TRAIO 1 RXD0 23 P1_4 TXD0 24 P1_3 KI3 AN11 25 P4_5 INT0 INT0 26 P6_6 INT2 TXD1 27 P6_7 INT3 RXD1 28 P1_2 KI2 AN10 29 P1_1 KI1 AN9 30 ...

Page 26: ...L FB Frame base registers 1 The 4 high order bits of INTB are INTBH and the 16 low order bits of INTB are INTBL Interrupt table register b19 b0 USP Program counter ISP SB User stack pointer Interrupt stack pointer Static base register PC FLG Flag register Carry flag Debug flag Zero flag Sign flag Register bank select flag Overflow flag Interrupt enable flag Stack pointer select flag Reserved area ...

Page 27: ... bit register indicates the start address of an interrupt vector table 2 5 Program Counter PC PC 20 bits wide indicates the address of an instruction to be executed 2 6 User Stack Pointer USP and Interrupt Stack Pointer ISP The stack pointer SP USP and ISP are 16 bits wide each The U flag of FLG is used to switch between USP and ISP 2 7 Static Base Register SB SB is a 16 bit register for SB relati...

Page 28: ...Stack Pointer Select Flag U ISP is selected when the U flag is set to 0 USP is selected when the U flag is set to 1 The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed 2 8 9 Processor Interrupt Priority Level IPL IPL 3 bits wide assigns processor interrupt priority levels from level 0 to level 7 If a requ...

Page 29: ...R which have nothing allocated are reserved for future user and cannot be accessed by users Figure 3 1 Memory Map of R8C 20 Group Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer oscillation stop detection voltage detection Address break Reserved Reset FFFFFh 0FFFFh 0YYYYh 0XXXXh 00400h 002FFh 00000h Internal ROM program ROM Internal RAM SFR Refer to 4 Specia...

Page 30: ...e nothing allocated are reserved for future use and cannot be accessed by users Figure 3 2 Memory Map of R8C 21 Group Undefined instruction Overflow BRK instruction Address match Single step Watchdog timer oscillation stop detection voltage detection Address break Reserved Reset FFFFFh 0FFFFh 0YYYYh 0XXXXh 00400h 002FFh 00000h Internal ROM program ROM Internal RAM SFR Refer to 4 Special Function R...

Page 31: ...de Register 0 PM0 00h 0005h Processor Mode Register 1 PM1 00h 0006h System Clock Control Register 0 CM0 01101000b 0007h System Clock Control Register 1 CM1 00100000b 0008h 0009h 000Ah Protect Register PRCR 00h 000Bh 000Ch Oscillation Stop Detection Register OCD 00000100b 000Dh Watchdog Timer Reset Register WDTR XXh 000Eh Watchdog Timer Start Register WDTS XXh 000Fh Watchdog Timer Control Register ...

Page 32: ...upt Control Register IIC Bus Interrupt Control Register 2 SSUIC IICIC XXXXX000b 0050h 0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b 0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b 0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b 0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b 0055h INT2 Interrupt Control Register INT2IC XX00X000b 0056h...

Page 33: ...Buffer Register U0RB XXh 00A7h XXh 00A8h UART1 Transmit Receive Mode Register U1MR 00h 00A9h UART1 Bit Rate Register U1BRG XXh 00AAh UART1 Transmit Buffer Register U1TB XXh 00ABh XXh 00ACh UART1 Transmit Receive Control Register 0 U1C0 00001000b 00ADh UART1 Transmit Receive Control Register 1 U1C1 00000010b 00AEh UART1 Receive Buffer Register U1RB XXh 00AFh XXh 00B0h 00B1h 00B2h 00B3h 00B4h 00B5h ...

Page 34: ... P0 Register P0 XXh 00E1h Port P1 Register P1 XXh 00E2h Port P0 Direction Register PD0 00h 00E3h Port P1 Direction Register PD1 00h 00E4h Port P2 Register P2 XXh 00E5h Port P3 Register P3 XXh 00E6h Port P2 Direction Register PD2 00h 00E7h Port P3 Direction Register PD3 00h 00E8h Port P4 Register P4 XXh 00E9h 00EAh Port P4 Direction Register PD4 00h 00EBh 00ECh Port P6 Register P6 XXh 00EDh 00EEh P...

Page 35: ...r TRBSC FFh 010Eh Timer RB Primary TRBPR FFh 010Fh 0110h 0111h 0112h 0113h 0114h 0115h 0116h 0117h 0118h Timer RE Counter Data Register TRESEC 00h 0119h Timer RE Compare Data Register TREMIN 00h 011Ah 011Bh 011Ch Timer RE Control Register 1 TRECR1 00h 011Dh Timer RE Control Register 2 TRECR2 00h 011Eh Timer RE Count Source Select Register TRECSR 00001000b 011Fh 0120h 0121h 0122h 0123h 0124h 0125h ...

Page 36: ... TRDGRB0 FFh 014Bh FFh 014Ch Timer RD General Register C0 TRDGRC0 FFh 014Dh FFh 014Eh Timer RD General Register D0 TRDGRD0 FFh 014Fh FFh 0150h Timer RD Control Register 1 TRDCR1 00h 0151h Timer RD I O Control Register A1 TRDIORA1 10001000b 0152h Timer RD I O Control Register C1 TRDIORC1 10001000b 0153h Timer RD Status Register 1 TRDSR1 11000000b 0154h Timer RD Interrupt Enable Register 1 TRDIER1 1...

Page 37: ...VCC rises Voltage monitor 1 reset 1 VCC falls monitor voltage Vdet1 Voltage monitor 2 reset 1 VCC falls monitor voltage Vdet2 Watchdog timer reset Underflow of watchdog timer Software reset Write 1 to PM03 bit in PM0 register RESET Voltage monitor 1 reset SFR VCA26 VW1C0 and VW1C6 bits SFR VCA13 VCA27 VW1C1 VW1F0 VW1F1 VW1C7 VW2C2 and VW2C3 bits Pin CPU and SFR bits other than those listed above V...

Page 38: ...ctions P0 P1 P2 Input port P3_0 P3_1 P3_3 to P3_5 P3_7 Input port P4_2 to P4_7 Input port P6 Input port b19 b0 Interrupt table register INTB Program counter PC User stack pointer USP Interrupt stack pointer ISP Static base register SB Content of addresses 0FFFEh to 0FFFCh Flag register FLG C IPL D Z S B O I U b15 b0 b15 b0 b15 b0 b8 b7 b15 b0 0000h 0000h 0000h 0000h 0000h 0000h 0000h Data register...

Page 39: ...ON Watchdog timer start select bit 0 Starts w atchdog timer automatically after reset 1 Watchdog timer is inactive after reset RW ROMCR ROM code protect disabled bit 0 ROM code protect disabled 1 ROMCP1 enabled RW ROMCP1 ROM code protect bit 0 ROM code protect enabled 1 ROM code protect disabled RW RW b5 b4 Reserved bits Set to 1 RW If the block including the OFS register is erased FFh is set to t...

Page 40: ...nction Registers SFRs for the status of the SFR after reset The internal RAM is not reset If the RESET pin is pulled L during writing to the internal RAM the internal RAM will be in indeterminate state Figure 5 5 shows the Example of Hardware Reset Circuit and Operation and Figure 5 6 shows the Example of Hardware Reset Circuit Usage Example of External Supply Voltage Detection Circuit and Operati...

Page 41: ...re Reset Circuit Usage Example of External Supply Voltage Detection Circuit and Operation RESET VCC VCC RESET 2 7 V 0 V 0 2 VCC or below 0 V NOTE 1 Refer to 20 Electrical Characteristics td P R 10 µs or more RESET VCC VCC RESET 2 7 V 0 V 0 V 5 V 5 V Example when VCC 5 V Power supply voltage detection circuit NOTE 1 Refer to 20 Electrical Characteristics td P R 10 µs or more ...

Page 42: ...s enabled after power on reset Figure 5 7 shows the Example of Power On Reset Circuit and Operation NOTE 1 When using power on reset function set the LVD1ON bit to 0 voltage monitor 1 reset enabled after reset Figure 5 7 Example of Power On Reset Circuit and Operation 32 1 fOCO S Vdet1 3 Vpor1 tw por1 Vdet1 3 Vpor2 2 0 V trth trth External power Vcc NOTES 1 When using the voltage monitor 1 digital...

Page 43: ...f voltage monitor 1 reset 5 4 Voltage Monitor 2 Reset A reset is applied using the on chip voltage detection 2 circuit The voltage detection 2 circuit monitors the input voltage to the VCC pin The voltage to monitor is Vdet2 When the input voltage to the VCC pin drops to the Vdet2 level or below the pins CPU and SFR are reset and the program is executed beginning with the address indicated by the ...

Page 44: ...1 Voltage Detection 2 VCC Monitor Voltage to monitor Vdet1 Vdet2 Detection target Whether passing through Vdet1 by rising or falling Whether passing through Vdet2 by rising or falling Monitor None VCA13 bit in VCA1 register Whether VCC is higher or lower than Vdet2 Process When Voltage Is Detected Reset Voltage monitor 1 reset Voltage monitor 2 reset Reset at Vdet1 VCC Restart CPU operation at VCC...

Page 45: ...ltage detection 2 signal Voltage detection 1 signal Internal reference voltage 1 2 1 2 1 2 Voltage detection 1 circuit VCA26 VCC Internal reference voltage Voltage detection 1 signal is held H when VCA26 bit is set to 0 disabled Voltage detection 1 signal fOCO S VW1F1 to VW1F0 00b 01b 10b 11b VW1C7 VW1C6 Voltage monitor 1 reset generation circuit VW1C0 to VW1C1 VW1F0 to VW1F1 VW1C6 VW1C7 Bits in V...

Page 46: ... VW2C2 bit is set to 0 not detected by writing 0 by program When VCA27 bit is set to 0 voltage detection 2 circuit disabled VW2C2 bit is set to 0 VW2C7 VW2C3 Watchdog timer block Watchdog timer underflow signal This bit is set to 0 not detected by writing 0 by program Voltage monitor 2 interrupt reset generation circuit VW2C0 to VW2C3 VW2F2 VW2F1 VW2C6 VW2C7 Bits in VW2C register VCA13 Bit in VCA1...

Page 47: ...Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit VCA20 Internal pow er low consumption enable bit 5 0 Disables low consumption 1 Enables low consumption RW When using the voltage monitor 2 interrupt reset or the VCA13 bit in the VCA1 register set the VCA27 bit to 1 After the VCA27 bit is from 0 to 1 the voltage detection circuit elapses for td E A before starting operation...

Page 48: ...ampling clock select bits b5 b4 0 0 fOCO S divide by 1 0 1 fOCO S divide by 2 1 0 fOCO S divide by 4 1 1 fOCO S divide by 8 VW1F0 RW When read the content is undefined RO VW1C6 Voltage monitor 1 circuit mode select bit When the VW1C0 bit is set to 1 enables voltage monitor 1 reset set to 1 RW VW1C7 Voltage monitor 1 reset generation condition select bit 4 When the VW1C1 bit is set to 1 digital fil...

Page 49: ... Vdet2 or above 1 When VCC reaches Vdet2 or below RW When the VW2C6 bit is set to 1 voltage monitor 2 reset mode set the VW2C7 bit to 1 w hen VCC reaches to Vdet2 or below do not set to 0 Set the PRC3 bit in the PRCR register to 1 enables w riting before w riting to the VW2C register When w riting the VW2C register the VW2C2 bit may be set to 1 Set the VW2C2 bit to 0 after w riting the VW2C regist...

Page 50: ...0200 6 1 VCC Input Voltage 6 1 1 Monitoring Vdet1 Vdet1 cannot be monitored 6 1 2 Monitoring Vdet2 Set the VCA27 bit in the VCA2 register to 1 voltage detection 2 circuit enabled After td E A has elapsed refer to 20 Electrical Characteristics Vdet2 can be monitored by the VCA13 bit in the VCA1 register ...

Page 51: ...Set the VW1C1 bit in the VW1C register to 1 digital filter disabled 5 1 Set the VW1C6 bit in the VW1C register to 1 voltage monitor 1 reset mode 6 Set the VW1C2 bit in the VW1C register to 0 7 Set the CM14 bit in the CM1 register to 0 low speed on chip oscillator on 8 Wait for the sampling clock of the digital filter x 4 cycles no wait time 9 Set the VW1C0 bit in the VW1C register to 1 enables vol...

Page 52: ...Reset Voltage Monitor 2 Interrupt Voltage Monitor 2 Reset 1 Set the VCA27 bit in the VCA2 register to 1 voltage detection 2 circuit enabled 2 Wait for td E A 3 Select the sampling clock of the digital filter by the VW2F0 to VW2F1 bits in the VW2C register Select the timing of the interrupt and reset request by the VW2C7 bit in the VW2C register 1 4 2 Set the VW2C1 bit in the VW2C register to 0 dig...

Page 53: ...ycles VW2C2 bit 0 1 When the VW2C1 bit is set to 0 digital filter enabled VW2C2 bit 0 1 When the VW2C1 bit is set to 1 digital filter disabled and the VW2C7 bit is set to 0 Vdet2 or above VCA13 Bit in VCA1 register VW2C1 VW2C2 VW2C6 VW2C7 Bit in VW2C register Set to 0 by interrupt request acknowledgement Set to 0 by a program Voltage monitor 2 interrupt request VW2C6 0 Voltage monitor 2 interrupt ...

Page 54: ...pin state Figures 7 1 to 7 7 show the Configurations of Programmable I O Ports Table 7 2 lists the Functions of Programmable I O Ports Also Figure 7 9 shows the PDi i 0 to 4 and 6 Registers Figure 7 10 shows the Pi i 0 to 4 and 6 Registers Figure 7 11 shows the Registers PUR0 and PUR1 and Figure 7 12 shows the PMR Register i 0 to 4 6 j 0 to 7 NOTE 1 Nothing is assigned to bits PD3_2 PD3_6 PD4_0 to...

Page 55: ... as I O Ports for Peripheral Functions i 0 to 4 6 j 0 to 7 Refer to descriptions of each function for how to set peripheral functions 7 3 Pins Other than Programmable I O Ports Figure 7 8 shows the Configuration of I O Pins Table 7 3 Setting of PDi_j Bit when Functioning as I O Ports for Peripheral Functions i 0 to 4 6 j 0 to 7 I O of Peripheral Functions PDi_j Bit Setting of Port shared with Pin ...

Page 56: ...ral function Analog input Port latch Data bus Pull up selection Input to each peripheral function P1_4 1 Port latch Data bus Pull up selection Output from each peripheral function P0 Port latch Direction register Data bus Pull up selection Analog input Direction register Direction register 1 NOTE 1 symbolizes a parasitic diode Ensure the input voltage on each port will not exceed VCC 1 1 1 1 1 ...

Page 57: ...l function INT1 input Digital filter Input to each peripheral function P1_5 and P1_7 Port latch Data bus Pull up selection Direction register P1_6 and P2 Port latch Data bus Pull up selection Input to each peripheral function 1 Output from each peripheral function Direction register 1 NOTE 1 symbolizes a parasitic diode Ensure the input voltage on each port will not exceed VCC 1 1 1 ...

Page 58: ...3 to P3_5 and P3_7 1 Port latch Data bus Pull up selection Input to each peripheral function Output from each peripheral function Direction register P3_0 and P3_1 Port latch Data bus Pull up selection 1 Output from each peripheral function Direction register 1 NOTE 1 symbolizes a parasitic diode Ensure the input voltage on each port will not exceed VCC 1 1 1 ...

Page 59: ...age 43 of 458 REJ09B0250 0200 Figure 7 4 Configuration of Programmable I O Ports 4 P4_3 and P4_4 Port latch Data bus Pull up selection P4_2 VREF Data bus Direction register 1 NOTE 1 symbolizes a parasitic diode Ensure the input voltage on each port will not exceed VCC 1 1 1 ...

Page 60: ...atch Data bus Pull up selection Digital filter P4_6 XIN Data bus Clocked inverter 2 P4_7 XOUT Data bus 3 NOTES 1 symbolizes a parasitic diode Ensure the input voltage on each port will not exceed VCC 2 When CM05 1 CM10 1 or CM13 0 the clocked inverter is cutoff 3 When CM10 1 or CM13 0 the feedback resistor is unconnected 4 When CM05 CM13 1 or CM10 CM13 1 this pin is pulled up 4 Direction register ...

Page 61: ... Configuration of Programmable I O Ports 6 P6_1 to P6_5 Port latch Data bus Pull up selection P6_0 1 Port latch Direction register Data bus Pull up selection Output from each peripheral function Direction register 1 NOTE 1 symbolizes a parasitic diode Ensure the input voltage on each port will not exceed VCC 1 1 1 ...

Page 62: ...s 7 P6_7 P6_6 INT2 input Port latch Data bus Pull up selection Digital filter 1 Output from each peripheral function Direction register INT3 input Port latch Data bus Pull up selection Digital filter Direction register Input to each peripheral function 1 NOTE 1 symbolizes a parasitic diode Ensure the input voltage on each port will not exceed VCC 1 1 1 ...

Page 63: ... O Ports Rev 2 00 Aug 27 2008 Page 47 of 458 REJ09B0250 0200 Figure 7 8 Configuration of I O Pins MODE MODE signal input RESET RESET signal input 1 NOTE 1 symbolizes a parasitic diode Ensure the input voltage on each port will not exceed VCC 1 ...

Page 64: ...de When read its content is 0 PDi_7 Port Pi_7 direction bit RW Nothing is assigned to the PD3_2 and PD3_6 bits in the PD3 register When w riting to the PD3_2 and PD3_6 bits w rite 0 input mode When read its content is 0 Port Pi Register i 0 to 4 6 1 2 Symbol Address After Reset P0 00E0h Indeterminate P1 00E1h Indeterminate P2 00E4h Indeterminate P3 00E5h Indeterminate P4 00E8h Indeterminate P6 00E...

Page 65: ...RW P2_0 to P2_3 pull up 1 PU04 RW Pull Up Control Register 1 Symbol Address After Reset PUR1 00FDh XX00XX00b Bit Symbol Bit Name Function RW NOTE 1 RW PU14 P6_0 to P6_3 pull up 1 RW 0 Not pulled up 1 Pulled up b0 When this bit is set to 1 pulled up and the pin w hose direct bit is set to 0 input mode the pin is pulled up b3 b2 0 b1 0 b7 b6 b5 b4 b7 b6 Nothing is assigned If necessary set to 0 When...

Page 66: ...2 CH1 CH0 ADGSEL0 Setting value 0 X X X X Input port 1 1 X X X X Output port 0 1 1 1 0 A D converter input AN7 Table 7 5 Port P0_1 AN6 Register PD0 ADCON0 Function Bit PD0_1 CH2 CH1 CH0 ADGSEL0 Setting value 0 X X X X Input port 1 1 X X X X Output port 0 1 1 0 0 A D converter input AN6 Table 7 6 Port P0_2 AN5 Register PD0 ADCON0 Function Bit PD0_2 CH2 CH1 CH0 ADGSEL0 Setting value 0 X X X X Input ...

Page 67: ...0 0 1 0 0 A D converter input AN2 Table 7 10 Port P0_6 AN1 Register PD0 ADCON0 Function Bit PD0_6 CH2 CH1 CH0 ADGSEL0 Setting value 0 X X X X Input port 1 1 X X X X Output port 0 0 0 1 0 A D converter input AN1 Table 7 11 Port P0_7 AN0 Register PD0 ADCON0 Function Bit PD0_7 CH2 CH1 CH0 ADGSEL0 Setting value 0 X X X X Input port 1 1 X X X X Output port 0 0 0 0 0 A D converter input AN0 Table 7 12 P...

Page 68: ... X X X KI2 input 0 X 1 1 0 1 A D converter input AN10 Table 7 15 Port P1_3 KI3 AN11 Register PD1 KIEN ADCON0 Function Bit PD1_3 KI3EN CH2 CH1 CH0 ADGSEL0 Setting value 0 X X X X X Input port 1 1 X X X X X Output port 0 1 X X X X KI3 input 0 X 1 1 1 1 A D converter input AN11 Table 7 16 Port P1_4 TXD0 Register PD1 U0MR Function Bit PD1_4 SMD2 SMD1 SMD0 Setting value 0 0 0 0 Input port 1 1 0 0 0 Out...

Page 69: ...ble 7 19 Port P1_7 TRAIO INT1 Register PD1 TRAIOC TRAMR INTEN Function Bit PD1_7 TIOSEL TOPCR TMOD2 TMOD1 TMOD0 INT1EN Setting value 0 0 X X X X X Input port 1 X 1 X X X X X Other than 001b 1 1 X X X X X Output port X 1 X X X X X Other than 001b 0 0 X Other than 001b X TRAIO input 0 0 X Other than 001b 1 TRAIO INT1 input X 0 0 0 0 1 X TRAIO pulse output Table 7 20 Port P2_0 TRDIOA0 TRDCLK Register...

Page 70: ...m output output compare function 0 1 X Table 7 22 Port P2_2 TRDIOC0 Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORC0 Function Bit PD2_2 EC0 CMD1 CMD0 PWM3 PWMC0 IOC2 IOC1 IOC0 Setting value 0 1 X X X X X X X Input port 1 1 1 X X X X X X X Output port 0 X 0 0 1 0 1 X X Timer mode input capture function X 0 1 0 X X X X X Complementary PWM mode waveform output 1 1 X 0 0 1 X X X X X Reset synchronous PWM m...

Page 71: ...2_5 TRDIOB1 Register PD2 TRDOER1 TRDFCR TRDPMR TRDIORA1 Function Bit PD2_5 EB1 CMD1 CMD0 PWM3 PWMB1 IOB2 IOB1 IOB0 Setting value 0 1 X X X X X X X Input port 1 1 1 X X X X X X X Output port 0 X 0 0 1 0 1 X X Timer mode input capture function X 0 1 0 X X X X X Complementary PWM mode waveform output 1 1 X 0 0 1 X X X X X Reset synchronous PWM mode waveform output X 0 0 0 1 1 X X X PWM mode waveform ...

Page 72: ...0 1 0 1 X X Timer mode input capture function X 0 1 0 X X X X X Complementary PWM mode waveform output 1 1 X 0 0 1 X X X X X Reset synchronous PWM mode waveform output X 0 0 0 1 1 X X X PWM mode waveform output X 0 0 0 1 0 0 0 1 Timer mode waveform output output compare function 0 1 X Table 7 28 Port P3_0 TRAO Register PD3 TRAIOC Function Bit PD3_0 TOENA Setting value 0 0 Input port 1 1 0 Output p...

Page 73: ... 0 X SCS output 2 1 1 X X X 1 1 SDA input output Table 7 32 Port P3_5 SCL SSCK Register PD3 Clock Synchronous Serial I O with Chip Select Refer to Table 16 4 Association between Communication Modes and I O Pins PMR ICCR1 Function Bit PD3_5 SSCK output control SSCK input control IICSEL ICE Setting value 0 0 0 0 X Input port 1 0 0 0 X 0 1 0 0 0 X Output port 2 1 0 0 X 0 X 0 1 0 0 SSCK input X 1 0 0 ...

Page 74: ..._5 INT0 Register PD4 INTEN Function Bit PD4_5 INT0EN Setting value 0 X Input port 1 1 X Output port 0 1 INT0 input Table 7 38 Port P4_6 XIN Register CM1 CM0 Circuit specifications Function Bit CM13 CM10 CM05 Oscillation buffer Feedback resistor Setting value 0 X X OFF OFF Input port 1 0 0 ON ON XIN XOUT oscillation 1 0 1 OFF ON External XIN input 1 1 0 OFF OFF XIN XOUT oscillation stop 1 1 1 OFF O...

Page 75: ...Pulled up by setting the PU15 bit in the PUR0 register to 1 Table 7 40 Port P6_0 TREO Register PD6 TRECR1 Function Bit PD6_0 TOENA Setting value 0 0 Input port 1 1 0 Output port X 1 TREO output Table 7 41 Port P6_1 Register PD6 Function Bit PD6_1 Setting value 0 Input port 1 1 Output port Table 7 42 Port P6_2 Register PD6 Function Bit PD6_2 Setting value 0 Input port 1 1 Output port Table 7 43 Por...

Page 76: ...ster PD6 PMR U1MR U1C0 INTEN Function Bit PD6_6 U1PINSEL SMD2 SMD1 SMD0 NCH INT2EN Setting value 0 X 0 0 0 X X Input port 1 0 X X X 1 X 0 0 0 X X Output port 0 X X X 0 X X X X X 1 INT2 input X 1 0 0 1 0 X TXD1 output CMOS output 1 0 0 1 0 1 1 1 0 X 1 0 0 1 1 X TXD1 output N channel open drain output 1 0 0 1 0 1 1 1 0 Table 7 47 Port P6_7 INT3 RXD1 Register PD6 PMR INTEN Function Bit PD6_7 U1PINSEL...

Page 77: ...g of the direction registers 2 Connect these unassigned pins to the MCU using the shortest wire length 2 cm or less as possible 3 When power on reset function is in use Figure 7 13 Unassigned Pin Handling Table 7 48 Unassigned Pin Handling Pin Name Connection Ports P0 to P2 P3_0 P3_1 P3_3 to P3_7 P4_3 to P4_5 P6 After setting to input mode connect every pin to VSS via a resistor pull down or conne...

Page 78: ...les w riting before rew riting to the PM0 register The MCU is reset w hen this bit is set to 1 When read its content is 0 RW b7 b4 PM03 Softw are reset bit Nothing is assigned If necessary set to 0 When read the content is 0 b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 b2 b0 Processor Mode Register 1 1 Symbol Address After Reset PM1 0005h 00h Bit Symbol Bit Name Function RW NOTES 1 2 0 b1 b0 RW Reserved bits Set...

Page 79: ...nits The bus operation is the same as Area SFR data flash even address byte access in Table 9 3 Access Unit and Bus Operations and 16 bit data is accessed at a time Table 9 1 Bus Cycles by Access Space of the R8C 20 Group Access Area Bus Cycle SFR 2 cycles of CPU clock ROM RAM 1 cycle of CPU clock Table 9 2 Bus Cycles by Access Space of the R8C 21 Group Access Area Bus Cycle SFR Data flash 2 cycle...

Page 80: ... clock frequency is automatically set to up to 20 MHz by a driver when using the high speed on chip oscillator as the CPU clock source Table 10 1 Specifications of Clock Generation Circuit Item XIN Clock Oscillation Circuit On Chip Oscillator High Speed On Chip Oscillator Low Speed On Chip Oscillator Use of Clock CPU clock source Peripheral function clock source CPU clock source Peripheral functio...

Page 81: ...clock Forcible discharge when OCD0 0 Charge discharge circuit Oscillation stop detection interrupt generation circuit detection Watchdog timer interrupt OCD1 OCD2 bit switch signal CM14 bit switch signal Oscillation stop detection watchdog timer voltage monitor 2 interrupt CM02 CM05 CM06 Bits in CM0 register CM10 CM13 CM14 CM16 CM17 Bits in CM1 register OCD0 OCD1 OCD2 Bits in OCD register FRA00 FR...

Page 82: ...t 0 5 0 Enables CM16 CM17 1 Divide by 8 mode RW b7 Reserved bit Set to 0 RW When entering stop mode the CM06 bit is set to 1 divide by 8 mode Set the PRC0 bit in the PRCR register to 1 enables w riting before rew riting to the CM0 register The CM05 bit is to stop the XIN clock w hen the high speed on chip oscillator mode low speed on chip oscillator mode is selected Do not use this bit for w hethe...

Page 83: ...it 2 0 Low 1 High RW CM17 RW b7 b6 0 0 No division mode 0 1 Divide by 2 mode 1 0 Divide by 4 mode 1 1 Divide by 16 mode System clock division select bits 1 3 CM16 RW When the CM10 bit is set to 1 stop mode and the CM13 bit is set to 1 XIN XOUT pin the XOUT P4_7 pin becomes H When the CM13 bit is set to 0 input ports P4_6 P4_7 the P4_7 XOUT enters input mode In count source protect mode Refer to 13...

Page 84: ...w speed on chip oscillator on if the OCD2 bit is set to 1 selects on chip oscillator clock Refer to Figure 10 13 Procedure for Switching Clock Source from Low Speed On Chip Oscillator to XIN Clock for the sw itching procedure w hen the XIN clock re oscillates after detecting an oscillation stop Set the PRC0 bit in the PRCR register to 1 enables w riting before rew riting to the OCD register The OC...

Page 85: ...b to 111b When setting the FRA01 bit to 0 selects low speed on chip oscillator do not set the FRA00 bit to 0 40MHz on chip oscillator off at the same time Set the FRA00 bit to 0 after setting the FRA01 bit to 0 b7 b2 Reserved bits Set to 0 RW Set the PRC0 bit in the PRCR register to 1 enables w riting before rew riting to the FRA0 register High Speed On Chip Oscillator Control Register 1 1 Symbol ...

Page 86: ...A20 bit follow the procedure show n in Figure 10 10 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit VCA20 Internal pow er low consumption enable bit 5 0 Disables low consumption 1 Enables low consumption RW When using the voltage monitor 2 interrupt reset or the VCA13 bit in the VCA1 register set the VCA27 bit to 1 After the VCA27 bit is from 0 to 1 the voltage detection ...

Page 87: ...e XIN clock is oscillating stably The power consumption can be reduced by setting the CM05 bit in the CM0 register to 1 stop XIN clock if the OCD2 bit is set to 1 select on chip oscillator clock When the clocks externally generated to the XIN pin are input a XIN clock does not stop if setting the CM05 bit to 1 If necessary use an external circuit to stop the clock In stop mode all clocks including...

Page 88: ...ng ambient temperature The application products must be designed with sufficient margin to accommodate the frequency range 10 2 2 High Speed On Chip Oscillator Clock The clock generated by the high speed on chip oscillator is used as the clock source for the CPU clock peripheral function clock fOCO fOCO F and fOCO40M To use the high speed on chip oscillator clock as the clock source of the CPU clo...

Page 89: ...struction is executed after setting the CM02 bit in the CM0 register to 1 peripheral function clock stops in wait mode the clock fi stop 10 3 4 fOCO fOCO is operating clocks for the peripheral functions The fOCO run at the same frequency as the on chip oscillator clock and can be used as the source for the timer RA When the WAIT instruction is executed the clocks fOCO does not stop 10 3 5 fOCO40M ...

Page 90: ...ed on chip oscillator on or the FRA00 bit in the FRA0 register is set to 1 high speed on chip oscillator on the fOCO can be used for timers RA When the FRA00 bit is set to 1 fOCO40M can be used for timer RD When the CM14 bit is set to 0 low speed on chip oscillator on fOCO S can be used for the watchdog timer and voltage detection circuit 10 4 1 2 High Speed On Chip Oscillator Mode The high speed ...

Page 91: ...ower low consumption enabled enables lower consumption current in wait mode When enabling reduced internal power consumption using the VCA20 bit follow Figure 10 10 Procedure for Enabling Reduced Internal Power Consumption Using VCA20 bit 10 4 2 Wait Mode Since the CPU clock stops in wait mode the CPU operated in the CPU clock and the watchdog timer when count source protection mode is disabled st...

Page 92: ...VL0 bits of the peripheral function interrupts not to use for exiting wait mode to 000b disables interrupt 2 Set the I flag to 1 3 Operate the peripheral function to use for exiting wait mode When exiting by a peripheral function interrupt the time number of cycles between interrupt request generation and interrupt routine execution is determined by the settings of the FMSTP bit in the FMR0 regist...

Page 93: ...ed T2 Time for Interrupt Sequence T3 Remarks 0 flash memory operates Period of system clock 12 cycles 30 µs max Period of CPU clock 6 cycles Period of CPU clock 20 cycles Following total time is the time from wait mode until an interrupt routine is executed 1 flash memory stops Period of system clock 12 cycles Same as above Same as above Wait mode Flash memory activation sequence CPU clock restart...

Page 94: ...nabled by VCA20 bit Enter low speed on chip oscillator mode Stop XIN clock and high speed on chip oscillator clock VCA20 1 internal power low consumption enabled 2 Enter wait mode 4 VCA20 0 internal power low consumption disabled 2 Start XIN clock or high speed on chip oscillator clock Wait until XIN clock oscillation stabilizes Enter high speed clock mode or high speed on chip oscillator mode In ...

Page 95: ...et or peripheral function interrupt When using a reset to exit stop mode set the ILVL2 to ILVL0 bits for the peripheral function interrupts to 000b disables interrupts before setting the CM10 bit to 1 Figure 10 11 shows the Time from Stop Mode to Interrupt Routine Execution When using a peripheral function interrupt to exit stop mode set up the following before setting the CM10 bit to 1 1 Set the ...

Page 96: ...12 cycles 30 µs max Period of CPU clock 6 cycles Period of CPU clock 20 cycles Following total time of T0 to T4 is the time from wait mode until an interrupt routine is executed 1 flash memory stops Period of system clock 12 cycles Same as above Same as above Stop mode Flash memory activation sequence CPU clock restart sequence Interrupt sequence T2 T3 T4 Interrupt request generated Oscillation pe...

Page 97: ...w speed on chip oscillator mode CM14 0 OCD2 1 FRA01 0 High speed on chip oscillator mode OCD2 1 FRA00 1 FRA01 1 High speed clock mode CM05 0 CM13 1 OCD2 0 Standard operating mode CM14 0 OCD2 1 FRA01 0 CM05 0 CM13 1 OCD2 0 CM05 0 CM13 1 OCD2 0 OCD2 1 FRA00 1 FRA01 1 FRA00 1 FRA01 1 CM14 0 FRA01 0 All oscillators stop Interrupt WAIT instruction Interrupt CM05 CM0 register CM13 CM14 CM1 register OCD2...

Page 98: ...is re oscillated after oscillation stop switch the XIN clock to the clock source of the CPU clock and peripheral functions by a program Figure 10 13 shows the Procedure for Switching Clock Source from Low Speed On Chip Oscillator to XIN Clock To enter wait mode while using the oscillation stop detection function set the CM02 bit to 0 peripheral function clock does not stop in wait mode Since the o...

Page 99: ...r 1 and Voltage Monitor 2 Interrupts Generated Interrupt Source Bit Showing Interrupt Cause Oscillation Stop Detection a or b a OCD3 bit in OCD register 1 b OCD1 to OCD0 bits in OCD register 11b and the OCD2 bit 1 Watchdog Timer VW2C3 bit in VW2C register 1 Voltage Monitor 2 VW2C2 bit in VW2C register 1 Set OCD1 to OCD0 bits to 00b Determine several times that the OCD bit is 0 XIN clock oscillates...

Page 100: ...op detection interrupts OCD1 to OCD3 Bits in OCD register VW2C3 Bit in VW2C register Interrupt sources judgment OCD3 1 XIN clock stops OCD1 1 Oscillation stop detection interrupt enable and OCD2 1 Selects on chip oscillator clock VW2C3 1 Watchdog time underflows Jump to oscillation stop detection interrupt process routine Jump to voltage monitor 2 Interrupt process routine Jump to watchdog timer i...

Page 101: ...ect disabled FSET I Enable interrupt BSET 0 CM1 Stop mode JMP B LABEL_001 LABEL_001 NOP NOP NOP NOP 10 6 2 Wait Mode When entering wait mode set the FMR01 bit to 0 CPU rewrite mode disabled and execute the WAIT instruction An instruction queue pre reads 4 bytes from the WAIT instruction and the program stops Insert at least 4 NOP instructions after the WAIT instruction Example to execute the WAIT ...

Page 102: ... Symbol Address After Reset PRCR 000Ah 00h Bit Symbol Bit Name Function RW NOTE 1 This bit is set to 0 after w riting 1 to the PRC2 bit and executing w riting to any address Since the other bits are not set to 0 set to 0 by a program b7 b6 Reserved bits When read the content is 0 RO RW b5 b4 Reserved bits Set to 0 RW PRC3 Protect bit 3 Writing to the VCA2 VW1C and VW2C registers is enabled 0 Disab...

Page 103: ...le flag I flag does not enable or disable an interrupt The interrupt priority order based on interrupt priority level cannot be changed Interrupt non maskable interrupt Hardware Software non maskable interrupt maskable interrupt Special Peripheral function 1 Undefined instruction UND instruction Overflow INTO instruction BRK instruction INT instruction Watchdog timer Oscillation stop detection Vol...

Page 104: ...rrupt is generated when the BRK instruction is executed 12 1 2 4 INT Instruction Interrupt An INT instruction interrupt is generated when the INT instruction is executed The INT instruction can select software interrupt numbers 0 to 63 Software interrupt numbers 3 to 31 are assigned to the peripheral function interrupt Therefore the MCU executes the same interrupt routine when the INT instruction ...

Page 105: ...on circuit refer to 6 Voltage Detection Circuit 12 1 3 4 Single Step Interrupt and Address Break Interrupt Do not use the single step interrupt For development tools only 12 1 3 5 Address Match Interrupt The address match interrupt is generated immediately before executing an instruction that is stored into an address indicated by the RMAD0 to RMAD1 registers when the AIER0 or AIER1 bit in the AIE...

Page 106: ...t use the single step interrupt For development tools only Table 12 1 Fixed Vector Tables Interrupt Source Vector Addresses Address L to H Remarks Reference Undefined Instruction 0FFDCh to 0FFDFh Interrupt on UND instruction R8C Tiny Series software manual Overflow 0FFE0h to 0FFE3h Interrupt on INTO instruction BRK Instruction 0FFE4h to 0FFE7h If the content of address 0FFE7h is FFh program execut...

Page 107: ...mer RE Reserved 11 to 12 Key Input 52 to 55 0034h to 0037h 13 KUPIC 12 3 Key Input Interrupt A D 56 to 59 0038h to 003Bh 14 ADIC 18 A D Converter Clock Synchronous Serial I O with Chip Select I2C bus Interface 2 60 to 63 003Ch to 003Fh 15 SSUIC IICIC 16 2 Clock Synchronous Serial I O with Chip Select SSU 16 3 I2C Bus Interface Reserved 16 UART0 Transmit 68 to 71 0044h to 0047h 17 S0TIC 15 Serial I...

Page 108: ...nterrupt Control Register 2 Symbol Address After Reset TREIC 004Ah XXXXX000b KUPIC 004Dh XXXXX000b ADIC 004Eh XXXXX000b S0TIC 0051h XXXXX000b S0RIC 0052h XXXXX000b S1TIC 0053h XXXXX000b S1RIC 0054h XXXXX000b TRAIC 0056h XXXXX000b TRBIC 0058h XXXXX000b Bit Symbol Bit Name Function RW NOTES 1 2 Rew rite the interrupt control register rew rite it w hen the interrupt request w hich is applicable for i...

Page 109: ...the content is undefined IR Interrupt request bit 0 Requests no interrupt 1 Requests interrupt RO ILVL0 RW Interrupt priority level select bits b2 b1 b0 0 0 0 Level 0 interrupt disable 0 0 1 Level 1 0 1 0 Level 2 0 1 1 Level 3 1 0 0 Level 4 1 0 1 Level 5 1 1 0 Level 6 1 1 1 Level 7 ILVL1 RW ILVL2 RW The IICSEL bit in the PMR register sw itches functions To rew rite the interrupt control register r...

Page 110: ...it in the INTEN register is set to 1 both edges set the POL bit to 0 selects falling edge The IR bit may be set to 1 requests interrupt w hen the POL bit is rew ritten Refer to 12 6 4 Changing Interrupt Sources b7 b6 b5 b4 b3 b2 b1 b0 0 ILVL0 RW Interrupt priority level select bits b2 b1 b0 0 0 0 Level 0 interrupt disable 0 0 1 Level 1 0 1 0 Level 2 0 1 1 Level 3 1 0 0 Level 4 1 0 1 Level 5 1 1 0 ...

Page 111: ...with Multiple Interrupt Request Sources 12 1 6 3 Bits ILVL2 to ILVL0 and IPL Interrupt priority levels can be set using the ILVL2 to ILVL0 bits Table 12 3 lists the Settings of Interrupt Priority Levels and Table 12 4 lists the Interrupt Priority Levels Enabled by IPL The following are conditions under which an interrupt is acknowledged I flag 1 IR bit 1 Interrupt priority level IPL The I flag IR ...

Page 112: ...ag is set to 0 disables interrupts The D flag is set to 0 disables single step interrupt The U flag is set to 0 ISP selected However the U flag does not change state if an INT instruction for software interrupt number 32 to 63 is executed 4 The CPU s internal temporary register 1 is saved to the stack 5 The PC is saved to the stack 6 The interrupt priority level of the acknowledged interrupt is se...

Page 113: ...ledged interrupt is set in the IPL When a software interrupt and special interrupt request are acknowledged the level listed in Table 12 5 is set to the IPL Table 12 5 lists the IPL Value When Software or Special Interrupt Is Acknowledged Table 12 5 IPL Value When Software or Special Interrupt Is Acknowledged Interrupt Sources Value Set to IPL Watchdog Timer Oscillation Stop Detection Voltage Moni...

Page 114: ...value before interrupt is generated Content of previous stack LSB MSB Address Content of previous stack m 4 m 3 m 2 m 1 m m 1 Stack state before interrupt request is acknowledged SP New SP value Content of previous stack LSB MSB Content of previous stack m m 1 Stack state after interrupt request is acknowledged PCL PCM FLGL FLGH PCH m 4 m 3 m 2 m 1 Stack Address PCH High order 4 bits of PC PCM Mid...

Page 115: ...t with the higher priority is acknowledged Set the ILVL2 to ILVL0 bits to select the desired priority level for maskable interrupts peripheral functions However if two or more maskable interrupts have the same priority level their interrupt priority is resolved by hardware with the higher priority interrupt acknowledged in hardware The priority levels of special interrupts such as reset reset has ...

Page 116: ...ircuit INT3 Timer RB Timer RA INT0 INT1 UART1 receive UART0 receive A D conversion SSU I2 C bus 1 Key Input IPL Priority level of each interrupt Level 0 default value Lowest Highest Priority of peripheral function interrupts if priority levels are same Interrupt request level judgment output signal Interrupt request acknowledged I flag Address match Watchdog timer Oscillation stop detection Voltag...

Page 117: ...ut Enable Register Symbol Address After Reset INTEN 00F9h 00h Bit Symbol Bit Name Function RW INT0 _____ input enable bit INT0 _____ input polarity select bit 1 2 INT1 _____ input enable bit INT1 _____ input polarity select bit 1 2 INT2 _____ input enable bit INT2 _____ input polarity select bit 1 2 INT3 _____ input enable bit INT3 _____ input polarity select bit 1 2 NOTES 1 2 0 Disable 1 Enable R...

Page 118: ...ut filter select bits INT0F0 RW INT0F1 RW b7 b6 b5 b4 b3 b2 b1 b0 RW b1 b0 0 0 No filter 0 1 Filter w ith f1 sampling 1 0 Filter w ith f8 sampling 1 1 Filter w ith f32 sampling RW b7 b6 0 0 No filter 0 1 Filter w ith f1 sampling 1 0 Filter w ith f8 sampling 1 1 Filter w ith f32 sampling INT3F1 INT3F0 INT1F0 b3 b2 0 0 No filter 0 1 Filter w ith f1 sampling 1 0 Filter w ith f8 sampling 1 1 Filter w ...

Page 119: ...igure 12 15 Operating Example of INTi Input Filter i 0 to 3 INTiF0 INTiF1 Bits in INTF register INTiEN INTiPL Bits in INTEN register 01b INTi Port direction register 1 Sampling clock Digital filter input level matches 3x INTi interrupt 10b 11b f32 f8 f1 INTiF1 to INTiF0 INTiEN Other than INTiF1 to INTiF0 00b 00b INTiPL 0 INTiPL 1 NOTE 1 INT0 Port P4_5 direction register INT1 Port P1_5 direction re...

Page 120: ...13 pins are not detected as interrupts Also when inputting H to the KIi pin which sets the KIiPL bit to 1 rising edge the input of the other K10 to K13 pins are not detected as interrupts Figure 12 16 shows a Block Diagram of Key Input Interrupt Figure 12 16 Block Diagram of Key Input Interrupt KI3 Pull up transistor KI2 Pull up transistor KI3PL 0 KI3PL 1 PD1_3 bit KI3EN bit PU02 bit in PUR0 regis...

Page 121: ...b2 RW KI2EN RW KI1PL KI1 input polarity select bit 0 Falling edge 1 Rising edge KI2 input enable bit 0 Disable 1 Enable b7 b6 b5 b4 b1 b0 The IR bit in the KUPIC register may be set to 1 requests interrupt w hen the KIEN register is rew ritten Refer to 12 6 4 Changing Interrupt Sources KI1EN RW KI3EN KI3 input enable bit KI3PL RW KI2PL KI2 input polarity select bit 0 Falling edge 1 Rising edge KI3...

Page 122: ...stack as it was before an interrupt request was acknowledged And then use a jump instruction Table 12 6 lists the Value of PC Saved to Stack when Address Match Interrupt is Acknowledged Figure 12 18 shows the Registers AIER and RMAD0 to RMAD1 NOTES 1 Refer to the 12 1 6 7 Saving a Register for the PC value saved 2 Operation code Refer to the R8C Tiny Series Software Manual REJ09B0001 Chapter 4 Ins...

Page 123: ...ad the content is 0 b7 b6 b5 b4 0 Disable 1 Enable RW b3 b2 b1 b0 Address match interrupt 0 enable bit 0 Disable 1 Enable RW AIER1 Address match interrupt 1 enable bit AIER0 Address Match Interrupt Register i i 0 or 1 b0 Symbol Address After Reset RMAD0 0012h 0010h 000000h RMAD1 0016h 0014h 000000h Setting Range RW b16 b0 b19 b3 b23 b7 RW b7 b4 Nothing is assigned If necessary set to 0 When read t...

Page 124: ...f the IR bit in the interrupt control register Table 12 8 lists the Registers Associated with Timer RD Interrupt Clock Synchronous Serial I O with Chip Select Interrupt and I2C bus Interface Interrupt and Figure 12 19 shows the Block Diagram of Timer RD Interrupt Figure 12 19 Block Diagram of Timer RD Interrupt Table 12 8 Registers Associated with Timer RD Interrupt Clock Synchronous Serial I O wi...

Page 125: ...Basically even though the interrupt is not acknowledged after the IR bit is set to 1 the interrupt request will not be maintained Also the IR bit is not set to 0 although 0 is written to the IR bit Since each bit in the status register is not automatically set to 0 even if the interrupt is acknowledged Therefore the IR bit is not also automatically set to 0 when the interrupt is acknowledged Set e...

Page 126: ... among the enabled interrupts is set to 0 This may cause a problem that the interrupt is canceled or an unexpected interrupt is generated 12 6 2 SP Setting Set any value in the SP before an interrupt is acknowledged The SP is set to 0000h after reset Therefore if an interrupt is acknowledged before setting any value in the SP the program may run out of control 12 6 3 External Interrupt and Key Inp...

Page 127: ...ions Figure 12 20 shows an Example of Procedure for Changing Interrupt Sources Figure 12 20 Example of Procedure for Changing Interrupt Sources NOTES 1 Execute the above settings individually Do not execute two or more settings at once by one instruction 2 To prevent interrupt requests from being generated disable the peripheral function before changing the interrupt source In this case use the I ...

Page 128: ... interrupt not requested it may not be set to 0 depending on the instruction to be used Therefore use the MOV instruction to set the IR bit to 0 c When disabling interrupts using the I flag set the I flag according to the following sample programs Refer to b for the change of interrupt control registers in the sample programs Sample programs 1 to 3 are preventing the I flag from being set to 1 int...

Page 129: ...Item Count Source Protection Mode Disabled Count Source Protection Mode Enabled Count Source CPU clock Low speed on chip oscillator clock Count Operation Decrement Count Start Condition Either of following can be selected After reset count starts automatically Count starts by writing to WDTS register Count Stop Condition Stop mode wait mode None Reset Condition of Watchdog Timer Reset Write 00h to...

Page 130: ...g timer automatically after reset 1 Watchdog timer is inactive after reset RW ROMCR ROM code protect disabled bit 0 ROM code protect disabled 1 ROMCP1 enabled RW ROMCP1 ROM code protect bit 0 ROM code protect enabled 1 ROM code protect disabled RW RW b5 b4 Reserved bits Set to 1 RW If the block including the OFS register is erased FFh is set to the OFS register To use the pow er on reset set the L...

Page 131: ...ister is set to 1 count source protection mode enabled 0FFFh is set to the w atchdog timer WO Watchdog Timer Start Register Symbol Address After Reset WDTS 000Eh Indeterminate RW WO Function The w atchdog timer starts counting after a w rite instruction to this register b0 b7 Count Source Protection Mode Register Symbol Address After Reset 1 CSPR 001Ch 00h Bit Symbol Bit Name Function RW NOTES 1 2...

Page 132: ...scaler n x count value of watchdog timer 32768 1 CPU clock n 16 or 128 selected by WDC7 bit in WDC register e g When the CPU clock is 16 MHz and prescaler is divided by 16 the period is approximately 32 8 ms Count Start Condition The WDTON bit 2 in the OFS register 0FFFFh selects the operation of watchdog timer after reset When the WDTON bit is set to 1 watchdog timer is in stop state after reset ...

Page 133: ...ON bit 1 in the OFS register 0FFFFh selects the operation of the watchdog timer after reset When the WDTON bit is set to 1 watchdog timer is in stop state after reset The watchdog timer and prescaler stop after reset and the count starts by writing to the WDTS register When the WDTON bit is set to 0 watchdog timer starts automatically after reset The watchdog timer and prescaler start counting aut...

Page 134: ...8 bit counter The two 8 bit timers with the 8 bit prescaler contain timer RA and timer RB These timers contain a reload register to memorize the default value of the counter The 16 bit timer is timer RD which contains the input capture and output compare The 4 and 8 bit counters are timer RE which contains the output compare All these timers operate independently Table 14 1 lists Functional Compar...

Page 135: ...de provided not provided not provided not provided Programmable waveform generation mode not provided provided not provided not provided Programmable one shot generation mode not provided provided not provided not provided Programmable wait one shot generation mode not provided provided not provided not provided Input capture mode not provided not provided provided not provided Output compare mode...

Page 136: ... the polarity by underflow of the timer Event counter mode The timer counts external pulses Pulse width measurement mode The timer measures the pulse width of an external pulse Pulse period measurement mode The timer measures the pulse period of an external pulse Figure 14 1 Block Diagram of Timer RA TCSTF bit TCKCUT bit 000b 001b 011b f2 f8 f1 010b fOCO TCK2 to TCK0 bit Counter Reload register TR...

Page 137: ...dge reception flag 3 5 TSTART In pulse w idth measurement mode and pulse period measurement mode use the MOV instruction to set the TRACR register If it is necessary to avoid changing the values of bits TEDGF and TUNDF w rite 1 to them Set to 0 in timer mode pulse output mode and event counter mode Bits TEDGF and TUNDF can be set to 0 by w riting 0 to these bits by a program How ever their value r...

Page 138: ...iod measurement mode 1 0 1 1 1 0 Do not set 1 1 1 b7 b6 b5 b4 RW Timer RA count source select bits b6 b5 b4 0 0 0 f1 0 0 1 f8 0 1 0 fOCO 0 1 1 f2 1 0 0 1 0 1 Do not set 1 1 0 1 1 1 Nothing is assigned If necessary set to 0 When read the content is 0 TMOD2 RW TCKCUT TCK1 b3 b2 b3 b1 b0 Timer RA Prescaler Register Symbol Address After Reset TRAPRE 0103h FFh 1 Mode Function Setting Range RW NOTE 1 Wh...

Page 139: ...200 Figure 14 4 TRA Register Timer RA Register Symbol Address After Reset TRA 0104h FFh 1 Mode Function Setting Range RW NOTE 1 00h to FFh b7 When the TSTOPbit in the TRACR register is set to 1 the TRA register is set to FFh b0 All Modes Counts of an underflow of the TRAPRE register RW ...

Page 140: ...on Timing When Timer RA underflows Timer RA interrupt INT1 TRAIO Pin Function Programmable I O port or INT1 interrupt input TRAO Pin Function Programmable I O port Read from Timer The count value can be read by reading the TRA and TRAPRE registers Write to Timer When registers TRAPRE and TRA are written while the count is stopped values are written to both the reload register and counter When regi...

Page 141: ...instruction is executed Figure 14 6 shows an Operating Example of Timer RA when Counter Value is Rewritten during Count Operation Figure 14 6 Operating Example of Timer RA when Counter Value is Rewritten during Count Operation Count source Reloads register of timer RA prescaler IR bit in TRAIC register 0 Counter of timer RA prescaler Reloads register of timer RA Counter of timer RA Set 01h to the ...

Page 142: ...ibly stops to the TSTOP bit in the TRACR register Interrupt Request Generation Timing When timer RA underflows timer RA interrupt INT1 TRAIO Pin Function Pulse output programmable output port or INT1 interrupt 1 TRAO Pin Function Programmable I O port or inverted output of TRAIO 1 Read from Timer The count value can be read by reading the TRA and TRAPRE registers Write to Timer When registers TRAP...

Page 143: ... TRAIO pin P1_7 1 INT1 _____ TRAIO pin P1_5 RW RW 0 TRAIO output 1 Port P1_7 or P1_5 Nothing is assigned If necessary set to 0 When read the content is 0 TRAO output enable bit TRAIO input filter select bits Set to 0 in pulse output mode TEDGSEL RW TRAIO polarity sw itch bit TIPF1 b7 b6 TOPCR RW TOENA RW RW TIPF0 TRAIO output control bit 0 0 b7 b6 b5 b4 b3 b2 0 Port P3_0 1 TRAO output Inverted TRA...

Page 144: ...bly stops to the TSTOP bit in the TRACR register Interrupt Request Generation Timing When timer RA underflows timer RA interrupt INT1 TRAIO Pin Function Count source input INT1 interrupt input TRAO Pin Function Programmable I O port 1 Read from Timer The count value can be read by reading the TRA and TRAPRE registers Write to Timer When registers TRAPRE and TRA are written while the count is stopp...

Page 145: ...the input is determined TRAIO output control bit Set to 0 in event counter mode Nothing is assigned If necessary set to 0 When read the content is 0 TRAO output enable bit TRAIO input filter select bits 1 b5 b4 0 0 No filter 0 1 Filter w ith f1 sampling 1 0 Filter w ith f8 sampling 1 1 Filter w ith f32 sampling TIPF1 b7 b6 RW TEDGSEL RW TRAIO polarity sw itch bit RW TIPF0 RW TOPCR RW b3 b2 b7 b6 b...

Page 146: ...T bit in the TRACR register Write 1 count forcibly stops to the TSTOP bit in the TRACR register Interrupt Request Generation Timing When timer RA underflows timer RA interrupt Rising or falling of the TRAIO input end of measurement period timer RA interrupt INT1 TRAIO Pin Function Measurement pulse input INT1 interrupt input TRAO Pin Function Programmable I O port Read from Timer The count value c...

Page 147: ... the same value from the TRAIO pin is sampled three times continuously the input is determined b3 b2 TIOSEL b1 b0 0 TRAIO input starts at L 1 TRAIO input starts at H 0 b7 b6 b5 b4 TOPCR RW TOENA RW RW TIPF0 TRAIO output control bit 0 TEDGSEL RW TRAIO polarity sw itch bit TIPF1 b7 b6 Nothing is assigned If necessary set to 0 When read the content is 0 TRAO output enable bit TRAIO input filter selec...

Page 148: ...unt start Count stop Underflow Period TSTART bit in TRACR register 1 0 Measurement pulse TRAIO pin input 1 0 TEDGF bit in TRACR register 1 0 TUNDF bit in TRACR register 1 0 The above applies under the following conditions H level width of measured pulse is measured TEDGSEL 1 TRAPRE FFh Set to 1 by program IR bit in TRAIC register 1 0 Set to 0 by program Count stop Count start Set to 0 when interru...

Page 149: ...nues counting Count Start Condition Write 1 count start to the TSTART bit in the TRACR register Count Stop Conditions Write 0 count stop to TSTART bit in the TRACR register Write 1 count forcibly stops to the TSTOP bit in the TRACR register Interrupt Request Generation Timing When timer RA underflows or reloads timer RA interrupt Rising or falling of the TRAIO input end of measurement period timer...

Page 150: ...e times continuously the input is determined b3 b2 TIOSEL b1 b0 0 Measures measurement pulse from one rising edge to next rising edge 1 Measures measurement pulse from one falling edge to next falling edge 0 0 b7 b6 b5 b4 RW TRAIO polarity sw itch bit TOPCR RW TOENA RW RW TIPF0 TRAO output enable bit TRAIO input filter select bits 1 b5 b4 0 0 No filter 0 1 Filter w ith f1 sampling 1 0 Filter w ith...

Page 151: ... instruction to write 0 to the TEDGF bit in the TRACR register At the same time write 1 to the TUNDF bit in the TRACR register 5 When set to 0 by a program use a MOV instruction to write 0 to the TUNDF bit At the same time write 1 to the TEDGF bit 6 The TUNDF and TEDGF bits are both set to 1 if the timer RA underflows and reloads on an active edge simultaneously 0Eh 0Dh 0Fh 0Eh 0Dh 0Ch 0Bh 0Ah 09h...

Page 152: ...count starts The TEDGF bit may be set to 1 by timer RA prescaler underflow which is generated for the first time since the count starts When using the pulse period measurement mode leave two periods or more of timer RA prescaler immediately after count starts and set the TEDGF bit to 0 The TCSTF bit retains 0 count stops for 0 to 1 cycle of the count source after setting the TSTART bit to 1 count ...

Page 153: ...mode The timer outputs pulses of a given width successively Programmable one shot generation mode The timer outputs one shot pulse Programmable wait one shot generation mode The timer outputs delayed one shot pulse Figure 14 13 Block Diagram of Timer RB INT0PL bit 00b 01b 11b f8 f1 10b Timer RA underflow TCK1 to TCK0 bit TSTART bit TRBPRE register Prescaler Timer RB interrupt INT0 interrupt TCSTF ...

Page 154: ...T RW TCSTF Timer RB count status flag 1 TSTOP RW b3 b2 When this bit is set to 1 the count is forcibly stopped When read the content is 0 b1 b0 0 Stops counting 1 Starts counting b7 b6 b5 b4 Timer RB One Shot Control Register 2 Symbol Address After Reset TRBOCR 0109h 00h Bit Symbol Bit Name Function RW NOTES 1 2 Nothing is assigned If necessary set to 0 When read the content is 0 Timer RB one shot...

Page 155: ...ogrammable w aveform generation mode 1 0 Programmable one shot generation mode 1 1 Programmable w ait one shot generation mode b7 b6 b5 b4 RW Nothing is assigned If necessary set to 0 When read the content is 0 Timer RB w rite control bit 2 0 Write to reload register and counter 1 Write to reload register only The TWRC bit can be set to either 0 or 1 in timer mode In programmable w aveform generat...

Page 156: ...unted Programmable w ait one shot generation mode Counts a timer RB prescaler underflow one shot w idth is counted 00h to FFh WO 2 Each value in the TRBPR register and TRBSC register is reloaded to the counter alternately and counted When the TSTOP bit in the TRBCR register is set to 1 the TRBSC register is set to FFh WO 2 Counts a timer RB prescaler underflow 1 00h to FFh Programmable one shot ge...

Page 157: ...he TSTOP bit in the TRBCR register Interrupt Request Generation Timing When timer RB underflows timer RB interrupt TRBO Pin Function Programmable I O port INT0 Pin Function Programmable I O port or INT0 interrupt input Read from Timer The count value can be read out by reading the TRBPR and TRBPRE registers Write to Timer When registers TRBPRE and TRBPR are written while the count is stopped value...

Page 158: ...ster However values are transferred from the reload register to the counter of the prescaler in synchronization with the count source In addition values are transferred from the reload register to the counter of the timer in synchronization with prescaler underflows Therefore even if the TWRC bit is set for writing to both the reload register and counter the counter value is not updated immediatel...

Page 159: ...eload register and counter Count source Reloads register of timer RB prescaler IR bit in TRBIC register Counter of timer RB prescaler Reloads register of timer RB Counter of timer RB Set 01h to the TRBPRE register and 25h to the TRBPR register by a program After writing the reload register is written with the first count source Reload on underflow After writing the reload register is written on th...

Page 160: ...flows it reloads the contents of the primary reload and secondary reload registers alternately before the count continues Width and Period of Output Waveform Primary period n 1 m 1 fi Secondary period n 1 p 1 fi Period n 1 m 1 p 1 fi fi Count source frequency n Setting value in TRBPRE register m Setting value in TRBPR register p Setting value in TRBSC register Count Start Condition Write 1 count s...

Page 161: ...PL Timer RB output level select bit 0 Outputs H for primary period Outputs L for secondary period Outputs L w hen the timer is stopped 1 Outputs L for primary period Outputs H for secondary period Outputs H w hen the timer is stopped Timer RB output sw itch bit 0 Outputs timer RB w aveform 1 Outputs value in P3_1 port latch RW RW One shot trigger control bit Nothing is assigned If necessary set to...

Page 162: ... program Set to 0 when interrupt request is acknowledged or set by program The above applies to the following conditions TSTART bit in TRBCR register 1 0 01h 00h 02h Timer RB secondary reloads Timer RB primary reloads Set to 0 by program TRBPRE 01h TRBPR 01h TRBSC 02h TRBIOC register TOCNT 0 timer RB waveform is output from the TRBO pin 02h 01h 00h 01h 00h Primary period Primary period Secondary p...

Page 163: ... register 2 Count Start Conditions The TSTART bit in the TRBCR register is set to 1 count starts and the next trigger is generated Set the TOSST bit in the TRBOCR register to 1 one shot starts Input trigger to the INT0 pin Count Stop Conditions When reloading completes after Timer RB underflows during primary period When the TOSSP bit in the TRBOCR register is set to 1 one shot stops When the TSTA...

Page 164: ...led NOTE 1 RW RW One shot trigger control bit 1 0 Falling edge trigger 1 Rising edge trigger RW TOCNT RW TOPL Timer RB output level select bit 0 Outputs one shot pulse H Outputs L w hen the timer is stopped 1 Outputs one shot pulse L Outputs H w hen the timer is stopped Timer RB output sw itch bit Set to 0 in programmable one shot generation mode b7 b6 b5 b4 b3 b2 INOSEG b1 b0 0 INOSTG Nothing is ...

Page 165: ...program Set to 1 by program Set to 0 when interrupt request is acknowledged or set by program The above applies to the following conditions TSTART bit in TRBCR register 1 0 1 0 01h 00h 01h 00h 01h Count starts Timer RB primary reloads Count starts Timer RB primary reloads Set to 0 by program Waveform output starts Waveform output ends Waveform output starts Waveform output ends Set to 0 when count...

Page 166: ...TF bit is set to 1 no retriggering occurs To use trigger input from the INT0 pin input the trigger after making the following settings Set the PD4_5 bit in the PD4 register to 0 input port Select the INT0 digital filter with bits INT0F1 and INT0F0 in the INTF register Select both edges or one edge with the INT0PL bit in INTEN register If one edge is selected further select falling or rising edge w...

Page 167: ... see Table 14 10 Programmable Wait One Shot Generation Mode Specifications When a trigger is generated from this point the timer starts outputting pulses only once for a given length of time equal to the setting value in the TRBSC register after waiting for a given length of time equal to the setting value in the TRBPR register Figure 14 23 shows the TRBIOC Register in Programmable Wait One Shot G...

Page 168: ... register to 1 one shot starts Input trigger to the INT0 pin Count Stop Conditions When reloading completes after timer RB underflows during secondary period When the TOSSP bit in the TRBOCR register is set to 0 one shot stops When the TSTART bit in the TRBCR register is set to 0 starts counting When the TSTOP bit in the TRBCR register is set to 1 forcibly stops counting Interrupt Request Generati...

Page 169: ...ng is assigned If necessary set to 0 When read the content is 0 One shot trigger polarity select bit 1 b7 b4 Refer to 14 2 3 1 One shot Trigger Selection b3 b2 INOSEG b1 b0 0 INOSTG b7 b6 b5 b4 RW TOCNT RW TOPL Timer RB output level select bit 0 Outputs one shot pulse H Outputs L w hen the timer is stopped or during w ait 1 Outputs one shot pulse L Outputs H w hen the timer is stopped or during w ...

Page 170: ...t to 1 by setting 1 to TOSST bit in TRBOCR register or INT0 pin input trigger Set to 0 when interrupt request is acknowledged or set by program The above applies to the following conditions TSTART bit in TRBCR register 1 0 1 0 01h 00h 00h 01h Count starts Timer RB secondary reloads Timer RB primary reloads Set to 0 by program Wait starts Waveform output starts Waveform output ends Set to 0 when co...

Page 171: ... TSTART bit to 0 count stops while the count is performing Timer RB counting is stopped when the TCSTF bit is set to 0 During this time do not access registers associated with timer RB 1 other than the TCSTF bit NOTE 1 Registers associated with timer RB TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR If the TSTOP bit in the TRBCR register is set to 1 during timer operation timer RB stops immediately ...

Page 172: ...ter does not occur during period A shown in Figures 14 25 and 14 26 The following shows the detailed workaround examples Workaround example a As shown in Figure 14 25 write to registers TRBSC and TRBPR in the timer RB interrupt routine These write operations must be completed by the beginning of period A Figure 14 25 Workaround Example a When Timer RB Interrupt is Used TRBO pin output Count source...

Page 173: ...on mode The following two workarounds should be performed in programmable one shot generation mode 1 To write to registers TRBPRE and TRBPR during count operation TCSTF bit is set to 1 note the following points When the TRBPRE register is written continuously during count operation TCSTF bit is set to 1 allow three or more cycles of the count source for each write interval When the TRBPR register ...

Page 174: ...llow three or more cycles of the prescaler underflow for each write interval 2 Do not set both the TRBPRE and TRBPR registers to 00h 3 Set registers TRBSC and TRBPR using the following procedure a To use INT0 pin one shot trigger enabled as the count start condition Set the TRBSC register and then the TRBPR register At this time after writing to the TRBPR register allow an interval of 0 5 or more ...

Page 175: ...e modulation and dead time Complementary PWM mode Output three phase waveforms 6 with triangular wave modulation and dead time PWM3 mode Output PWM waveform 2 with same period In the input capture function output compare function and PWM mode Channels 0 and 1 have the equivalent functions and functions or modes can be selected every pin Also a combination of these functions and modes can be used i...

Page 176: ...trigger input input capture function 1 1 1 XXb X 000b External clock input TRDCLK 1 Other than above I O port Table 14 13 Pin Functions TRDIOB0 P2_1 Register TRDOER1 TRDFCR TRDPMR TRDIORA0 Function Bit EB0 PWM3 CMD1 CMD0 PWMB0 IOB2_IOB0 Setting value 0 X 1Xb X XXXb Complementary PWM mode waveform output 0 X 01b X XXXb Reset synchronous PWM mode waveform output 0 0 00b X XXXb PWM3 mode waveform out...

Page 177: ...rm output 0 1 00b 0 001b 01Xb Timer mode waveform output output compare function X 1 00b 0 1XXb Timer mode trigger input input capture function 1 Other than above I O port Table 14 16 Pin Functions TRDIOA1 P2_4 Register TRDOER1 TRDFCR TRDIORA1 Function Bit EA1 PWM3 CMD1 CMD0 IOA2_IOA0 Setting value 0 X 1Xb XXXb Complementary PWM mode waveform output 0 X 01b XXXb Reset synchronous PWM mode waveform...

Page 178: ...tput 0 1 00b 1 XXXb PWM mode waveform output 0 1 00b 0 001b 01Xb Timer mode waveform output output compare function X 1 00b 0 1XXb Timer mode trigger input input capture function 1 Other than above I O port Table 14 19 Pin Functions TRDIOD1 P2_7 Register TRDOER1 TRDFCR TRDPMR TRDIORC1 Function Bit ED1 PWM3 CMD1 CMD0 PWMD1 IOD2_IOD0 Setting value 0 X 1Xb X XXXb Complementary PWM mode waveform outpu...

Page 179: ...register TRDIORCi register TRDSRi register TRDIERi register TRDPOCRi register TRDSTR register TRDMR register TRDPMR register TRDFCR register TRDOER1 register TRDOER2 register TRDOCR register Timer RD control circuit INT0 TRDIOA0 TRDCLK TRDIOB0 TRDIOC0 TRDIOD0 TRDIOB1 TRDIOC1 TRDIOD1 TRDIOA1 Count source select circuit f1 f2 f4 f8 f32 fOCO40M Channel 0 interrupt request Channel 1 interrupt request ...

Page 180: ...14 21 Count Source Selection Count Source Selection f1 f2 f4 f8 f32 The count source is selected by bits TCK2 to TCK0 in the TRDCRi register fOCO40M 1 The FRA00 bit in the FRA0 register is set to 1 high speed on chip oscillator frequency Bits TCK2 to TCK0 in the TRDCRi register is set to 110b fOCO40M External Signal Input to TRDCLK Pin The STCLK bit in the TRDFCR register is set to 1 external cloc...

Page 181: ...egister Output Compare Function Compare match with TRDi register and TRDGRAi TRDGRBi register Transfer content in buffer register to TRDGRAi TRDGRBi register PWM Mode Reset Synchronous PWM Mode Compare match withTRD0 register and TRDGRA0 register Transfer content in buffer register to TRDGRAi TRDGRBi register Complementary PWM Mode Compare match with TRD0 register and TRDGRA0 register TRD1 registe...

Page 182: ...e IOB2 bit in the TRDIORAi register Bits IMFC and IMFD in the TRDSRi register are set to 1 at the input edge of the TRDIOCi pin when also using registers TRDGRCi and TRDGRDi as the buffer register in the input capture function When using the TRDGRCi and TRDGRDi registers for the buffer register in output compare function reset synchronous PWM mode complementary PWM mode and PWM3 mode the IMFC and ...

Page 183: ...register are set to 011b synchronous clear and the TRD1 register is set to 0000h at the same time as the TRD0 register is set to 0000h Figure 14 31 Synchronous Operation Value in TRD0 register TRDIOA0 input n n is set n writing Value in TRD1 register n Set to 0000h with TRD0 register Set to 0000h by input capture The above applies to the following conditions The SYNC bit in the TRDMR register is s...

Page 184: ... programmable I O port after L is applied to the INT0 pin The TRDIOji output pin is set to the programmable I O port after L is applied to the INT0 pin and waiting for 1 to 2 cycles of the Timer RD operation clock refer to Table 14 11 Timer RD Operation Clocks Set as below when using this function Set the pin status high impedance L or H output with the pulse output forced cutoff by the P2 and PD2...

Page 185: ... data Port P2_3 output data Port P2_3 input data Port P2_4 output data Port P2_4 input data Port P2_5 output data Port P2_5 input data Port P2_6 output data Port P2_6 input data Port P2_7 output data Port P2_7 input data PTO Bit in TRDOER2 register EA0 EB0 EC0 ED0 EA1 EB1 EC1 ED1 Bits in TRDOER1 register EA0 bit writing value EB0 bit writing value EC0 bit writing value ED0 bit writing value EA1 bi...

Page 186: ...sts the Input Capture Function Specifications Figures 14 34 to 14 44 show the Registers Associated with Input Capture Function and Figure 14 45 shows the Operating Example of Input Capture Function Figure 14 33 Block Diagram of Input Capture Function i 0 or 1 NOTES 1 When the BFCi bit in the TRDMR register is set to 1 the TRDGRCi register is used as the buffer register of the TRDGRAi register 2 Wh...

Page 187: ...e I O port or input capture input Select every pin INT0 Pin Function Programmable I O port or INT0 interrupt input Read from Timer The count value can be read by reading the TRDi register Write to Timer When the SYNC bit in the TRDMR register is set to 0 channels 0 and 1 operate independently Data can be written to the TRDi register When the SYNC bit in the TRDMR register is set to 1 channels 0 an...

Page 188: ... 1 TSTART0 RW TSTART1 RW TRD1 count start flag 0 Count stops 1 Count starts TRD0 count start flag 0 Count stops 1 Count starts Timer RD Mode Register Symbol Address After Reset TRDMR 0138h 00001110b Bit Symbol Bit Name Function RW b3 b2 BFD0 b1 b0 SYNC b7 b6 b5 b4 RW b3 b1 Timer RD synchronous bit 0 TRD0 and TRD1 registers operate independently 1 TRD0 and TRD1 registers operate synchronously Nothi...

Page 189: ...in the input capture function PWMD1 PWM mode of TRDIOD1 selection bit PWM mode of TRDIOB1 selection bit Set to 0 timer mode in the input capture function RW RW Nothing is assigned If necessary set to 0 When read the content is 1 Set to 0 timer mode in the input capture function PWM mode of TRDIOD0 selection bit Set to 0 timer mode in the input capture function PWMD0 RW RW PWMC0 RW PWM mode of TRDI...

Page 190: ...onous PWM mode or complementary PWM mode This bit is disabled in the input capture function Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 count stops OLS0 RW RW Counter phase output level selection bit in reset synchronous PWM mode or complementary PWM mode This bit is disabled in the input capture function A D trigger enable bit in complementary...

Page 191: ...tal filter function selection bit 0 Function is not used 1 Function is used TRDIOB pin digital filter function selection bit 0 Function is not used 1 Function is used RW RW TRDIOD pin digital filter function selection bit 0 Function is not used 1 Function is used TRDIOC pin digital filter function selection bit 0 Function is not used 1 Function is used Nothing is assigned If necessary set to 0 Whe...

Page 192: ...0 b1 b0 TCK2 This bit is enabled w hen the SYNC bit in the TRDMR register is set to 1 TRD0 and TRD1 registers operate synchronously This bit is enabled w hen the TCK2 to TCK0 bits are set to 101b TRDCLK input and the STCLK bit in the TRDFCR register is set to 1 external clock input enabled RW CKEG1 CCLR0 RW b7 b6 b5 0 0 0 Disable clear free running operation 0 0 1 Clear by the input capture in the...

Page 193: ... a buffer register of TRDGRBi register for this bit by the BFDi bit in the TRDMR register set the IOD2 bit in the TRDIORCi register to the same value as the IOB2 bit in the TRDIORAi register RW RW b7 IOB2 RW TRDGRB control bit b5 b4 0 0 Input capture to the TRDGRBi register at the rising edge 0 1 Input capture to the TRDGRBi register at the falling edge 1 0 Input capture to the TRDGRBi register at...

Page 194: ...FCi bit in the TRDMR register set the IOC2 bit in the TRDIORCi register to the same value as the IOA2 bit in the TRDIORAi register TRDGRD mode selection bit 2 Set to 1 input capture in the input capture function RW IOD3 IOD2 RW TRDGRD control bit b5 b4 0 0 Input capture to the TRDGRDi register at the rising edge 0 1 Input capture to the TRDGRDi register at the falling edge 1 0 Input capture to the...

Page 195: ...bit to 0 Write 0 after read 2 Source for setting this bit to 1 TRDSR0 register fOCO128 signal edge w hen the IOA3 bit in the TRDIORA0 register is set to 0 fOCO128 signal TRDIOA0 pin input edge w hen the IOA3 bit in the TRDIORA0 register is set to 1 TRDIOA0 input 3 TRDSR1 register Input edge of TRDIOA1 pin 3 Input capture compare match flag B Source for setting this bit to 0 Write 0 after read 2 So...

Page 196: ...he IMFB bit IMIEA Input capture compare match interrupt enable bit C 0 Disable an interrupt IMIC by the IMFC bit 1 Enable an interrupt IMIC by the IMFC bit IMIEC RW RW Input capture compare match interrupt enable bit D 0 Disable an interrupt IMID by the IMFD bit 1 Enable an interrupt IMID by the IMFD bit Overflow underflow interrupt enable bit 0 Disable an interrupt OVI by the OVF bit 1 Enable an ...

Page 197: ...re Input Pin TRDGRAi General register The value in the TRDi register can be read at the input capture TRDIOAi TRDGRBi TRDIOBi TRDGRCi BFCi 0 General register The value in the TRDi register can be read at the input capture TRDIOCi TRDGRDi BFDi 0 TRDIODi TRDGRCi BFCi 1 Buffer register The value in the TRDi register can be read at the input capture Refer to 14 3 2 Buffer Operation TRDIOAi TRDGRDi BFD...

Page 198: ...input for the count source The CKEG1 to CKEG0 bits in the TRDCRi register are set to 01b count at the falling edge for the count source The IOA2 to IOA0 bits in the TRDIORAi register are set to 101b input capture at the falling edge of the TRDIOAi input The BFCi bit in the TRDMR register is set to 1 The TRDGRCi register is used as the buffer register of the TRDGRAi register Count value in TRDi reg...

Page 199: ...k period selected by the TCK2 to TCK0 bits or DFCK1 to DFCK0 bits Sampling clock TRDIOji input signal Input signal through digital filtering Transmission cannot be performed without 3 times match because the input signal is assumed as noise Signal transmission delayed up to 5 sampling clock Recognition of the signal change with 3 time match f32 f8 f1 i 0 or 1 j either A B C or D TCK0 to TCK2 Bits ...

Page 200: ...14 59 list the Registers Associated with Output Compare Function and Figure 14 60 shows the Operating Example of Output Compare Function Figure 14 47 Block Diagram of Output Compare Function TRDIOA0 Output control Comparator TRDGRA0 TRD0 TRDIOC0 Output control Comparator TRDGRC0 Compare match signal TRDIOB0 Output control Comparator TRDGRB0 TRDIOD0 Output control Comparator TRDGRD0 Channel 0 TRDIO...

Page 201: ...TRDIOA0 Pin Function Programmable I O port output compare output or TRDCLK external clock input TRDIOB0 TRDIOC0 TRDIOD0 TRDIOA1 to TRDIOD1 Pin Functions Programmable I O port or output compare output select every pin INT0 Pin Function Programmable I O port pulse output forced cutoff signal input or INT0 interrupt input Read from Timer The count value can be read by reading the TRDi register Write ...

Page 202: ... TSTART0 When the CSEL0 bit is set to 1 w rite 0 to the TSTART0 bit When the CSEL1 bit is set to 1 w rite 0 to the TSTART1 bit When the CSEL0 bit is set to 0 and generating the compare match signal TRDIOA0 this bit is set to 0 count stops When the CSEL1 bit is set to 0 and generating the compare match signal TRDIOA1 this bit is set to 0 count stops Timer RD Mode Register Symbol Address After Reset...

Page 203: ...M mode of TRDIOC0 selection bit Set to 0 timer mode in the output compare function PWM mode of TRDIOB1 selection bit Set to 0 timer mode in the output compare function RW RW Nothing is assigned If necessary set to 0 When read the content is 1 Set to 0 timer mode in the output compare function PWM mode of TRDIOD0 selection bit Set to 0 timer mode in the output compare function PWMD0 RW b7 PWMB1 PWM...

Page 204: ...nous PWM mode or complementary PWM mode This bit is disabled in the output compare function Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 count stops OLS0 RW RW Counter phase output level selection bit in reset synchronous PWM mode or complementary PWM mode This bit is disabled in the output compare function A D trigger enable bit in complementar...

Page 205: ...put disable bit 0 Enable output 1 Disable output The TRDIOD0 pin is used as a programmable I O port TRDIOC1 output disable bit 0 Enable output 1 Disable output The TRDIOC1 pin is used as a programmable I O port EC1 RW EA1 EB1 RW TRDIOD1 output disable bit 0 Enable output 1 Disable output The TRDIOD1 pin is used as a programmable I O port TRDIOB1 output disable bit 0 Enable output 1 Disable output ...

Page 206: ...lection bit TRDIOC0 initial output level selection bit Write to the TRDOCR register w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 count stops TOC0 RW RW TRDIOA1 initial output level selection bit RW RW TRDIOD0 initial output level selection bit TOD1 RW RW TOB0 RW TRDIOA0 output level selection bit 0 Initial output L 1 Initial output H TRDIOB0 output level selection bi...

Page 207: ...2 CKEG0 b1 b0 TCK2 This bit is enabled w hen the SYNC bit in the TRDMR register is set to 1 TRD0 and TRD1 operate synchronously This bit is enabled w hen the TCK2 to TCK0 bits are set to 101b TRDCLK input and the STCLK bit in the TRDFCR register is set to 1 external clock input enabled RW CKEG1 CCLR0 RW b7 b6 b5 0 0 0 Disable clear free running operation 0 0 1 Clear by the compare match in the TRD...

Page 208: ...bit 1 Set to 0 output compare in the output compare function RW IOB2 RW TRDGRB control bit b5 b4 0 0 Disable pin output by the compare match TRDIOBi pin functions as programmable I O port 0 1 L output by the compare match in the TRDGRBi register 1 0 H output by the compare match in the TRDGRBi 1 1 Toggle output by the compare match in the TRDGRBi register b7 b6 b5 b4 0 b3 b2 IOA3 b1 b0 1 0 IOA2 Wh...

Page 209: ...0 TRDGRC control bit b1 b0 0 0 Disable pin output by the compare match 0 1 L output by the compare match in the TRDGRCi register 1 0 H output by the compare match in the TRDGRCi register 1 1 Toggle output by the compare match in the TRDGRCi register RW TRDGRD control bit b5 b4 0 0 Disable pin output by the compare match 0 1 L output by the compare match in the TRDGRDi register 1 0 H output by the ...

Page 210: ... value in the TRDi register matches w ith the value in the TRDGRAi register Input capture compare match flag B Source for setting this bit to 0 Write 0 after read 2 Source for setting this bit to 1 When the value in the TRDi register matches w ith the value in the TRDGRBi register IMFA Input capture compare match flag C Source for setting this bit to 0 Write 0 after read 2 Source for setting this ...

Page 211: ...t IMID by the IMFD bit 1 Enable an interrupt IMID by the IMFD bit Overflow underflow interrupt enable bit 0 Disable an interrupt OVI by the OVF bit 1 Enable an interrupt OVI by the OVF bit RW IMIEB RW Input capture compare match interrupt enable bit A 0 Disable an interrupt IMIA by the IMFA bit 1 Enable an interrupt IMIA by the IMFA bit Input capture compare match interrupt enable bit B 0 Disable ...

Page 212: ...ster Write the compare value TRDIOCi TRDGRDi TRDIODi TRDGRCi 1 1 Buffer register Write the next compare value refer to 14 3 2 Buffer Operation TRDIOAi TRDGRDi TRDIOBi TRDGRCi 0 0 TRDIOAi output control refer to 14 3 6 1 Changing Output Pins in Registers TRDGRCi i 0 or 1 and TRDGRDi TRDIOAi TRDGRDi TRDIOBi Timer RD General Register Ai Bi Ci and Di i 0 or 1 1 Symbol Address After Reset TRDGRA0 TRDGR...

Page 213: ...DOER1 register are set to 0 Enable the TRDIOAi TRDIOBi and TRDIOCi pin outputs The CCLR2 to CCLR0 bits in the TRDCRi register are set to 001b Set the TRDi register to 000h by the compare match in the TRDGRAi register The TOAi and TOBi bits in the TRDOCR register is set to 0 initial output L to the compare match the TOCi bit is set to 1 initial output H to the compare match The IOA2 to IOA0 bits in...

Page 214: ...D bit in the TRDIORCi register Set the BFji bit in the TRDMR register to 0 general register Set the different value in the TRDGRCi register and the TRDGRAi register Also set the different value in the TRDGRDi register and the TRDGRBi register TRDIOA0 Output control Comparator TRDGRA0 TRD0 TRDIOC0 Output control Comparator TRDGRC0 Compare match signal TRDIOB0 Output control Comparator TRDGRB0 TRDIO...

Page 215: ...The EAi and EBi bits in the TRDOER1 register are set to 0 Enable TRDIOAi and TRDIOBi pin outputs The CCLR2 to CCLR0 bits in the TRDCRi register are set to 001b Set the TRDi register to 0000h by the compare match in the TRDGRAi register The TOAi and TOBi bits in the TRDOCR register are set to 0 initial output L to the compare match The IOA2 to IOA0 bits in the TRDIORAi register are set to 011b TRDI...

Page 216: ...ot be used for other modes Figure 14 63 shows the Block Diagram of PWM Mode Table 14 27 lists the PWM Mode Specifications Figures 14 64 to 14 73 show the Registers Associated with PWM Mode and Figures 14 74 to 14 75 show the Operations of PWM Mode Figure 14 63 Block Diagram of PWM Mode TRDIOBi Output control TRDGRAi TRDi Compare match signal TRDGRBi TRDIOCi TRDGRCi TRDGRDi TRDIODi Note 1 Note 2 i ...

Page 217: ...utput pin holds level after output change by the compare match Interrupt Request Generation Timing Compare match the content in the TRDi register matches with the content in the TRDGRhi register TRDi register overflows TRDIOA0 Pin Function Programmable I O port or TRDCLK external clock input TRDIOA1 Pin Function Programmable I O port TRDIOB0 TRDIOC0 TRDIOD0 TRDIOB1 TRDIOC1 TRDIOD1 Pin Functions Pr...

Page 218: ...ister CSEL0 RW RW TRD1 count operation select bit 0 Count stops at the compare match w ith the TRDGRA1 register 1 Count continues at the compare match w ith the TRDGRA1 register b7 b4 RW TSTART1 RW TRD1 count start flag 5 0 Count stops 3 1 Count starts TRD0 count start flag 4 0 Count stops 2 1 Count starts Nothing is assigned When w rite set to 0 When read its content is 1 b7 b6 b5 b4 b3 b2 CSEL1 ...

Page 219: ...nous bit 0 TRD0 and TRD1 registers operate independently 1 TRD0 and TRD1 registers operate synchronously Nothing is assigned If necessary set to 0 When read the content is 1 b7 b6 b5 b4 b3 b2 BFD0 b1 b0 SYNC Timer RD PWM Mode Register Symbol Address After Reset TRDPMR 0139h 10001000b Bit Symbol Bit Name Function RW Nothing is assigned If necessary set to 0 When read the content is 1 PWM mode of TR...

Page 220: ...selection bit in reset synchronous PWM mode or complementary PWM mode This bit is disabled in PWM mode Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 count stops OLS0 RW RW Counter phase output level selection bit in reset synchronous PWM mode or complementary PWM mode This bit is disabled in PWM mode A D trigger enable bit in complementary PWM mo...

Page 221: ... 0 Enable output 1 Disable output The TRDIOC1 pin is used as a programmable I O mode TRDIOC0 output disable bit 0 Enable output 1 Disable output The TRDIOC0 pin is used as a programmable I O mode EC0 RW ED1 RW EA1 EB1 RW TRDIOD1 output disable bit 0 Enable output 1 Disable output The TRDIOD1 pin is used as a programmable I O mode TRDIOB1 output disable bit 0 Enable output 1 Disable output The TRDI...

Page 222: ...initial output level selection bit 2 TOA0 b7 b6 b5 b4 0 When the pin functions are w aveform output refer to Table 14 13 to 14 15 Table 14 17 to 14 19 and the TRDOCR register is set the initial output level is output b3 b2 TOD0 b1 b0 0 Timer RD Control Register i i 0 or 1 Symbol Address After Reset TRDCR0 TRDCR1 0140h 0150h 00h 00h Bit Symbol Bit Name Function RW NOTES 1 2 This bit is enabled w he...

Page 223: ...lue in the TRDi register matches w ith the value in the TRDGRDi register 3 Overflow flag Source for setting this bit to 0 Write 0 after read 2 Source for setting this bit to 1 When the TRDi register overflow s RW IMFB RW Input capture compare match flag A Source for setting this bit to 0 Write 0 after read 2 Source for setting this bit to 1 When the value in the TRDi register matches w ith the val...

Page 224: ...C by the IMFC bit 1 Enable an interrupt IMIC by the IMFC bit IMIEC RW RW Input capture compare match interrupt enable bit D 0 Disable an interrupt IMID by the IMFD bit 1 Enable an interrupt IMID by the IMFD bit Overflow underflow interrupt enable bit 0 Disable an interrupt OVI by the OVF bit 1 Enable an interrupt OVI by the OVF bit RW IMIEB RW Input capture compare match interrupt enable bit A 0 D...

Page 225: ...evel is selected PWM mode output level control bit C 0 L active of TRDIOCi output level is selected 1 H active of TRDIOCi output level is selected POLB Nothing is assigned If necessary set to 0 When read the content is 1 PWM mode output level control bit D 0 L active of TRDIODi output level is selected 1 H active of TRDIODi output level is selected RW Timer RD Counter i i 0 or 1 1 Symbol Address A...

Page 226: ...er Set the changing point of PWM output TRDIOCi TRDGRDi BFDi 0 TRDIODi TRDGRCi BFCi 1 Buffer register Set the next PWM period refer to 14 3 2 Buffer Operation TRDGRDi BFDi 1 Buffer register Set the changing point of the next PWM output refer to 14 3 2 Buffer Operation TRDIOBi Timer RD General Register Ai Bi Ci and Di i 0 or 1 1 Symbol Address After Reset TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA1 TRD...

Page 227: ...program Set to 0 by a program TRDIOBi output IMFA bit in TRDSRi register 1 0 IMFB bit in TRDSRi register 1 0 IMFC bit in TRDSRi register 1 0 IMFD bit in TRDSRi register 1 0 i 0 or 1 Set to 0 by a program The above applies to the following conditions The BFCi and BFDi bits in the TRDMR register are set to 0 The TRDGRCi and TRDGRDi registers are not used as the buffer register The EBi ECi and EDi bi...

Page 228: ...i register n 0000h TRDGRBi register IMFA bit in TRDSRi register 1 0 IMFB bit in TRDSRi register 1 0 TSTARTi bit in TRDSTR register TRDIOBi output p n 1 0 L is applied to TRDIOBi output by the compare match in the TRDGRBi register with no change m i 0 or 1 The above applies to the following conditions The EBi bit in the TRDOER1 register is set to 0 Enable TRDIOBi output The POLB bit in the TRDPOCRi...

Page 229: ... and Figure 14 85 shows the Operating Example of Reset Synchronous PWM Mode Refer to Figure 14 75 Operating Example of PWM Mode Duty 0 Duty 100 for the operation example in PWM Mode of duty 0 and duty 100 Figure 14 76 Block Diagram of Reset Synchronous PWM Mode Period TRDIOC0 TRDIOB0 TRDIOD0 TRDIOA1 TRDIOC1 TRDIOB1 TRDIOD1 PWM1 PWM2 PWM3 Waveform control TRDGRB0 register TRDGRA1 register TRDGRB1 r...

Page 230: ...the TRDGRA0 register The PWM output pin holds level after output change by the compare match Interrupt Request Generation Timing Compare match the content in the TRD0 register matches with the content in the TRDGRj0 TRDGRA1 and TRDGRB1 registers The TRD0 register overflows TRDIOA0 Pin Function Programmable I O port or TRDCLK external clock input TRDIOB0 Pin Function PWM output 1 normal phase outpu...

Page 231: ... 1 Count continues at the compare match w ith the TRDGRA1 register TRD0 count operation select bit 0 Count stops at the compare match w ith the TRDGRA0 register 1 Count continues at the compare match w ith the TRDGRA0 register CSEL0 RW RW TSTART1 RW TRD1 count start flag 5 This bit is not used in reset synchronous PWM mode 0 Count stops 3 1 Count starts TRD0 count start flag 4 0 Count stops 2 1 Co...

Page 232: ...re set to 00b timer mode PWM mode or PWM3 mode the setting of the PWM3 bit is enabled b3 b2 OLS1 b1 b0 0 1 b7 b6 b5 b4 RW CMD1 RW Combination mode selection bit 1 2 Set to 01b reset synchronous PWM mode in reset synchronous PWM mode CMD0 Normal phase output level selection bit in reset synchronous PWM mode or complementary PWM mode 0 Initial output H Active level L 1 Initial output L Active level ...

Page 233: ...Disable output the TRDIOC1 pin is used as a programmable I O port TRDIOC0 output disable bit 0 Enable output 1 Disable output the TRDIOC0 pin is used as a programmable I O port EC0 RW RW EB0 RW TRDIOA0 output disable bit Set this bit to 1 the TRDIOA0 pin is used as a programmable I O port in reset synchronous PWM mode TRDIOB0 output disable bit 0 Enable output 1 Disable output the TRDIOB0 pin is u...

Page 234: ...ock edge selection bit 2 b4 b3 0 0 Count at the rising edge 0 1 Count at the falling edge 1 0 Count at both edges 1 1 Do not set b7 b6 b5 b4 0 0 1 b3 b2 CKEG0 b1 b0 TCK2 The TRDCR1 register is not used in reset synchronous PWM mode This bit is enabled w hen the TCK2 to TCK0 bits are set to 101b TRDCLK input and the STCLK bit in the TRDFCR register is set to 1 external clock input enabled RW CKEG1 ...

Page 235: ...bit to 1 When the value in the TRDi register matches w ith the value in the TRDGRDi register 3 Overflow flag Source for setting this bit to 0 Write 0 after read 2 Source for setting this bit to 1 When the TRDi register overflow s RW IMFB RW Input capture compare match flag A Source for setting this bit to 0 Write 0 after read 2 Source for setting this bit to 1 When the value in the TRDi register m...

Page 236: ... Input capture compare match interrupt enable bit C 0 Disable an interrupt IMIC by the IMFC bit 1 Enable an interrupt IMIC by the IMFC bit IMIEC RW RW Input capture compare match interrupt enable bit D 0 Disable an interrupt IMID by the IMFD bit 1 Enable an interrupt IMID by the IMFD bit Overflow underflow interrupt enable bit 0 Disable an interrupt OVI by the OVF bit 1 Enable an interrupt OVI by ...

Page 237: ... TRDIOD1 TRDGRC1 BFC1 0 These points are not used in reset synchronous PWM mode TRDGRD1 BFD1 0 TRDGRC0 BFC0 1 Buffer register Set the next PWM period Refer to 14 3 2 Buffer Operation Output inverted every period of TRDIOC0 and PWM pins TRDGRD0 BFD0 1 Buffer register Set the changing point of the next PWM1 output Refer to 14 3 2 Buffer Operation TRDIOB0 TRDIOD0 TRDGRC1 BFC1 1 Buffer register Set th...

Page 238: ...output IMFA bit in TRDSR0 register 1 0 IMFB bit in TRDSR0 register 1 0 IMFA bit in TRDSR1 register 1 0 IMFB bit in TRDSR1 register 1 0 TSTARTi bit in TRDSTR register 1 0 n 1 TRDIOC1 output TRDIOA1 output m q m p TRDIOB1 output TRDIOC0 output p 1 Initial output H i 0 or 1 The above applies to the following conditions The OLS1 and OLS0 bits in the TRDFCR register are set to 0 initial output level H ...

Page 239: ...ications Figures 14 87 to 14 95 show the Registers Associated with Complementary PWM Mode Figure 14 96 shows the Output Model of Complementary PWM Mode and Figure 14 97 shows the Operating Example of Complementary PWM Mode Figure 14 86 Block Diagram of Complementary PWM Mode Period TRDIOC0 TRDIOB0 TRDIOD0 TRDIOA1 TRDIOC1 TRDIOB1 TRDIOD1 PWM1 PWM2 PWM3 Waveform control TRDGRB0 register TRDGRA1 regi...

Page 240: ...TR register Count Stop Conditions Write 0 count stops to the TSTART0 and TSTART1 bits in the TRDSTR register when the CSEL0 bit in the TRDSTR register is set to 1 The PWM output pin holds output level before the count stops Interrupt Request Generation Timing Compare match the content in the TRDi register matches with the content in the TRDGRji register The TRD1 register undeflows TRDIOA0 Pin Func...

Page 241: ... signal TRDIOA1 this bit is set to 0 count stops Set the TRDSTR register using the MOV instruction do not use the bit handling instruction Refer to 14 3 12 1 TRDSTR Register of Notes on Timer RD TRD0 count operation select bit 0 Count stops at the compare match w ith the TRDGRA0 register 1 Count continues at the compare match w ith the TRDGRA0 register CSEL0 RW RW TRD1 count operation select bit 0...

Page 242: ...egister RW TRDGRC0 register function selection bit Set this bit to 0 general register in complementary PWM mode BFC0 RW RW TRDGRD0 register function selection bit 0 General register 1 Buffer register of TRDGRB0 register TRDGRC1 register function selection bit 0 General register 1 Buffer register of TRDGRA1 register RW b3 b1 Timer RD synchronous bit Set this bit to 0 The TRD0 and TRD1 registers ope...

Page 243: ... mode 0 Initial output H Active level L 1 Initial output L Active level H Set bits CMD1 to CMD0 w hen both the TSTART0 and TSTART1 bits in the TRDSTR register are set to 0 count stops OLS0 RW RW Counter phase output level selection bit in reset synchronous PWM mode or complementary PWM mode 0 Initial output H Active level L 1 Initial output L Active level H A D trigger enable bit in complementary ...

Page 244: ...utput The TRDIOC0 pin is used as a programmable I O port EC0 RW RW TRDIOA1 output disable bit 0 Enable output 1 Disable output The TRDIOA1 pin is used as a programmable I O port RW RW RW EB0 RW TRDIOA0 output disable bit Set this bit to 1 The TRDIOA0 pin is used as a programmable I O port in complementary PWM mode TRDIOB0 output disable bit 0 Enable output 1 Disable output The TRDIOB0 pin is used ...

Page 245: ...External clock edge selection bit 2 3 b4 b3 0 0 Count at the rising edge 0 1 Count at the falling edge 1 0 Count at both edges 1 1 Do not set b7 b6 b5 b4 0 0 0 b3 b2 CKEG0 b1 b0 TCK2 This bit is enabled w hen the TCK2 to TCK0 bits are set to 101b TRDCLK input and the STCLK bit in the TRDFCR register is set to 1 external clock input enabled RW CKEG1 CCLR0 RW Set to 000b disable clear free running o...

Page 246: ...RCi register 3 Nothing is assigned to the bit 5 in the TRDSR0 register When w riting to the bit 5 w rite 0 When reading its content is 1 IMFC RW RW Input capture compare match flag D Source for setting this bit to 0 Write 0 after read 2 Source for setting this bit to 1 When the value in the TRDi register matches w ith the value in the TRDGRDi register 3 Overflow flag Source for setting this bit to...

Page 247: ...by the IMFC bit 1 Enable an interrupt IMIC by the IMFC bit IMIEC RW RW Input capture compare match interrupt enable bit D 0 Disable an interrupt IMID by the IMFD bit 1 Enable an interrupt IMID by the IMFD bit Overflow underflow interrupt enable bit 0 Disable an interrupt OVI by the OVF and UDF bits 1 Enable an interrupt OVI by the OVF and UDF bits RW IMIEB RW Input capture compare match interrupt ...

Page 248: ... 8 bit units b0 b7 b8 b0 b15 b7 Timer RD Counter 1 1 Symbol Address After Reset TRD1 0157h 0156h 0000h Setting Range RW NOTE 1 b8 b0 b15 b7 Access the TRD1 register in 16 bit units Do not access it in 8 bit units b0 b7 Function Select 0000h Count a count source Count operation is incremented or decremented When an underflow occurs the UDF bit in the TRDSR1 register is set to 1 0000h to FFFFh RW Ti...

Page 249: ...g range Setting value or above in TRD0 register TRDGRA0 register TRD0 register setting value or below Do not write when the TSTART0 and TSTART1 bits in the TRDSTR register are set to 1 count starts TRDIOA1 TRDIOC1 TRDGRB1 General register Set the changing point of PWM3 output at initialization Setting range Setting value or above in TRD0 register TRDGRA0 register TRD0 register setting value or bel...

Page 250: ...f Complementary PWM Mode Value in TRDi register TRDIOD0 output 0000h Value in TRDGRA0 register Value in TRDGRB0 register Value in TRDGRA1 register Value in TRDGRB1 register TRDIOB0 output TRDIOC1 output TRDIOA1 output TRDIOD1 output TRDIOB1 output TRDIOC0 output Value in TRD0 register Value in TRD1 register i 0 or 1 ...

Page 251: ...2 Width of normal phase active level Dead time n 1 p 2 Width of counter phase active level Set to FFFFh 1 0 UDF bit in TRDSR1 register 1 0 Following data Modify with a program TRDGRD0 register Transfer When the CMD1 to CMD0 bits are set to 11b Transfer When the CMD1 to CMD0 bits are set to 10b Value in TRD1 register Value in TRD0 register CMD0 CMD1 Bits in TRDFCR register i 0 or 1 The above applie...

Page 252: ... 10b the content is transferred when the TRD1 register underflows When the CMD1 to CMD0 bits are set to 11b the content is transferred at the compare match in the TRD0 and TRDGRA0 registers 14 3 9 2 A D Trigger Generation The compare match in the TRD0 and TRDGRA0 registers and the TRD1 underflow can be used as a conversion start trigger of the A D converter It can be selected by the ADEG and ADTRG...

Page 253: ... Specifications Figures 14 99 to 14 107 show the Registers Associated with PWM3 Mode and Figure 14 108 shows the Operating Example of PWM3 Mode Figure 14 98 Block Diagram of PWM3 Mode TRDIOA0 Output control TRDGRC0 Compare match signal TRDIOB0 Output control Comparator TRDGRA0 TRD0 TRDGRC1 Compare match signal Comparator TRDGRA1 TRDGRD0 Comparator TRDGRB0 TRDGRD1 Comparator TRDGRB1 Compare match s...

Page 254: ...output pin holds output level before the count stops When the CSEL0 bit in the TRDSTR register is set to 0 the count stops at the compare match in the TRDGRA0 register The PWM output pin holds level after output change by the compare match Interrupt Request Generation Timing Compare match the content in the TRDi register matches with the content in the TRDGRji register The TRD0 register overflows ...

Page 255: ... register 1 Count continues at the compare match w ith the TRDGRA1 register TRD0 count operation select bit 0 Count stops at the compare match w ith the TRDGRA0 register 1 Count continues at the compare match w ith the TRDGRA0 register CSEL0 RW RW TSTART1 RW TRD1 count start flag 5 Set this bit to 0 count stops in PWM3 mode 3 TRD0 count start flag 4 0 Count stops 2 1 Count starts b7 b6 b5 b4 b3 b2...

Page 256: ...FCR 013Ah 10000000b Bit Symbol Bit Name Function RW NOTES 1 2 STCLK External clock input selection bit Set this bit to 0 external clock input disabled in PWM3 mode RW RW PWM3 RW ADTRG ADEG A D trigger edge selection bit enabled in complementary PWM mode This bit is disabled in PWM3 mode RW PWM3 mode selection bit 2 Set this bit to 0 PWM3 mode in PWM3 mode Normal phase output level selection bit en...

Page 257: ...output 1 Disable output The TRDIOA0 pin is used as a programmable I O port TRDIOB0 output disable bit 0 Enable output 1 Disable output The TRDIOB0 pin is used as a programmable I O port 1 1 1 1 b7 b6 b5 b4 b3 b2 ED0 b1 b0 1 1 EA0 Timer RD Output Master Enable Register 2 Symbol Address After Reset TRDOER2 013Ch 01111111b Bit Symbol Bit Name Function RW INT0 _____ of pulse output forced 0 Pulse outp...

Page 258: ...START0 and TSTART1 bits in the TRDSTR register are set to 0 count stops TOC0 RW RW TRDIOA1 initial output level selection bit RW RW TRDIOD0 initial output level selection bit TOD1 RW RW TOB0 RW TRDIOA0 output level selection bit 2 0 Active level H initial output L output H by the compare match in the TRDGRA1register output L by the compare match in the TRDGRA0 register 1 Active level L initial out...

Page 259: ...0 0 1 f2 0 1 0 f4 0 1 1 f8 1 0 0 f32 1 0 1 Do not set 1 1 0 fOCO40M 1 1 1 Do not set External clock edge selection bit 1 This bit is disabled in PWM3 mode b7 b6 b5 b4 0 0 1 b3 b2 CKEG0 b1 b0 TCK2 The TRDCR1 register is not used in PWM3 mode RW CKEG1 CCLR0 RW Set to 001b the TRD0 register clear at the compare match w ith TRDGRA0 register in PWM3 mode TRD0 counter clear selection bit This bit is ena...

Page 260: ... Source for setting this bit to 1 When the value in the TRDi register matches w ith the value in the TRDGRCi register 2 IMFC Overflow flag Source for setting this bit to 0 Write 0 after read 1 Source for setting this bit to 1 When the TRDi register overflow s RW RW Input capture compare match flag D Source for setting this bit to 0 Write 0 after read 1 Source for setting this bit to 1 When the val...

Page 261: ...capture compare match interrupt enable bit C 0 Disable an interrupt IMIC by the IMFC bit 1 Enable an interrupt IMIC by the IMFC bit IMIEC RW RW Input capture compare match interrupt enable bit D 0 Disable an interrupt IMID by the IMFD bit 1 Enable an interrupt IMID by the IMFD bit Overflow underflow interrupt enable bit 0 Disable an interrupt OVI by the OVF bit 1 Enable an interrupt OVI by the OVF...

Page 262: ...DPOCR1 Timer RD General Register Ai Bi Ci and Di i 0 or 1 1 Symbol Address After Reset TRDGRA0 TRDGRB0 TRDGRC0 TRDGRD0 TRDGRA1 TRDGRB1 TRDGRC1 TRDGRD1 0149h 0148h 014Bh 014Ah 014Dh 014Ch 014Fh 014Eh 0159h 0158h 015Bh 015Ah 015Dh 015Ch 015Fh 015Eh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh FFFFh RW NOTE 1 RW Function Refer to Table 14 34 TRDGRji Register Functions in PWM3 Mode Access the TRDGRAi to ...

Page 263: ...to initial output level of PWM output Setting range Value set in TRDGRB1 register or above Value set in TRDGRA0 register or below TRDIOB0 TRDGRB1 General register Set the changing point active level timing of PWM output Setting range Value set in TRDGRB0 register or below TRDGRC0 BFC0 0 These registers are not used in PWM3 mode TRDGRC1 BFC1 0 TRDGRD0 BFD0 0 TRDGRD1 BFD1 0 TRDGRC0 BFC0 1 Buffer reg...

Page 264: ... by a program Set to 0 by a program Transfer m m Following data Transfer m Output L by the compare match in the TRDGRA0 register Transfer from the buffer register to general register Transfer from the buffer register to general register Initial output L j either A or B The above applies to the following conditions Both the TOA0 and TOB0 bits in the TRDOCR register are set to 0 initial output level...

Page 265: ...ding to bits in the TRDSRi register or both of them are set to 0 the IR bit is set to 0 interrupt not requested Therefore even though the interrupt is not acknowledged after the IR bit is set to 1 the interrupt request will not be maintained When the conditions of other request sources are met the IR bit remains 1 When multiple bits in the TRDIERi register are set to 1 which request source causes ...

Page 266: ...each mode Figures 14 41 14 56 14 69 14 81 14 92 and 14 104 for the TRDSRi register Refer to TRDIER0 to TRDIER1 Registers in each mode Figures 14 42 14 57 14 70 14 82 14 93 and 14 105 for the TRDIERi register Refer to 12 1 6 Interrupt Control for the TRDiIC register and 12 1 5 2 Relocatable Vector Tables for the interrupt vector ...

Page 267: ...r is set to 0000h These precautions are applicable when selecting the following by the CCLR2 to CCLR0 bits in the TRDCRi register 001b clear by the TRDi register at the compare match with the TRDGRAi register 010b clear by the TRDi register at the compare match with the TRDGRBi register 011b synchronous clear 101b clear by the TRDi register at the compare match with the TRDGRCi register 110b clear...

Page 268: ... 0 count stops 2 Set the CMD1 to CMD0 bits in the TRDFCR register to 00b timer mode PWM mode and PWM3 mode 3 Set the CMD1 to CMD0 bits to 01b reset synchronous PWM mode 4 Set the registers associated with other Timer RD again 14 3 12 7 Complementary PWM Mode When complementary PWM mode is used for motor control use it with OLS0 OLS1 Change the CMD1 to CMD0 bits in the TRDFCR register in the follow...

Page 269: ...to the general register TRDGRB0 TRDGRA1 TRDGRB1 For the order of m 1 m m 1 operation the IMFA bit remains unchanged and data are not transferred to the register such as the TRDGRA0 register Figure 14 110 Operation at Compare Match between Registers TRD0 and TRDGRA0 in Complementary PWM Mode No change IMFA bit in TRDSR0 register Transferred from buffer register TRDGRB0 register TRDGRA1 register TRD...

Page 270: ...eral register TRDGRB0 TRDGRA1 TRDGRB1 For the order of FFFFh 0 1 operation data are not transferred to the register such as the TRDGRB0 register Also at this time the OVF bit remains unchanged Figure 14 111 Operation When TRD1 Register Underflows in Complementary PWM Mode No change UDF bit in TRDSR0 register Transferred from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register Count ...

Page 271: ...MD1 to CMD0 bits Figure 14 112 Operation When Value in Buffer Register Value in TRDGRA0 Register in Complementary PWM Mode 0000h TRDGRD0 register TRDIOB0 output n3 n2 m 1 n3 n2 n1 n2 n1 n3 n2 n2 n1 n1 TRDGRB0 register Transfer Transfer by underflow in TRD1 register because of n3 m Transfer by underflow in TRD1 register because of first setting to n2 m TRDIOD0 output m Setting Value in TRDGRA0 Regi...

Page 272: ...ge other than that do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b select fOCO40M as the count source 0000h TRDGRD0 register TRDIOB0 output n1 m 1 n 2 n1 0000h n1 0000h n1 n1 n2 TRDGRB0 register Transfer Transfer by compare match in TRD0 and TRDGRA0 registers because content in TRDGRD0 register is set to 0000h Transfer by compare match in TRD0 and TRDGRA0 registers because of fi...

Page 273: ...J09B0250 0200 14 4 Timer RE Timer RE has the 4 bit counter and 8 bit counter Timer RE has the following mode Output compare mode Count a count source and detect the compare match The count source for timer RE is the operating clock that regulates the timing of timer operations ...

Page 274: ...utput Compare Mode Specifications Figures 14 115 to 14 119 show the Registers Associated with Output Compare Mode and Figure 14 120 shows the Operation in Output Compare Mode Figure 14 114 Block Diagram of Output Compare Mode TOENA TREO pin f32 f4 f8 4 bit counter 8 bit counter TRESEC Comparison circuit TREMIN 1 2 RCS2 1 RCS2 0 COMIE Timer RE interrupt f2 Match signal 00b 01b 10b RCS1 to RCS0 RCS6...

Page 275: ...r Interrupt Request Generation Timing When the 8 bit counter content matches with the TREMIN register content TREO Pin Function Select any one of the followings Programmable I O ports Output any one of f2 f4 and f8 Compare output Read from Timer When reading the TRESEC register the 8 bit counter value can be read When reading the TREMIN register the compare value can be read Write to Timer Writing...

Page 276: ...t Compare Mode Timer RE Counter Data Register Symbol Address After Reset TRESEC 0118h 00h RW Function 8 bit counter data can be read Although Timer RE stops counting the count value is held The TRESEC register is set to 00h w ith the compare match b7 b0 RO Timer RE Compare Data Register Symbol Address After Reset TREMIN 0119h 00h RW Function 8 bit compare data is stored b7 b0 RW ...

Page 277: ...tart bit 0 Count stops 1 Count starts RW b6 b5 Reserved bit Set to 0 TRERST Timer REreset bit When setting this bit to 0 after setting it to 1 the follow ings w ill occur The TRESEC TREMIN and TRECR2 registers are set to 00h The TCSTF INT and TSTART bits in the TRECR1 register are set to 0 The 8 bit counter is set to 00h and the 4 bit counter is set to 0h RW RW Interrupt request timing bit Set to ...

Page 278: ...b4 RW RCS1 RW Count source select bit b1 b0 0 0 f4 0 1 f8 1 0 f32 1 1 Do not set 4 bit counter select bit 0 Not used 1 Used Write to the RCS5 to RCS6 bits w hen the TOENA bit in the TRECR1 register is set to 0 disable clock output RCS2 RW RW b7 Reserved bit Set to 0 Nothing is assigned If necessary set to 0 When read the content is 0 RW RCS6 RW RCS5 b4 Nothing is assigned If necessary set to 0 Whe...

Page 279: ...n TREIC register 1 0 The above applies to the following conditions TOENA bit in TRECR1 register 1 enable clock output COMIE bit in TRECR2 register 1 enable compare match interrupt RCS6 to RCS5 bits in TRECSR register 11b compare output Set to 1 by a program Set to 0 by acknowledgement of interrupt request or a program TREMIN register setting value Matched TREO output 1 0 TCSTF bit in TRECR1 regist...

Page 280: ...Also timer RE stops counting when setting the TSTART bit to 0 count stops and the TCSTF bit is set to 0 count stops It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0 During this time do not access registers associated with timer RE other than the TCSTF bit NOTE 1 Registers associated with Timer RE TRESEC TREMIN TRECR1 TRECR2 ...

Page 281: ...ciated with UARTi Figure 15 1 UARTi i 0 or 1 Block Diagram 01b f8 f1 10b CLK1 to CLK0 RXD0 f32 1 16 1 16 1 2 1 n0 1 UART reception UART transmission Clock synchronous type when internal clock is selected Clock synchronous type Reception control circuit Transmission control circuit CKDIR 0 CKDIR 1 Receive clock Transmit clock Transmit receive unit U0BRG register CKDIR 0 Internal External CKDIR 1 UA...

Page 282: ...r bits Data bus low order bits D7 D6 D5 D4 D3 D2 D1 D0 UiTB register D8 TXDi 1SP 2SP SP SP PAR UARTi transmit register 0 i 0 or 1 SP Stop bit PAR Parity bit NOTE 1 Clock synchronous type is provide in UART0 only UART 7 bits UART 8 bits Clock synchronous type Clock synchronous type UART 7 bits Clock synchronous type UART 7 bits Clock synchronous type UART 8 bits UART 9 bits UART 7 bits UART 8 bits ...

Page 283: ...y error RO FER Framing error flag 2 0 No framing error 1 Framing error RO Nothing is assigned If necessary set to 0 When read the content is indeterminate b11 b9 Read out the UiRB register in 16 bit unit The SUM PER FER and OER bits are set to 0 no error w hen the SMD2 to SMD0 bits in the UiMR register are set to 000b serial interface disabled or the RE bit in the U0C1 register is set to 0 receive...

Page 284: ...O mode in UART1 Internal external clock select bit 3 0 Internal clock 1 External clock 1 Stop bit length select bit b7 Reserved bit RW Odd even parity select bit PRYE Parity enable bit 0 Parity disabled 1 Parity enabled PRY RW Set to 0 Set the PD1_6 bit in the PD1 register to 0 input SMD2 RW RW STPS RW 0 1 stop bit 1 2 stop bits CKDIR RW RW Serial I O mode select bit 2 4 b2 b1 b0 0 0 0 Serial inte...

Page 285: ...set to 0 When read the content is 0 b2 CKPOL CLK1 RW BRG count source select bit 1 b1 b0 0 0 Selects f1 0 1 Selects f8 1 0 Selects f32 1 1 Do not set RW RW RO b4 Reserved bit b7 b6 b5 b4 b3 b2 TXEPT b1 b0 0 CLK0 UARTi Transmit Receive Control Register 1 i 0 or 1 Symbol Address After Reset U0C1 00A5h 00000010b U1C1 00ADh 00000010b Bit Symbol Bit Name Function RW NOTES 1 2 Set the UiRRM bit to 0 dis...

Page 286: ...sult UART1 can be used as the clock asynchronous serial I O Do not set values other than 03h When read its content is indeterminate Port Mode Register Symbol Address After Reset PMR 00F8h 00h Bit Symbol Bit Name Function RW IICSEL RW 0 SSU function selects 1 I2 C bus function selects Set to 0 0 I O port P6_6 P6_7 1 TXD1 RXD1 Set to 0 Reserved bits SSU I2 C bus sw itch bit RW b0 0 Reserved bits U1P...

Page 287: ...in Transmit Start Conditions Before transmit starts the following requirements are required 1 The TE bit in the U0C1 register is set to 1 transmit enabled The TI bit in the U0C1 register is set to 0 data in the U0TB register Receive Start Conditions Before receive starts the following requirements are required 1 The RE bit in the U0C1 register is set to 1 receive enabled The TE bit in the U0C1 reg...

Page 288: ...rnal clock or external clock U0C0 CLK1 to CLK0 Select the count source in the U0BRG register TXEPT Transmit register empty flag NCH Select TXD0 pin output mode CKPOL Select the transfer clock polarity UFORM Select the LSB first or MSB first U0C1 TE Set this bit to 1 to enable transmit receive TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag U0IRS Se...

Page 289: ...interrupt request is acknowledged or set by a program Write dummy data to U0TB register Transfer from U0TB register to UART0 transmit register 1 fEXT D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 Receive data is taken in Read out from U0RB register Transfer from UART0 receive register to U0RB register TI bit in U0C1 register 1 0 1 0 1 0 1 0 TXEPT bit in U0C0 register IR bit in S0TIC register Set to 0 whe...

Page 290: ...rising edge of the transfer clock D1 D2 NOTES 1 When not transferring the CLK0 pin level is H 2 When not transferring the CLK0 pin level is L D3 D4 D5 D6 D7 D0 RXD0 D1 D2 D3 D4 D5 D6 D7 CLK0 2 D0 TXD0 D1 D2 D3 D4 D5 D6 D7 D0 RXD0 D1 D2 D3 D4 D5 D6 D7 When the CKPOL Bit in the U0C0 Register 1 output transmit data at the rising edge and input the receive data at the falling edge of the transfer cloc...

Page 291: ...Receive Mode Continuous receive mode is held by setting the U0RRM bit in the U0C1 register to 1 enables continuous receive mode In this mode reading U0RB register sets the TI bit in the U0C1 register to 0 data in the U0TB register When the U0RRM bit is set to 1 do not write dummy data to the U0TB register in a program ...

Page 292: ...g are required TE bit in UiC1 register is set to 1 transmit enabled TI bit in UiC1 register is set to 0 data in UiTB register Receive Start Conditions Before receive starts the following are required RE bit in UiC1 register is set to 1 receive enabled Detects start bit Interrupt Request Generation Timing When transmitting one of the following conditions can be selected UiIRS bit is set to 0 transm...

Page 293: ...e internal clock or external clock 3 STPS Select the stop bit PRY PRYE Select whether parity is included and odd or even UiC0 CLK0 CLK1 Select the count source for the UiBRG register TXEPT Transmit register empty flag NCH Select TXDi pin output mode CKPOL Set to 0 UFORM LSB first or MSB first can be selected when transfer data is 8 bit long Set to 0 when transfer data is 7 or 9 bit long UiC1 TE Se...

Page 294: ...rupt request is generated when transmit completes Start bit Parity bit Stop pulsing because the TE bit is set to 0 TXDi Write data to UiTB register Transfer from UiTB register to UARTi transmit register TI bit in UiC1 register 1 0 1 0 1 0 1 0 TXEPT bit in UiC0 register IR bit SiTIC register Stop bit Transmit timing when transfer data is 9 bits long parity disabled 2 stop bits 1 0 Stop bit Stop bit...

Page 295: ...disabled one stop bit The above timing diagram applies to the case where the register bits are set as follows UiMR register PRYE bit 0 parity disabled UiMR register STPS bit 0 1 stop bit i 0 or 1 UiC1 register RE bit Start bit Stop bit D0 D1 D7 RXDi Transfer clock Determined L Receive data taken in Reception triggered when transfer clock is generated by falling edge of start bit Transferred from U...

Page 296: ...2 0 16 2400 f8 64 40h 2403 85 0 16 25 19h 2403 85 0 16 4800 f8 32 20h 4734 85 1 36 12 0Ch 4807 69 0 16 9600 f1 129 81h 9615 38 0 16 51 33h 9615 38 0 16 14400 f1 86 56h 14367 82 0 22 34 22h 14285 71 0 79 19200 f1 64 40h 19230 77 0 16 25 19h 19230 77 0 16 28800 f1 42 2Ah 29069 77 0 94 16 10h 29411 76 2 12 31250 f1 39 27h 31250 00 0 00 15 0Fh 31250 00 0 00 38400 f1 32 20h 37878 79 1 36 12 0Ch 38461 5...

Page 297: ... bits in the UiRB register and the RI bit in the UiC1 register are set to 0 To check receive errors read the UiRB register and then use the read data Example when reading receive buffer register MOV W 00A6H R0 Read the U0RB register When writing data to the UiTB register in the clock asynchronous serial I O mode with 9 bit transfer data length write data high order byte first then low order byte i...

Page 298: ...ock output format and data output format 16 1 Mode Selection The clock synchronous serial interface contains 4 modes Table 16 1 lists the Mode Selections Refer to 16 2 Clock Synchronous Serial I O with Chip Select SSU or after for details of each mode Clock synchronous serial I O with chip select SSU Clock synchronous communication mode 4 wire bus communication mode I2C bus interface I2C bus inter...

Page 299: ... operates as slave device external clock can be selected When the MSS bit in the SSCRH register is set to 1 operates as master device internal clock selects from f1 256 f1 128 f1 64 f1 32 f1 16 f1 8 and f1 4 and outputs from SSCK pin can be selected Clock polarity and phase of SSCK can be selected Receive Error Detection Overrun error Overrun error occurs during receive and completes by error Whil...

Page 300: ...erial I O with Chip Select SSMR register Data bus Transmit receive control circuit SSCRL register SSCRH register SSER register SSSR register SSMR2 register SSTDR register SSRDR register Selector Multiplexer SSO SSI SCS SSCK Interrupt requests TXI TEI RXI OEI and CEI Internal clock generation circuit f1 Internal clock f1 i i 4 8 16 32 64 128 and 256 SSTRSR register ...

Page 301: ...le stop bit 3 0 Maintains receive operation after receiving 1 byte data 1 Completes receive operation after receiving 1 byte data RW b7 Nothing is assigned If necessary set to 0 When read the content is 0 The set clock is used w hen the internal clock is selected Master slave device select bit 2 0 Operates as slave device 1 Operates as master device RW MSS b4 b3 Nothing is assigned If necessary se...

Page 302: ...t is set to H When w rite 2 3 0 The data outputs L after the serial data output 1 The data outputs H after the serial data output RW b6 Nothing is assigned If necessary set to 0 When read the content is 1 b7 Nothing is assigned If necessary set to 0 When read the content is 0 b3 b2 Nothing is assigned If necessary set to 0 When read the content is 1 SOLP SOL w rite protect bit 2 The output level c...

Page 303: ...t odd edge CPOS SSCK clock polarity select bit 1 0 H w hen clock stops 1 L w hen clock stops b3 b4 CPHS SSCK clock phase select bit 1 RO BC1 BC2 Bit counter 2 to 0 b2 b1 b0 0 0 0 8 bit left 0 0 1 1 bit left 0 1 0 2 bit left 0 1 1 3 bit left 1 0 0 4 bit left 1 0 1 5 bit left 1 1 0 6 bit left 1 1 1 7 bit left BC0 RO RO Refer to 16 2 1 1 Association between Transfer Clock Polarity Phase and Data for ...

Page 304: ...s assigned If necessary set to 0 When read the content is 0 CEIE 0 Disables transmit data empty interrupt request 1 Enables transmit data empty interrupt request 0 Disables transmit end interrupt request 1 Enables transmit end interrupt request RW RE TE TEIE Transmit end interrupt enable bit RW RIE RW Receive enable bit 0 Disables receive 1 Enables receive Transmit enable bit 0 Disables transmit 1...

Page 305: ...nflict error occurs 1 Conflict error occurs 2 The TDREbit is set to 1 w hen setting the TEbit in the SSER register to 0 disables transmit The RDRF bit is set to 0 w hen reading out the data from the SSRDR register Overrun error flag 1 0 No overrun error occurs 1 Overrun error occurs 3 The TEND and TDRE bits are set to 0 w hen w riting the data to the SSTDR register TEND Transmit end 1 5 0 The TDRE...

Page 306: ...of data input and data output This bit functions as the SCS _____ input pin before starting transfer set to 0 clock synchronous communication mode The SSI pin and SSO pin corresponding port direction bits are set to 0 input mode w hen the SOOS bit is set to 0 CMOS output RW RW RW RW RW RW 0 Clock synchronous communication mode 1 Four w ire bus communication mode SSCK pin open drain output select b...

Page 307: ...ve Data Register Symbol Address After Reset SSRDR 00BFh FFh RW NOTE 1 The SSRDR register maintains the receive data before the overrun error occurs w hen the ORER bit in the SSSR register is set to 1 overrun error occurs When an overrun error occurs the receive data may contain errors and therefore should be discarded Store the receive data 1 The receive data is transferred to the SSRDR register a...

Page 308: ...cks of the transfer rate selected in the CKS0 to CKS2 bits in the SSCRH register When the MSS bit in the SSCRH register is set to 0 operates as slave device an external clock can be selected and the SSCK pin functions as input 16 2 1 1 Association between Transfer Clock Polarity Phase and Data Association between transfer clock polarity phase and data changes according to a combination of the SSUM...

Page 309: ... odd edge and CPOS bit 0 H when clock stops b1 b2 b3 b4 b5 b6 b7 SSCK CPOS 0 H when clock stops b0 SSO SSI When SSUMS bit 1 4 wire bus communication mode and CPHS bit 0 data change at odd edge b1 b2 b3 b4 b5 b6 b7 SSCK CPOS 1 L when clock stops SCS SSCK CPOS 0 H when clock stops SSO SSI When SSUMS bit 1 4 wire bus communication mode CPHS bit 1 data download at odd edge SSCK CPOS 1 L when clock sto...

Page 310: ...ociation between the data I O pin and SSTRSR register SS shift register changes according to a combination of the MSS bit in the SSCRH register and the SSUMS bit in the SSMR2 register Also connecting association changes according to the BIDE bit in the SSMR2 register Figure 16 11 shows an Association between Data I O Pins and SSTRSR Register Figure 16 11 Association between Data I O Pins and SSTRS...

Page 311: ... O with chip select interrupt request is generated Set the each interrupt source to 0 by a clock synchronous serial I O with chip select interrupt routine However the TDRE and TEND bits are automatically set to 0 by writing the transmit data to the SSTDR register and the RDRF bit is automatically set to 0 by reading the SSRDR register When writing the transmit data to the SSTDR register at the sam...

Page 312: ...o 1 in 4 wire bus bidirectional communication mode SSUMS and BIDE Bits in SSMR2 register MSS Bit in SSCRH register TE and RE Bits in SSER register Table 16 4 Association between Communication Modes and I O Pins Communication Mode Bit Setting Pin State SSUMS BIDE MSS TE RE SSI SSO SSCK Clock Synchronous Communication Mode 0 Disabled 0 0 1 Input 1 Input 1 0 1 Output Input 1 Input Output Input 1 0 1 ...

Page 313: ...de and format are changed set the TE bit to 0 and the RE bit to 0 before changing Setting the RE bit to 0 does not change the contents of the RDRF and ORER flags and the contents of the SSRDR register Figure 16 12 Initialization in Clock Synchronous Communication Mode Start SSMR2 register SSUMS bit 0 SSCRH register Set CKS0 to CKS2 bits Set RSSTP bit SSSR register ORER bit 0 1 SSER register RE bit...

Page 314: ...enerated When one frame of data is transferred while the TDRE bit is set to 0 data is transferred from the SSTDR to SSTRSR registers and a transmit of the next frame is started If the 8th bit is transmitted while the TDRE bit is set to 1 the TEND bit in the SSSR register is set to 1 the TDRE bit is set to 1 when the last bit of the transmit data is transmitted and the state is retained The TEI int...

Page 315: ... continued Read TEND bit in SSSR register TEND 1 No Yes Yes No No Yes SSER register TE bit 0 1 2 3 1 After reading the SSSR register and confirming that the TDRE bit is set to 1 write the transmit data to the SSTDR register When write the transmit data to the SSTDR register the TDRE bit is automatically set to 0 2 Determine whether data transmit is continued 3 When the data transmit is completed t...

Page 316: ...bit in the SSCRH register to 1 after receiving 1 byte data the receive operation is completed The clock synchronous serial I O with chip select outputs a clock for receiving 8 bit data and stops After that set the RE bit in the SSER register to 0 disables receive and the RSSTP bit to 0 receive operation is continued after receiving the 1 byte data and read the receive data If the SSRDR register is...

Page 317: ...curs perform an error 6 process after reading the ORER bit Then set the ORER bit to 0 Transmit receive can not be restarted while the ORER bit is set to 1 4 Confirm that the RDRF bit is set to 1 If the RDRF bit is set to 1 read the receive data in the SSRDR register If the SSRDR register is read the RDRF bit is automatically set to 0 ORER 1 End Read receive data in SSRDR register Read ORER bit in ...

Page 318: ...onfirming that the TEND bit is set to 0 the TDRE bit is set to 0 when the last bit of the transmit data is transmitted the RERF bit is set to 0 no data in the SSRDR register and the ORER bit is set to 0 no overrun error set the TE and RE bits to 1 Figure 16 17 shows a Sample Flowchart of Data Transmission Reception Clock Synchronous Communication Mode When exiting transmit receive mode after this ...

Page 319: ...the SSTDR register When writing the transmit data to the SSTDR register the TDRE bit is automatically set to 0 5 Set the TEND bit to 0 and 6 the RE and TE bits in the SSER register to 0 before ending transmit receive mode Read receive data in SSRDR register Read RDRF bit in SSSR register RDRF 1 No Yes 4 2 Confirm that the RDRF bit is set to 1 If the RDRF bit is set to 1 read the receive data in th...

Page 320: ...ock synchronous serial I O with chip select is set as a slave device the chip select line controls input When the clock synchronous serial I O with chip select is set as master device the chip select line controls output of the SCS pin or controls output of a general port by setting the CSS1 bit in the SSMR2 register When the clock synchronous serial I O with chip select is set as a slave device t...

Page 321: ...EIE and TIE End SSER register RE bit 0 TE bit 0 2 Set the BIDE bit to 1 in bidirectional mode and set the I O of the SCS pin by bits CSS0 and CSS1 1 1 The MLS bit is set to 0 for MSB first transfer The clock polarity and phase are set by bits CPHS and CPOS 2 NOTE 1 Write 0 after reading 1 to set the ORER bit to 0 SSMR2 register SCKS bit 1 Set bits SOOS CSS0 to CSS1 and BIDE SSCRH register Set MSS ...

Page 322: ...it is set to 0 the data is transferred from the SSTDR to SSTRSR registers and the next frame transmit is started If the 8th bit is transmitted while the TDRE is set to 1 the TEND in the SSSR register is set to 1 when the last bit of the transmit data is transmitted the TDRE bit is set to 1 and the state is retained If the TEIE bit in the SSER register is set to 1 enables transmit end interrupt req...

Page 323: ...ange at even edges CPOS bit 0 H when clock stops b7 SCS Output SSCK When CPHS bit 1 data change at even edges CPOS bit 0 H when clock stops CPHS CPOS Bits in SSMR register 1 frame TDRE bit in SSSR register 0 1 TEND bit in SSSR register 0 1 Data write to SSTDR register Process by program 1 frame High impedance b0 b7 High impedance SCS output TXI interrupt request is generated b7 b0 SSO 1 frame 1 fr...

Page 324: ...egister is read the RDRF bit is automatically set to 0 no data in the SSRDR register Read the receive data after setting the RSSTP bit in the SSCRH register to 1 after receiving 1 byte data the receive operation is completed The clock synchronous serial I O with chip select outputs a clock for receiving 8 bit data and stops After that set the RE bit in the SSER register to 0 disables receive and t...

Page 325: ... RDRF bit in SSSR register 0 1 RSSTP bit in SSCRH register 0 1 Dummy read in SSRDR register Process by program 1 frame High impedance b0 b7 High impedance SCS Output b7 b0 Data read in SSRDR register RXI interrupt request is generated RXI interrupt request is generated Data read in SSRDR register RXI interrupt request is generated b0 b7 b0 b7 b7 b0 SSI 1 frame RDRF bit in SSSR register 0 1 RSSTP b...

Page 326: ...ial I O with chip select detects that the synchronized internal SCS signal is held L in this period the CE bit in the SSSR register to 1 a conflict error occurs and the MSS bit is automatically set to 0 operates as a slave device Figure 16 21 shows an Arbitration Check Timing A future transmit operation is not performed while the CE bit is set to 1 Set the CE bit to 0 a conflict error does not occ...

Page 327: ...00 Aug 27 2008 Page 311 of 458 REJ09B0250 0200 16 2 8 Notes on Clock Synchronous Serial I O with Chip Select Set the IICSEL bit in the PMR register to 0 select clock synchronous serial I O with chip select function to use the clock synchronous serial I O with chip select ...

Page 328: ...s not possible yet stand by to set the SCL signal to L Direct drive of the SCL and SDA pins N channel open drain output is enabled Clock synchronous serial format Continuous transmit receive since the shift register transmit data register and receive data register are independent I O Pins SCL I O Serial clock I O pin SDA I O Serial data I O pin Transfer Clocks When the MST bit in the ICCR1 registe...

Page 329: ...CMR register ICDRT register SAR register ICSR register Address comparison circuit Output control SCL Interrupt request TXI TEI RXI STPI NAKI Transfer clock generation circuit ICDRS register ICDRR register Bus state judgment circuit Arbitration judgment circuit ICIER register Interrupt generation circuit Transmit receive control circuit Noise rejection circuit SDA Output control f1 Noise rejection ...

Page 330: ...age 314 of 458 REJ09B0250 0200 Figure 16 23 External Circuit Connection Example of Pins SCL and SDA SCL SDA SCL input SCL output SDA input SDA output Master VCC VCC SCL SDA SCL input SCL output SDA input SDA output Slave 1 SCL SDA SCL input SCL output SDA input SDA output SCL SDA Slave 2 ...

Page 331: ... 0 0 0 0 f1 28 0 0 0 1 f1 40 0 0 1 0 f1 48 0 0 1 1 f1 64 0 1 0 0 f1 80 0 1 0 1 f1 100 0 1 1 0 f1 112 0 1 1 1 f1 128 1 0 0 0 f1 56 1 0 0 1 f1 80 1 0 1 0 f1 96 1 0 1 1 f1 128 1 1 0 0 f1 160 1 1 0 1 f1 200 1 1 1 0 f1 224 1 1 1 1 f1 256 b5 b4 0 0 Slave receive mode 4 0 1 Slave transmit mode 1 0 Master receive mode 1 1 Master transmit mode RW MST RW RW Transfer receive select bit 2 3 6 In multimaster o...

Page 332: ...en w rite 1 2 0 SDA pin output is changed to L 1 SDA pin output is changed to high impedance H output is external pull up resistor SDA output value control bit SDAO w rite protect bit When rew rite to SDAO bit w rite 0 simultaneously 1 When read its content is 1 BBSY Bus busy bit 4 SCP Start stop condition generation disable bit When w rite to BBSY bit w rite 0 simultaneously 3 When read its conte...

Page 333: ... to BC2 bits w rite 0 simultaneously 2 4 When read its content is 1 RW The setting value is enabled in master mode of the I2 C bus format It is disabled in slave mode of the I2 C bus format or w hen the clock synchronous serial format is used 0 No w ait Transfer data and acknow ledge bit consecutively 1 Wait After the falling of the clock for the final data bit L period is extended for tw o transf...

Page 334: ...eceive data full and overrun error interrupt request 1 Enables receive data full and overrun error interrupt request 1 RW TIE Transmit interrupt enable bit 0 Disables transmit data empty interrupt request 1 Enables transmit data empty interrupt request TEIE Set the STIE bit to 1 enable stop condition detection interrupt request w hen the STOPbit in the ICSR register is set to 0 0 Disables transmit...

Page 335: ...END Transmit end 1 6 RW RW General call address recognition flag 1 2 When detecting the general call address this flag is set to 1 Arbitration lost flag overrun error flag 1 When the I2 C bus format is used this flag indicates that arbitration is lost in master mode In the follow ing case this flag is set to 1 3 When the internal SDA signal and SDA pin level do not match at the rise of the SCL sig...

Page 336: ...s a slave device RW RW RW RW SVA3 SVA6 SVA5 SVA4 RW RW FS Format select bit 0 I2 C bus format 1 Clock synchronous serial format RW SVA2 SVA0 SVA1 b7 b6 b0 b1 b5 b3 b2 b4 IIC Bus Transmit Data Register Symbol Address After Reset ICDRT 00BEh FFh RW RW Function Store transmit data When detecting that the ICDRS register is empty the stored transmit data is transferred to the ICDRS register and the sta...

Page 337: ...RS RW b7 b0 This register is a register that is used to transmit and receive data The transmit data is transferred from the ICDRT to ICDRS registers and data is transmitted from the SDA pin w hen transmitting When 1 byte data is received data is transferred from the ICDRS to ICDRR registers w hen receiving Function Port Mode Register Symbol Address After Reset PMR 00F8h 00h Bit Symbol Bit Name Fun...

Page 338: ...Hz 0 0 0 0 f1 28 179 kHz 286 kHz 357 kHz 571 kHz 714 kHz 1 f1 40 125 kHz 200 kHz 250 kHz 400 kHz 500 kHz 1 0 f1 48 104 kHz 167 kHz 208 kHz 333 kHz 417 kHz 1 f1 64 78 1 kHz 125 kHz 156 kHz 250 kHz 313 kHz 1 0 0 f1 80 62 5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 1 f1 100 50 0 kHz 80 0 kHz 100 kHz 160 kHz 200 kHz 1 0 f1 112 44 6 kHz 71 4 kHz 89 3 kHz 143 kHz 179 kHz 1 f1 128 39 1 kHz 62 5 kHz 78 1 kHz 12...

Page 339: ...However the TDRE and TEND bits are automatically set to 0 by writing transmit data to the ICDRT register and the RDRF bit is automatically set to 0 by reading the ICDRR register When writing transmit data to the ICDRT register the TDRE bit is set to 0 When data is transferred from the ICDRT to ICDRS registers the TDRE bit is set to 1 and when further setting the TDRE bit to 0 extra 1 byte may be t...

Page 340: ... signal is held H SLA Slave address R W Indicates the direction of data transmit receive Data is transmitted from the slave device to the master device when R W value is 1 and from the master device to the slave device when R W value is 0 A Acknowledge The receive device sets the SDA signal to L DATA Transmit receive data P Stop condition The master device changes the SDA signal from L to H while ...

Page 341: ...W are shown at the 1st byte At this time the TDRE bit is automatically set to 0 and data is transferred from the ICDRT to ICDRS registers the TDRE bit is set to 1 again 4 When the transmit of 1 byte data is completed while the TDRE bit is set to 1 the TEND bit in the ICSR register is set to 1 at the rise of the 9th transmit clock pulse Read the ACKBR bit in the ICIER register and confirm that the ...

Page 342: ...register 1 0 ICDRT register ICDRS register R W Slave address Address R W Processing by program 2 Instruction of start condition generation 3 Data write to ICDRT register 1st byte A 4 Data write to ICDRT register 2nd byte 5 Data write to ICDRT register 3rd byte Data 2 Address R W Data 1 Data 1 SDA master output SCL master output 1 2 8 9 6 7 4 5 3 b7 b6 b5 b4 b3 b2 b1 b0 SDA slave output TDRE bit in...

Page 343: ...register to the SDA pin at the 9th clock of the receive clock 3 The 1 frame data receive is completed and the RDRF bit in the ICSR register is set to 1 at the rise of the 9th clock At this time when reading the ICDRR register the received data can be read and the RDRF bit is set to 0 simultaneously 4 The continuous receive is enabled by reading the ICDRR register every time the RDRF bit is set to ...

Page 344: ...CL master output 1 8 9 6 7 4 5 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 1 2 SDA slave output TDRE bit in ICSR register 1 0 TEND bit in ICSR register 1 0 ICDRR register ICDRS register Data 1 Processing by program 1 Set TEND and TRS bits to 0 before setting TDRE bits to 0 A 2 Read ICDRR register Data 1 9 TRS bit in ICCR1 register 1 0 RDRF bit in ICSR register 1 0 A 3 Read ICDRR register Master transmit mode Mas...

Page 345: ...master output SCL master output 1 2 8 9 6 7 4 5 3 b7 b6 b5 b4 b3 b2 b1 b0 SDA slave output 1 0 RCVD bit in ICCR1 register 1 0 ICDRR register ICDRS register Data n 1 Processing by program 6 Stop condition generation A A 8 Set to slave receive mode 9 A Data n RDRF bit in ICSR register Data n Data n 1 5 Set RCVD bit to 1 before reading ICDRR register 7 Read ICDRR register before setting RCVD bit to 0...

Page 346: ...ve address matches in slave receive mode 2 When the slave address matches at the 1st frame after detecting the start condition the slave device outputs the level set by the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock At this time if the 8 bit data R W is set to 1 the TRS and TDRE bit in the ICSR register are set to 1 the mode is switched to slave transmit mode autom...

Page 347: ...t 1 8 9 6 7 4 5 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 1 2 SDA slave output TDRE bit in ICSR register 1 0 TEND bit in ICSR register 1 0 ICDRR register ICDRS register Data 1 Process by program A Data 2 9 TRS bit in ICCR1 register 1 0 A Slave transmit mode Slave receive mode SCL slave output ICDRT register Data 1 1 Data write to ICDRT register data 1 2 Data write to ICDRT register data 2 Data 2 2 Data write t...

Page 348: ...t SCL master output 1 2 8 9 6 7 4 5 3 b7 b6 b5 b4 b3 b2 b1 b0 SDA master output TDRE bit in ICSR register 1 0 TEND bit in ICSR register 1 0 ICDRT register ICDRS register Data n Process by program 3 Set the TEND bit to 0 A 9 A Data n Slave receive mode Slave transmit mode TRS bit in ICCR1 register 1 0 ICDRR register 4 Dummy read of ICDRR register after setting TRS bit to 0 5 Set TDRE bit to 0 SCL s...

Page 349: ... in the ICCR1 register to 0 and wait until the slave address matches in slave receive mode 2 When the slave address matches at the 1st frame after detecting the start condition the slave device outputs the level set in the ACKBT bit in the ICIER register to the SDA pin at the rise of the 9th clock Since the RDRF bit in the ICSR register is set to 1 simultaneously perform the dummy read the read da...

Page 350: ... 7 4 5 3 b7 b6 b5 b4 b3 b2 b1 b0 b7 1 2 SDA slave output ICDRR register ICDRS register Data 1 Process by program A 2 Dummy read of ICDRR register Data 1 9 RDRF bit in ICSR register 1 0 A 2 Read ICDRR register SCL slave output Data 2 SDA master output SCL master output 8 9 6 7 4 5 3 b7 b6 b5 b4 b3 b2 b1 b0 1 2 SDA slave output ICDRR register ICDRS register Data 1 Process by program A 3 Read ICDRR r...

Page 351: ...n the ICCR1 register is set to 1 the transfer clock is output from the SCL pin and when the MST bit is set to 0 the external clock is input The transfer data is output between the fall and the following fall of the SCL clock and data is determined by the rise of the SCL clock The MSB first or LSB first can be selected for the order of the data transfer by setting the MLS bit in the ICMR register T...

Page 352: ...r is set to 1 by selecting transmit mode after setting the TRS bit in the ICCR1 register to 1 3 Data is transferred from the ICDRT to ICDRS registers and the TDRE bit is automatically set to 1 by writing transmit data to the ICDRT register after confirming that the TDRE bit is set to 1 When writing data to the ICDRT register every time the TDRE bit is set to 1 the continuous transmit is enabled Wh...

Page 353: ...when the receive is completed Since the following byte data is enabled to receive when the MST bit is set to 1 the continuous clock is output The continuous receive is enabled by reading the ICDRR register every time the RDRF bit is set to 1 An overrun is detected at the rise of the 8th clock while the RDRF bit is set to 1 the AL bit in the ICSR register is set to 1 At this time the former receive...

Page 354: ... Noise Canceller The noise rejection circuit consists of two cascaded latch and match detector circuits When the SCL pin input signal or SDA pin input signal is sampled on f1 and 2 latch outputs match the level is passed forward to the next circuit When they do not match the former value is retained Figure 16 44 Block Diagram of Noise Canceller C D Q Latch C D Q Latch Match detection circuit SCL o...

Page 355: ...ad capacity and pull up resistor of the SCL line the SCL signal is monitored and the communication synchronizes per bit Figure 16 45 shows the Timing of Bit Synchronous Circuit and Table 16 8 lists the Time between Changing SCL Signal from L Output to High Impedance and Monitoring of SCL Signal Figure 16 45 Timing of Bit Synchronous Circuit 1 Tcyc 1 f1 s Table 16 8 Time between Changing SCL Signal...

Page 356: ... 2nd byte except the last byte 8 Wait the ICDRT register is empty 9 Set the transmit data of the last byte 10 Wait for the transmit end of the last byte 11 Set the TEND bit to 0 12 Set the STOP bit to 0 13 Generate the stop condition 14 Wait the stop condition is generated 15 Set to slave receive mode Set the TDRE bit to 0 ICCR1 register TRS bit 1 MST bit 1 ICCR2 register SCP bit 0 BBSY bit 1 Read...

Page 357: ...top condition 12 Wait the stop condition is generated 13 Read the receive data of the last byte 14 Set the RCVD bit to 0 15 Set to slave receive mode ICCR1 register TRS bit 0 Dummy read in ICDRR register Read RDRF bit in ICSR register Last receive 1 ICSR register TEND bit 0 ICSR register STOP bit 0 ICCR2 register SCP bit 0 BBSY bit 0 Read STOP bit in ICSR register STOP 1 ICSR register TDRE bit 0 N...

Page 358: ...byte 3 Wait the ICDRT register is empty 4 Set the transmit data of the last byte 5 Wait the last byte is transmitted 6 Set the TEND bit to 0 7 Set to slave receive mode 8 Dummy read in the ICDRR register to release the SCL signal 9 Set the TDRE bit to 0 TDRE 1 Read TDRE bit in ICSR register Last byte Write transmit data to ICDRT register TEND 1 Read TEND bit in ICSR register ICSR register TEND bit...

Page 359: ...ad the receive data 7 Set the ACKBT bit of the last byte 1 8 Read the receive data of last byte 1 9 Wait the last byte is received 10 Read the receive data of the last byte Dummy read in ICDRR register Read RDRF bit in ICSR register Last receive 1 1 2 3 4 5 6 7 8 10 9 ICIER register ACKBT bit 0 No Yes Read ICDRR register ICIER register ACKBT bit 1 Read ICDRR register Read RDRF bit in ICSR register...

Page 360: ... rate in this MCU should be set to 223 kbps 400 1 18 or more Bits MST and TRS in the ICCR1 register setting a Use the MOV instruction to set bits MST and TRS b When arbitration is lost confirm the contents of bits MST and TRS If the contents are other than the MST bit set to 0 and the TRS bit set to 0 slave receive mode set the MST bit to 0 and the TRS bit to 0 again 16 3 8 2 Master Receive Mode E...

Page 361: ...Break and Synch Field signal inputs to UART0 Detects bus collision NOTE 1 The WakeUp function is detected by INT1 Figure 17 1 Block Diagram of Hardware LIN Timer RA UART0 Interrupt control circuit Bus collision detection circuit Synch Field control circuit RXD0 pin TXD0 pin LSTART bit SBE bit LINE bit Timer RA interrupt TIOSEL 0 Hardware LIN TIOSEL 1 RXD data Timer RA underflow signal BCIE SBIE an...

Page 362: ... 2 Input Output Pins Table 17 1 lists the Pin Configuration of the hardware LIN Table 17 1 Pin Configuration Name Abbreviation Input Output Function Receive Data Input RXD0 Input Receive data input pin of the hardware LIN Transmit Data Output TXD0 Output Transmit data output pin of the hardware LIN ...

Page 363: ...ent is completed Synch Break detection interrupt enable bit 0 Disables bus collision detection interrupt 1 Enables bus collision detection interrupt 0 RXD0 input enabled 1 RXD0 input disabled When this bit is set to 1 Timer RA input is enabled and RXD0 input is disabled When read its content is 0 RxD0 input status flag Synch Break detection start bit 1 SFIE 0 Disables Synch Break detection interru...

Page 364: ...CT bit is set to0 When read its content is 0 Synch Break detection flag Bus collision detection flag SFDCT flag clear bit RO SBDCT flag clear bit BCDCT flag clear bit 1 show s Synch Break detected or Synch Break generation completed 1 show s Bus collision detected When this bit is set to 1 SFDCT bit is set to 0 When read its content is 0 When this bit is set to 1 SBDCT bit is set to 0 When read it...

Page 365: ... the hardware LIN reverses the output of the TXD0 pin and sets the SBDCT flag in the LINST register to 1 Furthermore if the SBIE bit in the LINCR register is set to 1 it generates a timer RA interrupt 3 The hardware LIN transmits 55h via UART0 4 The hardware LIN transmits an ID field via UART0 after it finished sending 55h 5 The hardware LIN performs communication for a response field after it fin...

Page 366: ...interrupts Bus collision detection Synch Break detection Synch Field measurement BCIE SBIE SFIE bits in LINCR register Hardware LIN Clear the status flags Bus collision detection Synch Break detection Synch Field measurement B2CLR B1CLR B0CLR bits in LINST register 1 Set the count source and the TRA and TRAPRE registers as suitable for the Synch Break period During master mode the Synch Field meas...

Page 367: ...egister ID field NO YES NO NO If the TRAPRE and TRA registers for timer RA do not need to be read or the register settings do not need to be changed after writing 0 to the TSTART bit the procedure for reading TCSTF flag 0 can be omitted Zero to one cycle of the timer RA count source is required after timer RA stops counting before the TCSTF flag is set to 0 Transmit the Synch Field After timer RA ...

Page 368: ...the SFDCT flag in the LINST register to 1 when it finished measuring the Synch Field Furthermore if the SFIE bit in the LINCR register is set to 1 it generates a timer RA interrupt 5 After it finished measuring the Synch Field the hardware LIN calculates a transfer rate from the count value of timer RA and sets the result in UART0 and sets the TRAPRE and TRA registers of the timer RA back again Th...

Page 369: ... slave mode MST bit in the LINCR register 0 Hardware LIN Set the LIN operation to start LINE bit in the LINCR register 1 Hardware LIN Set the RXD0 input unmasking timing After Synch Break detection or after Synch Field measurement SBE bit in the LINCR register Hardware LIN Set the register to enable interrupts Bus collision detection Synch Break detection Synch Field measurement Bits BCIE SBIE SFI...

Page 370: ...th the initially set count value Even if the duration of the input L level is shorter than the set period timer RA is reloaded with the initially set count value and waits until the next L level is input One to two cycles of the CPU clock are required after Synch Break detection before the SBDCT flag is set to 1 When the SBE bit in the LINCR register is set to 0 Unmasked after Synch Break is detec...

Page 371: ...B SFDCT 1 YES UART0 Communication via UART0 Clock asynchronous serial interface UART mode Receive ID field NO Hardware LIN measure the Synch Field The interrupt of timer RA may be used The SBDCT flag is set when the timer RA counter underflows upon reaching the terminal count When the SBE bit in the LINCR register is set to 1 Unmasked after Synch Field measurement is completed timer RA may be used...

Page 372: ...hows a Typical Operation when a Bus Collision is Detected Figure 17 11 Typical Operation when a Bus Collision is Detected TXD0 pin 1 0 RXD0 pin 1 0 Transfer clock 1 0 LINE bit in the LINCR register 1 0 TE bit in the U0C1 register 1 0 BCDCT flag in the LINST register 1 0 IR bit in the TRAIC register 1 0 Cleared to 0 upon acceptance of interrupt request or by a program Set by writing 1 to the B2CLR ...

Page 373: ...n Completion Flowchart Hardware LIN Clear the status flags Bus collision detection Synch Break detection Synch Field measurement Bits B2CLR B1CLR B0CLR in the LINST register 1 Timer RA Read the count status flag TCSTF flag in TRACR register UART0 Complete transmission via UART0 When the bus collision detection function is not used end processing for the UART0 transmission is not required TCSTF 0 Y...

Page 374: ...errupt Request Status Flag Cause of Interrupt Synch Break Detection SBDCT Generated when timer RA has underflowed after measuring the low level duration of RXD0 input or when a low level signal is input for a duration longer than the Synch Break period during communication Synch Break Generation Completed Generated when timer RA has completed outputting a low level signal to TXD0 for set period Sy...

Page 375: ...ug 27 2008 Page 359 of 458 REJ09B0250 0200 17 6 Notes on Hardware LIN For the time out processing of the header and response fields use another timer to measure the duration of time with respect to a Synch Break detection interrupt as the starting point ...

Page 376: ...0 bit mode FFh in 8 bit mode 2 The frequency of φAD must be 10 MHz or below Without sample and hold function the φAD frequency should be 250 kHz or above With the sample and hold function the φAD frequency should be 1 MHz or above 3 In repeat mode only 8 bit mode can be used Table 18 1 Performance of A D Converter Item Performance A D Conversion Method Successive approximation with capacitive coup...

Page 377: ...1_2 AN10 CH2 to CH0 110b P1_3 AN11 CH2 to CH0 111b ADGSEL0 1 CH0 to CH2 ADGSEL CKS0 Bits in ADCON0 register CKS1 VCUT Bits in ADCON1 register A D conversion rate selection ADGSEL0 0 ADCAP 1 Software trigger Timer RD interrupt request ADCAP 0 Trigger P0_7 AN0 CH2 to CH0 000b P0_6 AN1 CH2 to CH0 001b P0_5 AN2 CH2 to CH0 010b P0_4 AN3 CH2 to CH0 011b P0_3 AN4 CH2 to CH0 100b P0_2 AN5 CH2 to CH0 101b ...

Page 378: ...CKS1 in ADCON1 register 0 0 Select f4 1 Select f2 When CKS1 in ADCON1 register 1 0 Select f1 3 1 Select fOCO F RW If the ADCON0 register is rew ritten during A D conversion the conversion result is indeterminate When changing A D operation mode set the analog input pin again ADST A D conversion start flag 0 Disables A D conversion 1 Starts A D conversion RW ADCAP A D conversion automatic start bit...

Page 379: ...de select bit 2 0 8 bit mode 1 10 bit mode RW Set to 0 Frequency select bit 1 BITS RW A D Control Register 2 1 Symbol Address After Reset ADCON2 00D4h 00h Bit Symbol Bit Name Function RW NOTE 1 b0 0 0 0 b3 b2 b1 Reserved bit Set to 0 b7 b6 b5 b4 0 Without sample and hold 1 With sample and hold RW If the ADCON2 register is rew ritten during A D conversion the conversion result is indeterminate SMP ...

Page 380: ...selected pin by bits CH2 to CH0 and ADGSEL0 is A D converted once Start Condition When the ADCAP bit is set to 0 software trigger Set the ADST bit to 1 A D conversion starts When the ADCAP bit is set to 1 starts in timer RD complementary PWM mode The compare match in the TRD0 and TRDGRA0 registers or the TRD1 underflow is generated while the ADST bit is set to 1 Stop Condition A D conversion compl...

Page 381: ...t bit 4 0 Selects port P0 group AN0 to AN7 1 Selects port P1 group AN8 to AN11 CH1 RW CH0 ADCAP A D conversion automatic start bit 0 Starts in softw are trigger ADST bit 1 Starts in timer RD complementary PWM mode RW ADST A D conversion start flag 0 Disables A D conversion 1 Starts A D conversion RW Set øAD frequency to 10 MHz or below The analog input pin can be select according to a combination ...

Page 382: ...onnected from 0 not connected w ait for 1 µs or more before starting A D conversion b3 b2 VCUT b1 b0 0 0 Refer to a description of the CKS0 bit in the ADCON0 register function b7 b6 b5 b4 b2 b0 0 0 1 0 BITS RW If the ADCON1 register is rew ritten during A D conversion the conversion result is indeterminate CKS1 RW RW RW b7 b6 Reserved bit Vref connect bit 2 RW Set to 0 Frequency select bit 1 1 Vre...

Page 383: ...Specification Function The Input voltage on one pin selected by CH2 to CH0 and ADGSEL0 bits is A D converted repeatedly Start Condition When the ADCAP bit is set to 0 software trigger Set the ADST bit to 1 A D conversion starts When the ADCAP bit is set to 1 starts in timer RD complementary PWM mode The compare match in the TRD0 and TRDGRA0 registers or the TRD1 underflow is generated while the AD...

Page 384: ...ect bit 0 When CKS1 in ADCON1 register 0 0 Select f4 1 Select f2 When CKS1 in ADCON1 register 1 0 Select f1 3 1 Do not set RW If the ADCON0 register is rew ritten during A D conversion the conversion result is indeterminate When changing A D operation mode set the analog input pin again ADST A D conversion start flag 0 Disables A D conversion 1 Starts A D conversion RW ADCAP A D conversion automat...

Page 385: ... connected w ait for 1 µs or more before starting A D conversion b3 b2 VCUT b1 b0 0 0 0 Refer to a description of the CKS0 bit in the ADCON0 register function b7 b6 b5 b4 b2 b0 0 0 1 0 BITS RW If the ADCON1 register is rew ritten during A D conversion the conversion result is indeterminate CKS1 RW RW RW b7 b6 Reserved bit Set the BITS bit to 0 8 bit mode in repeat mode Vref connect bit 3 1 Vref co...

Page 386: ... sample and hold circuit is to be used or not Figure 18 8 shows the Timing Diagram of A D Conversion Figure 18 8 Timing Diagram of A D Conversion Sampling time 4ø AD cycle Sample hold disabled Conversion time at the 1st bit at the 2nd bit Comparison time Sampling time 2 5ø AD cycle Comparison time Sampling time 2 5ø AD cycle Comparison time Repeat until conversion ends Sampling time 4ø AD cycle Sa...

Page 387: ... Sample Hold Without Sample Hold With Sample Hold With Sample Hold 8 bits 10 bits 8 bits 10 bits Conversion Time Comparison Time Comparison Time End process Sampling Time End process Conversion time at the 1st bit Sampling Time Conversion time at the 2nd bit and the follows 49φAD 4φAD 2 0φAD 2 5φAD 2 5φAD 8 0φAD 59φAD 4φAD 2 0φAD 2 5φAD 2 5φAD 8 0φAD 28φAD 4φAD 2 5φAD 0 0φAD 2 5φAD 4 0φAD 33φAD 4φ...

Page 388: ... Wiring Resistor Approx 0 2kΩ i Ladder type Switches A D Control Register 0 ON Resistor Approx 0 6k f Analog Input Voltage Sampling Control Signal ON Resistor Approx 5kΩ C Approx 1 5pF A D Conversion Interrupt Request SW1 conducts only on the ports selected for analog input SW2 and SW3 are open when A D conversion is not in progress their status varies as shown by the waveforms in the diagrams on ...

Page 389: ...N 0 1 1024 VIN in time T 0 1 1024 means that A D precision drop due to insufficient capacitor charge is held to 0 1LSB at time of A D conversion in the 10 bit mode Actual error however is the value of absolute precision added to 0 1LSB When f XIN 10 MHz T 0 25 µs in the A D conversion mode without sample hold Output impedance R0 for sufficiently charging capacitor C within time T is determined as ...

Page 390: ...in the ADIC register or the ADST bit in the ADCON0 register can determine whether the A D conversion is completed When using the repeat mode select the frequency of the A D converter operating clock φAD or more for the CPU clock during A D conversion Do not select the fOCO F for the φAD If setting the ADST bit in the ADCON0 register to 0 A D conversion stops by a program and the A D conversion is ...

Page 391: ...hat all blank areas are used before performing an erase operation Avoid rewriting only particular blocks and try to average out the programming and erasure endurance of the blocks It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number 2 Blocks A and B are embedded only in the R8C 21 Group Table 19 1 Flash Memory Perfo...

Page 392: ...s rewritten by executing software commands from the CPU EW0 mode Rewritable in the RAM EW1 mode Rewritable in flash memory User ROM area is rewritten by using a dedicated serial programmer User ROM area is rewritten by using a dedicated parallel programmer Areas which can be rewritten User ROM area User ROM area User ROM area Operating mode Single chip mode Boot mode Parallel I O mode ROM programm...

Page 393: ...ral blocks The user ROM area can be rewritten in CPU rewrite and standard serial I O and parallel I O modes When rewriting the block 0 and block 1 in CPU rewrite mode set the FMR02 bit in the FMR0 register to 1 rewrite enables and when setting the FMR15 bit in the FMR1 register to 0 rewrite enables block 0 is rewritable When setting the FMR16 bit to 0 rewrite enables block 1 is rewritable When rew...

Page 394: ...1 0C000h 48 Kbytes ROM product 0FFFFh 0BFFFh 04000h Block 1 32 Kbytes 1 User ROM area Block 0 16 Kbytes 1 0C000h 32 Kbytes ROM product 0FFFFh 0BFFFh 08000h Block 1 16 Kbytes 1 Program ROM Boot ROM area reserved area 4 8 Kbytes 0E000h 0FFFFh NOTES 1 When setting the FMR02 bit in the FMR0 register to 1 enables to rewrite and the FMR15 bit in the FMR1 register to 0 enable to rewrite Block 0 is rewrit...

Page 395: ...Kbytes ROM product 0FFFFh 0BFFFh 08000h Block 1 16 Kbytes 1 Program ROM Boot ROM area reserved area 4 8 Kbytes 0E000h 0FFFFh Block B 1 Kbyte Block A 1 Kbyte 02400h 02BFFh Block B 1 Kbyte Block A 1 Kbyte 02400h 02BFFh Block B 1 Kbyte Block A 1 Kbyte 02400h 02BFFh Block B 1 Kbyte Block A 1 Kbyte 02400h 02BFFh Block B 1 Kbyte Block A 1 Kbyte 02400h 02BFFh NOTES 1 When setting the FMR02 bit in the FMR...

Page 396: ...cknowledged The ID code consists of 8 bit data the areas of which beginning with the first byte are 00FFDFh 00FFE3h 00FFEBh 00FFEFh 00FFF3h 00FFF7h and 00FFFBh Write a program in which the ID codes are set at these addresses and write them in the flash memory Figure 19 3 Address for Stored ID Code 4 bytes Address 00FFDFh to 00FFDCh Undefinedinstruction vector NOTE 1 The OFS register is assigned to...

Page 397: ...eserved bit NOTES 1 2 3 b7 b6 b5 b4 b3 b2 b1 b0 1 1 1 b1 Set to 1 RW WDTON Watchdog timer start select bit 0 Starts w atchdog timer automatically after reset 1 Watchdog timer is inactive after reset RW ROMCR ROM code protect disabled bit 0 ROM code protect disabled 1 ROMCP1 enabled RW ROMCP1 ROM code protect bit 0 ROM code protect enabled 1 ROM code protect disabled RW RW b5 b4 Reserved bits Set t...

Page 398: ...ode Single chip mode Areas in which a Rewrite Control Program Can be Located User ROM area User ROM area Areas in which a Rewrite Control Program can be Executed Necessary to transfer to any areas other than the flash memory e g RAM before executing Executing directly in user ROM or RAM area possible Areas which can be Rewritten User ROM area User ROM area However other than the blocks which conta...

Page 399: ...t to 1 CPU rewrite mode enabled The FMR0 register can determine status when program and erase operation complete Do not execute commands of the read status register in EW1 mode To enable the erase suspend function during the auto erase execute the block erase command after setting the FMR40 bit to 1 enables suspend The interrupt to enter an erase suspend should be in interrupt enabled status After...

Page 400: ...ed on chip oscillator mode low speed on chip oscillator mode XIN clock stop Figure 19 11 shows a Process to Reduce Power Consumption in High Speed On Chip Oscillator Mode Low Speed On Chip Oscillator Mode XIN Clock Stops and Low Speed Clock Mode XIN Clock Stops Note that when going to stop or wait mode while the CPU rewrite mode is disabled the FMR0 register does not need to be set because the pow...

Page 401: ...t to 0 program restarts when the auto program operation restarts 19 4 2 13 FMR43 Bit When the auto erase operation starts the FMR43 bit is set to 1 during erase execution The FMR43 bit remains 1 during erase execution during erase suspend operation When the auto erase operation ends the FMR43 bit is set to 0 erase not executed 19 4 2 14 FMR44 Bit When the auto program starts the FMR44 bit is set t...

Page 402: ...isabled 1 CPU rew rite mode enabled When setting the FMR01 bit to 0 CPU rew rite mode disabled the FMR02 bit is set to 0 disables rew rite This bit is set to 0 by executing the clear status command This bit is enabled w hen the FMR01 bit is set to 1 CPU rew rite mode enabled When the FMR01 bit is set to 0 and w riting 1 to the FMSTP bit the FMSTP bit is set to 1 The flash memory does not enter low...

Page 403: ...e 1 Disables rew rite When the FMR01 bit is set to 1 CPU rew rite mode enabled the FMR15 and FMR16 bits can be w ritten When setting this bit to 0 set to 0 immediately after setting it first to 1 When setting this bit to 1 set it to 1 b7 0 RW RW RW RO RW Reserved bit 0 Enables rew rite 1 Disables rew rite FMR16 Block 1 rew rite disable bit 2 3 When setting this bit to 1 set to 1 immediately after ...

Page 404: ...le bit 1 0 Disables reading 1 Enables reading Reserved bit 0 Disable 1 Enable Erase suspend request bit 2 0 Erase restart 1 Erase suspend request RO RO RW FMR43 Erase command flag 0 Erase not executed 1 During erase execution RO 0 Disable 1 Enable FMR46 Program suspend request bit 3 0 Program restart 1 Program suspend request Set the FMR01 bit in the FMR0 register to 0 CPU rew rite mode disabled i...

Page 405: ... bit in FMR4 register FMR43 bit in FMR4 register 1 0 1 0 1 0 1 0 Check that the FMR43 bit is set to 1 during erase execution and that the erase operation has not ended Check that the FMR44 bit is set to 1 during program execution and that the program has not ended Check the status and that the program ends normally Check the status and that the erase operation ends normally Remains 0 during suspen...

Page 406: ...e CM1 register 2 When setting the FMR01 bit to 1 write 0 to the FMR01 bit before writing 1 Do not generate an interrupt between writing 0 and 1 Write to the FMR01 bit in the RAM 3 Disable the CPU rewrite mode after executing the read array command EW0 Mode Operating Procedure Transfer a rewrite control program which uses CPU rewrite mode to the RAM Jump to the rewrite control program which has bee...

Page 407: ...urce for the CPU clock Turn XIN off Process in high speed on chip oscillator mode low speed on chip oscillator mode XIN clock stops Write 0 to the FMR01 bit CPU rewrite mode disabled Jump to a specified address in the flash memory High speed on chip oscillator mode low speed on chip oscillator mode XIN clock stops program NOTES 1 Set the FMR01 bit to 1 CPU rewrite mode enabled before setting the F...

Page 408: ...e addresses can be read continuously In addition the MCU enters read array mode after a reset 19 4 3 2 Read Status Register Command The read status register command reads the status register If writing 70h in the first bus cycle the status register can be read in the second bus cycle Refer to 19 4 4 Status Registers When reading the status register specify an address in the user ROM area Do not ex...

Page 409: ...ommands targeting block 0 to 3 are not acknowledged When the FMR02 bit is set to 1 rewrite enables and the FMR15 bit in the FMR1 register is set to 1 disable rewriting program commands targeting block 0 are not acknowledged When the FMR16 bit is set to 1 disable rewriting program commands targeting block 1 are not acknowledged Figure 19 12 shows the Program Command When Suspend Function Disabled F...

Page 410: ...2 REIT Access flash memory FMR42 0 NOTES 1 In EW0 mode the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area 2 td SR SUS is needed until the interrupt request is acknowledged after it is generated The interrupt to enter suspend should be in interrupt enabled status 3 When no interrupt is used the instruction to enable interrupts is not neede...

Page 411: ...block 0 is not acknowledged When the FMR16 bit is set to 1 disable rewriting the block erase command on block 1 is not acknowledged Do not use the block erase command during program suspend Figure 19 14 shows the Block Erase Command When Erase Suspend Function Disabled Figure 19 15 shows the Block Erase Command When Erase Suspend Function Enabled In EW1 mode do not execute this command on any addr...

Page 412: ...e interrupt 2 REIT Access flash memory FMR41 0 NOTES 1 In EW0 mode the interrupt vector table and interrupt routine for interrupts to be used should be allocated to the RAM area 2 td SR SUS is needed until the interrupt request is acknowledged after it is generated The interrupt to enter suspend should be in interrupt enabled status 3 When no interrupt is used the instruction to enable interrupts ...

Page 413: ...quencer status indicates operating status of the flash memory SR7 0 busy during auto programming and auto erasing and is set to 1 ready at the same time the operation completes 19 4 4 2 Erase Status Bits SR5 and FMR07 Refer to 19 4 5 Full Status Check 19 4 4 3 Program Status Bits SR4 and FMR06 Refer to 19 4 5 Full Status Check D0 to D7 Indicates the data bus which is read when the read status regi...

Page 414: ...1 Command sequence error When any command is not written correctly When invalid data other than those that can be written in the second bus cycle of the block erase command is written i e other than D0h or FFh 1 When executing the program command or block erase command while rewriting is disabled using the FMR02 bit in the FMR0 register the FMR15 or FMR16 bit in the FMR1 register When inputting an...

Page 415: ... No Yes Yes No Yes No Command sequence error Erase error Program error Command sequence error Execute the clear status register command set these status flags to 0 Check if command is properly input Re execute the command Erase error Execute the clear status register command set these status flags to 0 Erase command re execution times 3 times Re execute block erase command Program error Execute th...

Page 416: ...essing the pins shown in Table 19 8 and rewriting a flash memory using a writer apply H to the MODE pin and reset a hardware if a program is operated on the flash memory in single chip mode 19 5 1 ID Code Check Function The ID code check function determines whether the ID codes sent from the serial programmer and those written in the flash memory match refer to 19 3 Functions to Prevent Rewriting ...

Page 417: ...external oscillator Apply H and L or leave the pin open when using as input port P4_7 XOUT P4_7 input clock output I O P0_0 to P0_7 Input port P0 I Input H or L level signal or leave the pin open P1_0 to P1_7 Input port P1 I Input H or L level signal or leave the pin open P2_0 to P2_7 Input port P2 I Input H or L level signal or leave the pin open P3_0 P3_1 P3_3 to P3_5 P3_7 Input port P3 I Input ...

Page 418: ...to connect an oscillating circuit when operating with on chip oscillator clock VSS MODE Connect oscillator circuit 1 Package PLQP0048KB A VCC 48 R8C 20 Group R8C 21 Group 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 Mode setting Signal Value MODE RESET Voltage from programmer VSS VCC ...

Page 419: ...e 3 NOTES 1 In this example modes are switched between single chip mode and standard serial I O mode by controlling the MODE input with a switch 2 Connecting the oscillation is necessary Set the main clock frequency 1 MHz to 20 MHz Refer to Appendix Figure 2 1 Connection Example with M16C Flash Starter M3A 0806 MCU TXD RXD Data output Data input MODE NOTES 1 Controlled pins and external circuits v...

Page 420: ...y Use a parallel programmer which supports this MCU Contact the manufacturer of your parallel programmer about the parallel programmer and refer to the user s manual of your parallel programmer for details on how to use it User ROM area can be rewritten shown in Figure 19 1 and Figure 19 2 in parallel I O mode 19 6 1 ROM Code Protect Function The ROM code protect function disables to read and rewr...

Page 421: ...OM 2 Do not use the non maskable interrupt while block 0 is automatically erased because the fixed vector is allocated block 0 Table 19 9 EW0 Mode Interrupts Mode Status When Maskable Interrupt Request is Acknowledged When Watchdog Timer Oscillation Stop Detection and Voltage Monitor 2 Interrupt Request are Acknowledged EW0 During automatic erasing Any interrupt can be used by allocating a vector ...

Page 422: ...ed The auto erasing can be restarted by setting the FMR41 bit in the FMR4 register to 0 erase restart after the interrupt process completes Once an interrupt request is acknowledged the auto programming or auto erasing is forcibly stopped immediately and resets the flash memory An interrupt process starts after the fixed period and the flash memory restarts Since the block during the auto erasing ...

Page 423: ...R8C 20 Group R8C 21 Group 19 Flash Memory Rev 2 00 Aug 27 2008 Page 407 of 458 REJ09B0250 0200 19 7 1 7 Entering Stop Mode or Wait Mode Do not enter stop mode or wait mode during erase suspend ...

Page 424: ...x VCC AVCC Supply voltage 2 7 5 5 V VSS AVCC Supply voltage 0 V VIH Input H voltage 0 8VCC VCC V VIL Input L voltage 0 0 2VCC V IOH sum Peak sum output H current Sum of all Pins IOH peak 60 mA IOH peak Peak output H current 10 mA IOH avg Average output H current 5 mA IOL sum Peak sum output L currents Sum of all Pins IOL peak 60 mA IOL peak Peak output L currents 10 mA IOL avg Average output L cur...

Page 425: ...eristics Symbol Parameter Conditions Standard Unit Min Typ Max Resolution Vref AVCC 10 Bits Absolute Accuracy 10 bit mode φAD 10 MHz Vref AVCC 5 0 V 3 LSB 8 bit mode φAD 10 MHz Vref AVCC 5 0 V 2 LSB 10 bit mode φAD 10 MHz Vref AVCC 3 3 V 5 LSB 8 bit mode φAD 10 MHz Vref AVCC 3 3 V 2 LSB Rladder Resistor ladder Vref AVCC 10 40 kΩ tconv Conversion time 10 bit mode φAD 10 MHz Vref AVCC 5 0 V 3 3 µs 8...

Page 426: ...number of rewrites can be minimized by programming up to 128 groups before erasing them all in one operation It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number 5 If error occurs during block erase attempt to execute the clear status register command then the block erase command at least three times until the erase...

Page 427: ...asing them all in one operation In addition averaging the erasure endurance between blocks A and B can further reduce the actual erasure endurance It is also advisable to retain data on the erasure endurance of each block and limit the number of erase operations to a certain number 6 If error occurs during block erase attempt to execute the clear status register command then the block erase comman...

Page 428: ...since the voltage passes Vdet2 3 Necessary time until the voltage detection circuit operates when setting to 1 again after setting the VCA27 bit in the VCA2 register to 0 4 Hold Vdet2 Vdet1 5 When using the digital filter its sampling time is added to td Vdet2 A When using the voltage monitor 2 reset maintain this time until VCC 2 0 V after the voltage passes Vdet2 when the power supply falls Tabl...

Page 429: ...25 C maintain tw por1 for 3 000s or more if 40 C Topr 20 C Figure 20 3 Power on Reset Circuit Electrical Characteristics Table 20 8 Power on Reset Circuit Voltage Monitor 1 Reset Circuit Electrical Characteristics 3 Symbol Parameter Condition Standard Unit Min Typ Max Vpor1 Power on reset valid voltage 4 0 1 V Vpor2 Power on reset or voltage monitor 1 valid voltage 0 Vdet1 V trth External power VC...

Page 430: ...4 75 V to 5 25 V 0 C Topr 60 C 2 39 2 40 40 8 MHz VCC 3 0 V to 5 25 V 20 C Topr 85 C 2 38 8 40 41 2 MHz VCC 3 0 V to 5 5 V 40 C Topr 85 C 2 38 4 40 41 6 MHz VCC 3 0 V to 5 5 V 40 C Topr 125 C 2 38 0 40 42 0 MHz VCC 2 7 V to 5 5 V 40 C Topr 125 C 2 37 6 40 42 4 MHz The value of the FRA1 register when the reset is deasserted 08h 40 F7h High speed on chip oscillator adjustment range Adjust the FRA1 r...

Page 431: ...itions Standard Unit Min Typ Max tSUCYC SSCK clock cycle time 4 tCYC 2 tHI SSCK clock H width 0 4 0 6 tSUCYC tLO SSCK clock L width 0 4 0 6 tSUCYC tRISE SSCK clock rising time Master 1 tCYC 2 Slave 1 µs tFALL SSCK clock falling time Master 1 tCYC 2 Slave 1 µs tSU SSO SSI data input setup time 100 ns tH SSO SSI data input hold time 1 tCYC 2 tLEAD SCS setup time Slave 1tCYC 50 ns tLAG SCS hold time ...

Page 432: ... or VOH VIH or VOH tHI tLO tHI tFALL tRISE tLO tSUCYC tOD tH tSU SCS output SSCK output CPOS 1 SSCK output CPOS 0 SSO output SSI input 4 wire bus communication mode Master CPHS 1 VIH or VOH VIH or VOH tHI tLO tHI tFALL tRISE tLO tSUCYC tOD tH tSU SCS output SSCK output CPOS 1 SSCK output CPOS 0 SSO output SSI input 4 wire bus communication mode Master CPHS 0 CPHS CPOS Bits in SSMR register ...

Page 433: ...VOH SCS input SSCK input CPOS 1 SSCK input CPOS 0 SSO input SSI output 4 wire bus communication mode Slave CPHS 1 VIH or VOH VIH or VOH tHI tLO tHI tFALL tRISE tLO tSUCYC tH tSU SCS input SSCK input CPOS 1 SSCK input CPOS 0 SSO input SSI output 4 wire bus communication mode Slave CPHS 0 tOD tLEAD tSA tLAG tOR tHI tLO tHI tFALL tRISE tLO tSUCYC tH tSU tOD tLEAD tSA tLAG tOR CPHS CPOS Bits in SSMR r...

Page 434: ...cteristics Rev 2 00 Aug 27 2008 Page 418 of 458 REJ09B0250 0200 Figure 20 6 I O Timing of Clock Synchronous Serial I O with Chip Select Clock Synchronous Communication Mode VIH or VOH tHI tLO tSUCYC tOD tH tSU SSCK SSO output SSI input VIH or VOH ...

Page 435: ... 600 2 ns tSCLH SCL input H width 3tCYC 300 2 ns tSCLL SCL input L width 5tCYC 300 2 ns tsf SCL SDA input falling time 300 ns tSP SCL SDA input spike pulse rejection time 1tCYC 2 ns tBUF SDA input bus free time 5tCYC 2 ns tSTAH Start condition input hole time 3tCYC 2 ns tSTAS Retransmit start condition input setup time 3tCYC 2 ns tSTOP Stop condition input setup time 3tCYC 2 ns tSOAS Data input se...

Page 436: ...0 µA VCC 0 3 VCC V XOUT Drive capacity HIGH IOH 1 mA VCC 2 0 VCC V Drive capacity LOW IOH 500 µA VCC 2 0 VCC V VOL Output L Voltage Except XOUT IOL 5 mA 2 0 V IOL 200 µA 0 45 V XOUT Drive capacity HIGH IOL 1 mA 2 0 V Drive capacity LOW IOL 500 µA 2 0 V VT VT Hysteresis INT0 INT1 INT2 INT3 KI0 KI1 KI2 KI3 TRAIO RXD0 RXD1 CLK0 SSI SCL SDA SSO 0 1 0 5 V RESET 0 1 1 0 V IIH Input H current VI 5 V VCC ...

Page 437: ...or on 125 kHz Divide by 8 2 8 mA High speed on chip oscillator mode XIN clock off High speed on chip oscillator on fOCO 10 MHz Low speed on chip oscillator on 125 kHz No division 5 8 11 6 mA XIN clock off High speed on chip oscillator on fOCO 10 MHz Low speed on chip oscillator on 125 kHz Divide by 8 2 5 mA Low speed on chip oscillator mode XIN clock off High speed on chip oscillator off Low speed...

Page 438: ...AIO Input Timing Diagram when VCC 5 V Table 20 16 XIN Input Symbol Parameter Standard Unit Min Max tc XIN XIN input cycle time 50 ns tWH XIN XIN input H width 25 ns tWL XIN XIN input L width 25 ns Table 20 17 TRAIO Input Symbol Parameter Standard Unit Min Max tc TRAIO TRAIO input cycle time 100 ns tWH TRAIO TRAIO input H width 40 ns tWL TRAIO TRAIO input L width 40 ns Vcc 5V XIN input tWH XIN tc X...

Page 439: ...filter clock frequency x 3 or the minimum value of standard Figure 20 11 External Interrupt INTi Input Timing Diagram when VCC 5 V i 0 to 3 Table 20 18 Serial Interface Symbol Parameter Standard Unit Min Max tc CK CLK0 input cycle time 200 ns tW CKH CLK0 input H width 100 ns tW CKL CLK0 input L width 100 ns td C Q TXDi output delay time 50 ns th C Q TXDi hold time 0 ns tsu D C RXDi input setup tim...

Page 440: ...VCC 0 5 VCC V XOUT Drive capacity HIGH IOH 0 1 mA VCC 0 5 VCC V Drive capacity LOW IOH 50 µA VCC 0 5 VCC V VOL Output L voltage Except XOUT IOL 1 mA 0 5 V XOUT Drive capacity HIGH IOL 0 1 mA 0 5 V Drive capacity LOW IOL 50 µA 0 5 V VT VT Hysteresis INT0 INT1 INT2 INT3 KI0 KI1 KI2 KI3 TRAIO RXD0 RXD1 CLK0 SSI SCL SDA SSO 0 1 0 3 V RESET 0 1 0 4 V IIH Input H current VI 3 V VCC 3 V 4 0 µA IIL Input ...

Page 441: ...lator on 125 kHz Divide by 8 2 3 mA High speed on chip oscillator mode XIN clock off High speed on chip oscillator on fOCO 10 MHz Low speed on chip oscillator on 125 kHz No division 5 6 11 2 mA XIN clock off High speed on chip oscillator on fOCO 10 MHz Low speed on chip oscillator on 125 kHz Divide by 8 2 4 mA Low speed on chip oscillator mode XIN clock off High speed on chip oscillator off Low sp...

Page 442: ...IO Input Timing Diagram when VCC 3 V Table 20 22 XIN Input Symbol Parameter Standard Unit Min Max tc XIN XIN input cycle time 100 ns tWH XIN XIN input H width 40 ns tWL XIN XIN input L width 40 ns Table 20 23 TRAIO Input Symbol Parameter Standard Unit Min Max tc TRAIO TRAIO input Cycle time 300 ns tWH TRAIO TRAIO input H width 120 ns tWL TRAIO TRAIO input L width 120 ns Vcc 3V XIN input tWH XIN tc...

Page 443: ...filter clock frequency x 3 or the minimum value of standard Figure 20 15 External Interrupt INTi Input Timing Diagram when VCC 3 V i 0 to 3 Table 20 24 Serial Interface Symbol Parameter Standard Unit Min Max tc CK CLK0 input cycle time 300 ns tW CKH CLK0 input H width 150 ns tW CKL CLK0 input L width 150 ns td C Q TXDi output delay time 80 ns th C Q TXDi hold time 0 ns tsu D C RXDi input setup tim...

Page 444: ...tect disabled FSET I Enable interrupt BSET 0 CM1 Stop mode JMP B LABEL_001 LABEL_001 NOP NOP NOP NOP 21 1 2 Wait Mode When entering wait mode set the FMR01 bit to 0 CPU rewrite mode disabled and execute the WAIT instruction An instruction queue pre reads 4 bytes from the WAIT instruction and the program stops Insert at least 4 NOP instructions after the WAIT instruction Example to execute the WAIT...

Page 445: ... among the enabled interrupts is set to 0 This may cause a problem that the interrupt is canceled or an unexpected interrupt is generated 21 2 2 SP Setting Set any value in the SP before an interrupt is acknowledged The SP is set to 0000h after reset Therefore if an interrupt is acknowledged before setting any value in the SP the program may run out of control 21 2 3 External Interrupt and Key Inp...

Page 446: ...ctions Figure 21 1 shows an Example of Procedure for Changing Interrupt Sources Figure 21 1 Example of Procedure for Changing Interrupt Sources NOTES 1 Execute the above settings individually Do not execute two or more settings at once by one instruction 2 To prevent interrupt requests from being generated disable the peripheral function before changing the interrupt source In this case use the I ...

Page 447: ... interrupt not requested it may not be set to 0 depending on the instruction to be used Therefore use the MOV instruction to set the IR bit to 0 c When disabling interrupts using the I flag set the I flag according to the following sample programs Refer to b for the change of interrupt control registers in the sample programs Sample programs 1 to 3 are preventing the I flag from being set to 1 int...

Page 448: ...s before the count starts The TEDGF bit may be set to 1 by timer RA prescaler underflow which is generated for the first time since the count starts When using the pulse period measurement mode leave two periods or more of timer RA prescaler immediately after count starts and set the TEDGF bit to 0 The TCSTF bit retains 0 count stops for 0 to 1 cycle of the count source after setting the TSTART bi...

Page 449: ...the TSTART bit to 0 count stops while the count is performing Timer RB counting is stopped when the TCSTF bit is set to 0 During this time do not access registers associated with timer RB 1 other than the TCSTF bit NOTE 1 Registers associated with timer RB TRBCR TRBOCR TRBIOC TRBMR TRBPRE TRBSC TRBPR If the TSTOP bit in the TRBCR register is set to 1 during timer operation timer RB stops immediate...

Page 450: ...register does not occur during period A shown in Figures 21 2 and 21 3 The following shows the detailed workaround examples Workaround example a As shown in Figure 21 2 write to registers TRBSC and TRBPR in the timer RB interrupt routine These write operations must be completed by the beginning of period A Figure 21 2 Workaround Example a When Timer RB Interrupt is Used TRBO pin output Count sourc...

Page 451: ...ion mode The following two workarounds should be performed in programmable one shot generation mode 1 To write to registers TRBPRE and TRBPR during count operation TCSTF bit is set to 1 note the following points When the TRBPRE register is written continuously during count operation TCSTF bit is set to 1 allow three or more cycles of the count source for each write interval When the TRBPR register...

Page 452: ... allow three or more cycles of the prescaler underflow for each write interval 2 Do not set both the TRBPRE and TRBPR registers to 00h 3 Set registers TRBSC and TRBPR using the following procedure a To use INT0 pin one shot trigger enabled as the count start condition Set the TRBSC register and then the TRBPR register At this time after writing to the TRBPR register allow an interval of 0 5 or mor...

Page 453: ...er is set to 0000h These precautions are applicable when selecting the following by the CCLR2 to CCLR0 bits in the TRDCRi register 001b clear by the TRDi register at the compare match with the TRDGRAi register 010b clear by the TRDi register at the compare match with the TRDGRBi register 011b synchronous clear 101b clear by the TRDi register at the compare match with the TRDGRCi register 110b clea...

Page 454: ...to 0 count stops 2 Set the CMD1 to CMD0 bits in the TRDFCR register to 00b timer mode PWM mode and PWM3 mode 3 Set the CMD1 to CMD0 bits to 01b reset synchronous PWM mode 4 Set the registers associated with other Timer RD again 21 3 3 7 Complementary PWM Mode When complementary PWM mode is used for motor control use it with OLS0 OLS1 Change the CMD1 to CMD0 bits in the TRDFCR register in the follo...

Page 455: ...red to the general register TRDGRB0 TRDGRA1 TRDGRB1 For the order of m 1 m m 1 operation the IMFA bit remains unchanged and data are not transferred to the register such as the TRDGRA0 register Figure 21 4 Operation at Compare Match between Registers TRD0 and TRDGRA0 in Complementary PWM Mode No change IMFA bit in TRDSR0 register Transferred from buffer register TRDGRB0 register TRDGRA1 register T...

Page 456: ... general register TRDGRB0 TRDGRA1 TRDGRB1 For the order of FFFFh 0 1 operation data are not transferred to the register such as the TRDGRB0 register Also at this time the OVF bit remains unchanged Figure 21 5 Operation When TRD1 Register Underflows in Complementary PWM Mode No change UDF bit in TRDSR0 register Transferred from buffer register TRDGRB0 register TRDGRA1 register TRDGRB1 register Coun...

Page 457: ...e CMD1 to CMD0 bits Figure 21 6 Operation When Value in Buffer Register Value in TRDGRA0 Register in Complementary PWM Mode 0000h TRDGRD0 register TRDIOB0 output n3 n2 m 1 n3 n2 n1 n2 n1 n3 n2 n2 n1 n1 TRDGRB0 register Transfer Transfer by underflow in TRD1 register because of n3 m Transfer by underflow in TRD1 register because of first setting to n2 m TRDIOD0 output m Setting Value in TRDGRA0 Reg...

Page 458: ...age other than that do not set bits TCK2 to TCK0 in registers TRDCR0 and TRDCR to 110b select fOCO40M as the count source 0000h TRDGRD0 register TRDIOB0 output n1 m 1 n 2 n1 0000h n1 0000h n1 n1 n2 TRDGRB0 register Transfer Transfer by compare match in TRD0 and TRDGRA0 registers because content in TRDGRD0 register is set to 0000h Transfer by compare match in TRD0 and TRDGRA0 registers because of f...

Page 459: ...t Also timer RE stops counting when setting the TSTART bit to 0 count stops and the TCSTF bit is set to 0 count stops It takes the time for up to 2 cycles of the count source until the TCSTF bit is set to 0 after setting the TSTART bit to 0 During this time do not access registers associated with timer RE other than the TCSTF bit NOTE 1 Registers associated with Timer RE TRESEC TREMIN TRECR1 TRECR...

Page 460: ...its in the UiRB register and the RI bit in the UiC1 register are set to 0 To check receive errors read the UiRB register and then use the read data Example when reading receive buffer register MOV W 00A6H R0 Read the U0RB register When writing data to the UiTB register in the clock asynchronous serial I O mode with 9 bit transfer data length write data high order byte first then low order byte in ...

Page 461: ...f the other masters For example if the fastest transfer rate of the other masters is set to 400 kbps the I2C bus transfer rate in this MCU should be set to 223 kbps 400 1 18 or more Bits MST and TRS in the ICCR1 register setting a Use the MOV instruction to set bits MST and TRS b When arbitration is lost confirm the contents of bits MST and TRS If the contents are other than the MST bit set to 0 a...

Page 462: ...ug 27 2008 Page 446 of 458 REJ09B0250 0200 21 6 Notes on Hardware LIN For the time out processing of the header and response fields use another timer to measure the duration of time with respect to a Synch Break detection interrupt as the starting point ...

Page 463: ...n the ADIC register or the ADST bit in the ADCON0 register can determine whether the A D conversion is completed When using the repeat mode select the frequency of the A D converter operating clock φAD or more for the CPU clock during A D conversion Do not select the fOCO F for the φAD If setting the ADST bit in the ADCON0 register to 0 A D conversion stops by a program and the A D conversion is f...

Page 464: ...M 2 Do not use the non maskable interrupt while block 0 is automatically erased because the fixed vector is allocated block 0 Table 21 2 EW0 Mode Interrupts Mode Status When Maskable Interrupt Request is Acknowledged When Watchdog Timer Oscillation Stop Detection and Voltage Monitor 2 Interrupt Request are Acknowledged EW0 During automatic erasing Any interrupt can be used by allocating a vector t...

Page 465: ...d The auto erasing can be restarted by setting the FMR41 bit in the FMR4 register to 0 erase restart after the interrupt process completes Once an interrupt request is acknowledged the auto programming or auto erasing is forcibly stopped immediately and resets the flash memory An interrupt process starts after the fixed period and the flash memory restarts Since the block during the auto erasing o...

Page 466: ...R8C 20 Group R8C 21 Group 21 Usage Notes Rev 2 00 Aug 27 2008 Page 450 of 458 REJ09B0250 0200 21 8 1 7 Entering Stop Mode or Wait Mode Do not enter stop mode or wait mode during erase suspend ...

Page 467: ...possible 21 9 2 Countermeasures against Noise Error of Port Control Registers During severe noise testing mainly power supply system noise and introduction of external noise the data of port related registers may be changed As a firmware countermeasure it is recommended to periodically reset the port registers port direction registers and pull up control registers However examine fully before intr...

Page 468: ...ers 2 Some of the user flash memory and RAM areas are used by the on ship debugger These areas cannot be accessed by the user Refer to the on chip debugger manual for which areas are used 3 Do not set the address match interrupt the registers of AIER RMAD0 RMAD1 and the fixed vector tables in a user system 4 Do not use the BRK instruction in a user system Connecting and using the on chip debugger ...

Page 469: ... following attention 1 Do not use the following flash memory areas because these areas are used for the emulator debugger When debugging of these areas intensive evaluation on the real chip is required ROM 128 KB Product R5F2120CJFP R5F2120CKFP R5F2121CJFP R5F2121CKFP addresses 20000h to 23FFFh Connecting and using the emulator debugger has some peculiar restrictions Refer to each emulator debugge...

Page 470: ...ONS 1 AND 2 DO NOT INCLUDE MOLD FLASH NOTE DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET Detail F L1 c A L A 1 A 2 3 F 48 37 36 25 24 13 12 1 1 2 x Index mark y Z E ZD bp e H E HD D E Previous Code JEITA Package Code RENESAS Code PLQP0048KB A 48P6Q A MASS Typ 0 2g P LQFP48 7x7 0 50 1 0 0 125 0 20 0 75 0 75 0 08 0 20 0 145 0 09 0 27 0 22 0 17 Max Nom Min Dimension in Millimeters Symbol Reference 7 1 7 0...

Page 471: ...1 VCC 10 M16C Flash Starter M3A 0806 RXD TXD TXD RESET 48 R8C 20 Group R8C 21 Group 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 MODE NOTE 1 An oscillation circuit must be connected even when operating with the on chip oscillator clock Connect oscillation circuit 1 Emulator E8 R0E000080KCE00 MODE 4 7kO 10 RESET ...

Page 472: ...3 1 shows the Example of Oscillation Evaluation Circuit Appendix Figure 3 1 Example of Oscillation Evaluation Circuit VSS Connect oscillation circuit VCC RESET 48 R8C 20 Group R8C 21 Group 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 NOTE 1 After reset the XIN clock stops Write a program to oscillate the XIN clo...

Page 473: ... T TRA 123 TRACR 121 TRAIC 92 TRAIOC 121 124 127 129 131 134 TRAMR 122 TRAPRE 122 TRBCR 138 TRBIC 92 TRBIOC 139 141 145 148 153 TRBMR 139 TRBOCR 138 TRBPR 140 TRBPRE 140 TRBSC 140 TRD0 180 195 209 220 232 245 TRD0IC 93 TRD1 180 195 209 232 TRD1IC 93 TRDCR0 176 191 206 218 229 243 TRDCR1 176 191 206 229 TRDDF0 175 TRDDF1 175 TRDFCR 174 188 204 216 227 240 TRDGRAi i 0 or 1 181 196 210 221 232 246 TR...

Page 474: ...8 of 458 REJ09B0250 0200 TRECR2 261 TRECSR 262 TREIC 92 TREMIN 260 TRESEC 260 U U1SR 270 UiBRG i 0 or 1 267 UiC0 i 0 or 1 269 UiC1 i 0 or 1 269 UiMR i 0 or 1 268 UiRB i 0 or 1 267 UiTB i 0 or 1 267 V VCA1 31 VCA2 31 70 VW1C 32 VW2C 33 W WDC 114 WDTR 115 WDTS 115 ...

Page 475: ...eration System clock generation circuit revised 5 Table 1 3 Product Information of R8C 20 Group revised Figure 1 2 Type Number Memory Size and Package of R8C 20 Group revised 6 Table 1 4 Product Information of R8C 21 Group revised Figure 1 3 Type Number Memory Size and Package of R8C 21 Group revised 7 Figure 1 4 Pin Assignments Top View TCLK TRDCLK revised 8 Table 1 5 Pin Functions Analog Power S...

Page 476: ...00b 0024h TBD Value when shipping NOTES revised 24 Figure 5 4 OFS Register Function of the LVD1ON bit after Hardware reset after reset revised NOTES revised 25 5 1 1 When Power Supply is Stable 2 revised 5 1 2 Power On 4 revised 26 Figure 5 5 Example of Hardware Reset Circuit and Operation and Figure 5 6 Example of Hardware Reset Circuit Usage Example of External Supply Voltage Detection Circuit a...

Page 477: ...ded Table 9 3 Access Unit and Bus Operations SFR SFR data flash ROM RAM ROM program ROM RAM below the Table 9 3 However only following at a time added 67 Figure 10 2 CM0 Register NOTE6 deleted 69 Figure 10 4 OCD Register System clock select bet 3 System clock select bet 4 1 Selects on chip oscillator clock 4 1 Selects on chip oscillator clock 3 corrected 70 Figure 10 5 Registers FRA0 and FRA1 NOTE...

Page 478: ... 12 2 Relocatable Vector Tables A0RIC S0RIC corrected 96 Table 12 5 IPL Value When Software or Special Interrupt Is Acknowledged Address break added 98 Figure 12 10 Priority Levels of Hardware Interrupts Address break added 109 12 6 Notes on Interrupts 12 6 Precautions on Interrupts 12 6 Notes on Interrupts revised 112 Figure 13 1 Block Diagram of Watchdog Timer L active PM12 Bit in PM1 register a...

Page 479: ...ns TRDIOC1 P2_6 Table 14 19 Pin Functions TRDIOD1 P2_7 Table 14 20 Pin Functions INT0 P4_5 added 162 14 3 1 Mode Selection deleted Table 14 21 Count Source Selection Selection of f1 f2 f4 f8 f32 and fOCO40M revised Figure 14 29 Block Diagram of Count Source TPSC2 to TPSC0 TCK2 to TCK0 revised 163 Figure 14 30 Buffer Operation in Input Capture Function revised 164 Figure 14 31 Buffer Operation in O...

Page 480: ...ns on the 5 to 6th lines from the bottom TRCIOAi TRDIOAi and TRCIOBi TRDIOBi corrected 184 Figure 14 49 Registers TRDSTR and TRDMR in Output Compare Function revised 185 Figure 14 50 TRDPMR Register in Output Compare Function revised 186 Figure 14 51 TRDFCR Register in Output Compare Function revised 187 Figure 14 52 Registers TRDOER1 to TRDOER2 in Output Compare Function NOTE in the TRDOER2 regis...

Page 481: ... Registers TRDOER1 to TRDOER2 in Complementary PWM Mode NOTE in the TRDOER2 register added 227 Figure 14 92 Registers TRDCR0 to TRDCR1 in Complementary PWM Mode revised 228 Figure 14 93 Registers TRDSR0 to TRDSR1 in Complementary PWM Mode revised 231 Below the Table 14 32 Since values buffer register added 235 Figure 14 99 Block Diagram of PWM3 Mode Buffer added 236 Table 14 33 PWM3 Mode Specifica...

Page 482: ...7 Figure 15 11 Receive Timing Example in UART Mode revised 279 15 3 Notes on Serial Interface 15 3 Precautions on Serial Interface 15 3 Notes on Serial Interface revised 280 16 Clock Synchronous Serial Interface on the 3rd line SSU added 281 16 2 Clock Synchronous Serial I O with Chip Select SSU SSU added Table 16 2 Clock Synchronous Serial I O with Chip Select Specifications NOTE2 deleted 285 Fig...

Page 483: ...ster Transmit Mode Clock Synchronous Serial Figure 16 46 Example of Register Setting in Master Transmit Mode I2C Bus Interface Mode revised 339 Figure 16 47 Example of Register Setting in Master Receive Mode I2C Bus Interface Mode Figure 16 47 Example of Register Setting in Master Receive Mode Clock Synchronous Serial Figure 16 47 Example of Register Setting in Master Receive Mode I2C Bus Interfac...

Page 484: ...ected 367 18 3 Sample and Hold on the 2nd and 5th lines to 28 φ AD cycles 10 bit resolution deleted When performing the microcomputer deleted 368 18 4 A D Conversion Cycles added 369 18 5 Internal Equivalent Circuit of Analog Input added 370 18 6 Output Impedance of Sensor Under A D Conversion added 371 18 7 Notes on A D Converter 18 7 Precautions on A D Converter 18 7 Notes on A D Converter revis...

Page 485: ...ure 19 15 Block Erase Command When Erase Suspend Function Enabled revised 393 Table 19 5 Status Register Bits Value after Reset of SR7 D7 0 1 corrected 396 19 5 Standard Serial I O Mode on the 3rd line Standard serial I O interface There are three serial I O mode 3 revised Table 19 7 Pin Functions Flash Memory Standard Serial I O Mode 2 revised 398 Figure 19 17 Pin Connections for Standard Serial ...

Page 486: ...Example of Oscillation Evaluation Circuit revised 1 00 Nov 15 2006 All pages Preliminary and Under development deleted 2 Table 1 1 Functions and Specifications for R8C 20 Group revised NOTE1 deleted 3 Table 1 2 Functions and Specifications for R8C 21 Group revised NOTE1 deleted 5 Table 1 3 Product Information for R8C 20 Group R5F2120AJFP D R5F2120CJFP D R5F2120AKFP D R5F2120CKFP D and NOTE added F...

Page 487: ...s NOTE1 added 48 Figure 7 9 PDi i 0 to 4 and 6 Registers Bit Names revised Figure 7 10 Pi i 0 to 4 and 6 Registers Bit Names revised 64 Table 10 1 Specifications of Clock Generation Circuit NOTE3 10 MHz 20 MHz revised 68 Figure 10 4 OCD Register NOTE7 Figure 10 12 Figure 10 14 corrected 69 Figure 10 5 Registers FRA0 and FRA1 High Speed On Chip Oscillator Control Register 0 1 NOTE2 revised High Spe...

Page 488: ...ower Control Mode Figure 10 12 State Transitions in Power Control Mode corrected 82 10 5 1 How to Use Oscillation Stop Detection Function on the 6th line Figure 10 12 Figure 10 14 corrected On the 10th line Figure 10 11 Figure 10 13 corrected 83 Figure 10 11 Figure 10 13 corrected 84 Figure 10 12 Figure 10 15 corrected 85 10 6 Notes on Clock Generation Circuit revised 94 Figure 12 5 Registers INT0...

Page 489: ...t Mode Figure 14 9 TRAIOC Register in Pulse Width Measurement Mode replaced Timer RA Control Register 4 deleted Figure 14 12 TRAMR Register in Pulse Width Measurement Mode deleted 132 Figure 14 10 Operating Example of Pulse Width Measurement Mode revised 133 Table 14 6 Pulse Period Measurement Mode Specifications revised 134 Figure 14 14 Registers TRACR and TRAIOC in Pulse Period Measurement Mode ...

Page 490: ... RB in Programmable Waveform Generation Mode replaced Figure 14 20 revised 147 Table 14 9 Programmable One Shot Generation Mode Specifications revised NOTE added 148 Figure 14 24 Registers TRBIOC and TRBMR in Programmable One Shot Generation Mode Figure 14 21 TRBIOC Register in Programmable One Shot Generation Mode replaced NOTE revised Timer RB Mode Register deleted 150 14 2 3 1 One Shot Trigger ...

Page 491: ...R Register in PWM Mode Figure 14 62 TRDSTR Register in PWM Mode replaced Timer RD Star Register 1 TRD0 count start bit 4 TRD0 count start flag 4 corrected TRD1 count start bit 5 TRD1 count start flag 5 corrected 202 Figure 14 68 Registers TRDOER1 to TRDOER2 in PWM Mode Figure 14 65 Registers TRDOER1 to TRDOER2 in PWM Mode replaced 203 Figure 14 69 Registers TRDOCR and TRDCR0 to TRDCR1 in PWM Mode ...

Page 492: ...corrected TRD1 count start bit 5 TRD1 count start flag 5 corrected 239 Figure 14 103 TRDOCR Register in PWM3 Mode Figure 14 100 TRDOCR Register in PWM3 Mode replaced NOTE2 added 249 14 3 12 4 Count Source Switch count clock source count source corrected 14 3 12 7 Complementary PWM Mode on the bottom line Do not use the TRDGRC0 register in complementary PWM mode deleted 265 Figure 15 4 UiMR Registe...

Page 493: ...line from the bottom When rewriting the block 2 and block 3 in CPU rewrite mode set the FMR02 bit in the FMR0 register to 1 rewrite enables added 375 Figure 19 1 Flash Memory Block Diagram for R8C 20 Group revised 376 Figure 19 2 Flash Memory Block Diagram for R8C 21 Group revised 378 Figure 19 4 OFS Register NOTE2 LVD0ON LVD1ON and voltage monitor 0 reset enabled after reset voltage monitor 0 res...

Page 494: ...5 Electrical Characteristics 1 VCC 5 V Table 20 14 Electrical Characteristics 1 VCC 5 V revised RAM Hold Voltage Min 1 8 2 0 corrected 418 Table 20 16 Electrical Characteristics 2 Vcc 5 V Table 20 15 Electrical Characteristics 2 Vcc 5 V revised Wait mode revised 421 Table 20 21 Electrical Characteristics 3 VCC 3 V Table 20 20 Electrical Characteristics 3 VCC 3 V revised RAM hold voltage Min 1 8 2 ...

Page 495: ... 5 6 revised 26 5 2 and Figure 5 7 revised 31 Figure 6 4 VCA2 register NOTE5 revised 52 Table 7 17 revised 53 Table 7 19 revised 56 Table 7 29 and Table 7 30 revised 57 Table 7 33 revised 66 Figure 10 2 NOTE4 revised 69 Figure 10 5 FRA0 register NOTE2 revised and FRA1 register NOTE2 added 70 Figure 10 7 VCA2 register NOTE5 revised 73 10 3 2 revised 75 10 4 1 3 revised 76 Table 10 3 Watchdog Timer ...

Page 496: ...ure 14 33 input capture signal added 183 Figure 14 46 revised 185 Table 14 25 Count Stop Conditions revised 201 Table 14 27 Count Stop Conditions revised 214 Table 14 29 Count Stop Conditions revised 221 Figure 14 84 NOTE1 revised 238 Table 14 33 Count Stop Conditions revised 251 14 3 12 1 and Table 14 36 revised 267 Figure 15 3 Registers U0BRG and U1BRG U0BRG UiBRG 271 Table 15 1 NOTE2 revised 27...

Page 497: ...ister 1 356 Figure 17 11 Bit name in the LINST register SCDCT flag BCDCT flag 357 Figure 17 12 Procedure of Hardware LIN Clear the status flags LINST register 0 LINST register 1 362 Figure 18 2 NOTE4 revised 364 Table 18 2 Stop Condition revised 365 Figure 18 4 NOTE4 revised 368 Figure 18 6 NOTE4 revised 372 Figure 18 10 revised SW5 added 373 18 6 the six line from the bottom A D conversion mode w...

Page 498: ...tchdog Timer Interrupt deleted 430 Figure 21 1 NOTE2 revised 432 21 3 1 revised 433 21 3 2 revised and 21 3 2 1 added 434 21 3 2 2 added 435 21 3 2 3 added 436 21 3 2 4 added 437 21 3 3 1 and Table 21 1 revised 444 21 4 the fourth line from the top added 445 21 5 2 1 replaced and 21 5 2 2 added 447 21 7 revised 452 22 revised 455 Appendix Figure 2 2 revised 456 Appendix Figure 3 1 NOTE1 revised 2 ...

Page 499: ...rnal clock 0 internal clock 286 Figure 16 3 revised 302 16 2 5 4 added 305 Figure 16 18 revised 351 Figure 17 6 revised 354 Figure 17 9 revised 375 Table 19 1 NOTE1 revised 398 Table 19 6 FRM0 Register FMR0 Register 408 Table 20 2 NOTE2 revised 410 Table 20 4 NOTE2 and NOTE4 revised 411 Table 20 5 NOTE2 and NOTE5 revised 412 Table 20 6 td Vdet1 A added NOTE5 added Table 20 7 td Vdet2 A and NOTE2 r...

Page 500: ...C 21 Group Hardware Manual Publication Data Rev 0 10 Sep 29 2005 Rev 2 00 Aug 27 2008 Published by Sales Strategic Planning Div Renesas Technology Corp 2008 Renesas Technology Corp All rights reserved Printed in Japan ...

Page 501: ...2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan R8C 20 Group R8C 21 Group Hardware Manual ...

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