Renesas R61509V Specification Download Page 1

Rev. 0.11 April 25, 2008, page 1 of 181 

 

  

 

 

 

 

 

Target Spec

 

 

R61509V 

260k-color, 240RGB x 432-dot graphics liquid crystal 
controller driver for Amorphous-Silicon TFT Panel  

REJxxxxxxx-xxxx 

Rev.0.11 

April 25, 2008

 

 

Description ......................................................................................................... 6

 

Features ......................................................................................................... 7

 

Power Supply Specifications .............................................................................. 8

 

Differences Between R61509 and R61509V...................................................... 9

 

Block Diagram .................................................................................................... 10

 

Block Function.................................................................................................... 11

 

1.

 

System Interface.....................................................................................................................................................11

 

2.

 

External Display Interface (RGB, VSYNC interfaces)........................................................................................12

 

3.

 

Address Counter (AC) ...........................................................................................................................................12

 

4.

 

Graphics RAM (GRAM)........................................................................................................................................13

 

5.

 

Grayscale Voltage Generating Circuit..................................................................................................................13

 

6.

 

Liquid Crystal Drive Power Supply Circuit..........................................................................................................13

 

7.

 

Timing Generator ..................................................................................................................................................13

 

8.

 

Oscillator (OSC).....................................................................................................................................................13

 

9.

 

Liquid crystal driver Circuit..................................................................................................................................13

 

10.

 

Internal Logic Power Supply Regulator...............................................................................................................13

 

Pin Function ........................................................................................................ 14

 

Pad Arrangement ................................................................................................ 19

 

Pad coordinate..................................................................................................... 21

 

Bump Arrangement............................................................................................. 36

 

Connection Example........................................................................................... 37

 

GRAM Address Map .......................................................................................... 38

 

Instruction ......................................................................................................... 40

 

Summary of Contents for R61509V

Page 1: ...Block Diagram 10 Block Function 11 1 System Interface 11 2 External Display Interface RGB VSYNC interfaces 12 3 Address Counter AC 12 4 Graphics RAM GRAM 13 5 Grayscale Voltage Generating Circuit 13 6 Liquid Crystal Drive Power Supply Circuit 13 7 Timing Generator 13 8 Oscillator OSC 13 9 Liquid crystal driver Circuit 13 10 Internal Logic Power Supply Regulator 13 Pin Function 14 Pad Arrangement 1...

Page 2: ... Control 9 R023h 65 Frame Marker Control R090h 66 Power Control 67 Power Control 1 R100h 67 Power Control 2 R101h 69 Power Control3 R102h 73 Power Control 4 R103h 74 RAM Access 75 RAM Address Set Horizontal Address R200h RAM Address Set Vertical Address R201h 75 GRAM Data Write R202h 76 GRAM Data Read R202h 77 NVM Data Read NVM Data Write R280h 78 Window Address Control 81 Window Horizontal RAM Ad...

Page 3: ...2 Notes to VSYNC Interface Operation 114 FMARK Interface 116 FMP Setting Example 120 RGB Interface 121 RGB Interface 121 Polarities of VSYNCX HSYNCX ENABLE and DOTCLK Signals 122 Setting Example of Display Control Clock in RGB Interface Operation 123 RGB Interface Timing 124 16 18 Bit RGB Interface Timing 124 RAM access via system interface in RGB interface operation 125 16 Bit RGB Interface 126 1...

Page 4: ...ns of Power supply Circuit External Elements 151 Voltage Setting Pattern Diagram 152 Liquid Crystal Application Voltage Waveform and Electrical Potential 153 VCOMH and VREG1OUT Voltage Adjustment Sequence 154 NVM Control 155 NVM Load Register Resetting Sequence 156 NVM Write Sequence 157 NVM Erase Sequence 158 Power Supply Setting Sequence 159 Notes to Power Supply ON Sequence 161 Instruction Sett...

Page 5: ...ial Interface Timing Characteristics 173 RGB Interface Timing Characteristics 173 LCD Driver Output Characteristics 174 Reset Timing Characteristics 174 Notes to Electrical Characteristics 175 Test Circuits 176 Timing Characteristics 177 80 system Bus Interface 177 Clock Synchronous Serial Interface 178 Reset Operation 178 LCD Driver and VCOM Output Characteristics 179 ...

Page 6: ...s as system interface to the microcomputer As moving picture interface the R61509V also supports RGB interface VSYNCX HSYNCX DOTCLK ENABLE and DB17 0 The power supply circuit incorporates step up circuit and voltage follower circuit to generate TFT liquid crystal panel drive voltages The R61509V s power management functions such as 8 color display and shut down and so on make this LSI an ideal dri...

Page 7: ...with a moving picture simultaneously Abundant color display and drawing functions Programmable for 262k color display Partial display function Low power consumption architecture allowing direct input of interface I O power supply Shut down function 8 color display function Input power supply voltages IOVCC interface I O power supply VCC logic regulator power supply VCI liquid crystal analog circui...

Page 8: ... IM1 2 RESETX DB17 0 RDX SDI SDO WR_SCL RS CSX VSYNCX HSYNCX DOTCLK ENABLE FMARK Connect to VCC and VCI on the FPC when the electrical potentials are the same VCC logic regulator power supply 2 5V 3 3V Connect to IOVCC and VCI on the FPC when the electrical potentials are the same 5 Input voltage VCI liquid crystal drive power supply voltage 2 5V 3 3V Connect to IOVCC and VCC on the FPC when the e...

Page 9: ... Power Control 1 SAP 1 0 Adjusts bias current in source amplifier Supported Deleted Because the sequence is changed See Power Supply Setting Sequence for detail SAP SOAPON Enables source amplifier Supported Deleted Because the sequence is changed See Power Supply Setting Sequence for detail BT 2 0 Defines step up factor DDVDH x2 VCL x 1 VGH x6 x7 VGL x 3 x 4 x 5 DDVDH x2 VCL x 1 VGH x5 x6 VGL x 3 ...

Page 10: ... 㩷 㩷 㩷 㩷 18 18 18 18 VPP1 VPP3A 3B IM2 1 IM0_ID VCL PROTECT Index Register IR Control Register CR Address Counter Graphic RAM GRAM 233 280byte Write data latch Read data latch System interface 18 bit 16 bit 9 bit 8 bit Serial External display interface Timing generator Oscillator Internal reference voltage generating circuit Internal logic power supply circuit LCD drive level generating circuit La...

Page 11: ...tically written to the internal GRAM by internal operation The data is read via RDR from the internal GRAM Therefore invalid data is sent to the data bus when the R61509V performs the first read operation from the internal GRAM Valid data is read out when the R61509V performs the second and subsequent read operation The R61509V allows writing instructions consecutively by executing the instruction...

Page 12: ... signals VSYNCX HSYNCX and DOTCLK In RGB interface operation data DB17 0 is written in synchronization with these signals when the polarity of enable signal ENABLE allows write operation in order to prevent flicker when updating display data In VSYNC interface operation the display operation is synchronized with the internal clock except frame synchronization which synchronizes the display operati...

Page 13: ...The R61509V generates the RC oscillation clock internally Using an external oscillation resistor is not possible The oscillation frequency is set to 678 kHz before shipment for details see Electrical Characteristics Use the frame frequency adjustment function to change the number of display lines and the frame frequency While the R61509V is shut down RC oscillation halts so that reduce power consu...

Page 14: ... allocated several different places on the chip Make sure to connect all of them to power following Connection Example Table 6 Bus Interface Amplitude IOVCC GND Signal I O Connect to Function When not used CSX I Host processor Chip selection signal Amplitude IOVCC GND Low The R61509V is selected and accessible High The R61509V is not selected and not accessible IOVCC RS I Host processor Register s...

Page 15: ...cessor Line synchronous signal Low active Amplitude IOVCC GND GND IOVCC DOTCLK I Host processor Dot clock signal Data is input on the rising edge of DOTCLK Amplitude IOVCC GND GND IOVCC FMARK O Host processor Frame head pulse Amplitude IOVCC GND FMARK is used when writing data to the internal RAM Open IM2 1 IM0_ID I GND IOVCC Select host processor interface Amplitude IOVCC GND IM2 IM1 IM0 System I...

Page 16: ...eference voltage for step up circuit 1 Make sure that DDVDH VGH and VGL output voltages do no go exceed the ratings DDVDH O Stabilizing capacitor Power supply for the source driver liquid crystal drive unit and VCOM drive Connect to a stabilizing capacitor VGH O Stabilizing capacitor Power supply for the gate driver liquid crystal drive unit Connect to a stabilizing capacitor VGL O Stabilizing cap...

Page 17: ...COMH and VCOML The alternating cycle is set by internal register Also the VCOM output can be started and halted by register setting VCOMH O Stabilizing capacitor The High level of VCOM amplitude The output level can be adjusted by either external resistor VCOMR or electronic volume VCOML O Stabilizing capacitor The Low level of VCOM amplitude The output level can be adjusted by instruction VDV bit...

Page 18: ... 1 4 DUMMYR1 and DUMMYR4 DUMMYR2 and DUMMYR3 are short circuited within the chip for COG contact resistance measurement Open VGLDMY 1 4 O Unused gate line Output VGL level Use when fixing unused gate line of the panel Open DUMMYA Open Dummy pad Leave open OPEN DUMMYB Open Dummy pad Leave open OPEN DUMMYC Open Dummy pad Leave open OPEN TESTO1 15 O Dummy pad Leave open OPEN TEST 1 5 I GND Test pin C...

Page 19: ...143 VCOML 144 VCOML 145 GND 146 GND 147 GND 148 GND 149 GND 150 GND 151 GND 152 GND 153 GND 154 VGS 155 AGND 156 AGND 157 AGND 158 AGND 159 AGND 160 AGND 161 AGND 162 AGND 163 AGND 164 VTEST Open 165 VCIR Open 166 VREG1OUT 167 VCOMR 168 C11M 169 C11M 170 C11M 171 C11M 172 C11M 173 C11P 174 C11P 175 C11P 176 C11P 177 C11P 178 C12M 179 C12M 180 C12M S716 489 181 C12M S717 488 182 C12M S718 487 183 C...

Page 20: ...p height 12μm Alignment mark Table 10 Alignment marks X axis Y axis 1 a 9381 0 251 0 Type A 1 b 9381 0 251 0 㩷 㩷 㩷 㩷 㩷 X Y 30um 30um 30um 30um 30um 20um 20um 30um 30um 30um 30um 30um 75um 75um 1 a Left Alignment Mark 150um Alignment Mark Area X size 150um Alignment Mark Area Y size Alignment Mark Area 30um 30um 30um 30um 30um 20um 20um 150um Alignment Mark Area X size 150um Alignment Mark Area Y s...

Page 21: ... 0 72 DUMMYB 4165 0 269 0 23 VCCDUM1 7595 0 269 0 73 VSYNCX 4095 0 269 0 24 DUMMYA 7525 0 269 0 74 HSYNCX 4025 0 269 0 25 DUMMYA 7455 0 269 0 75 IOVCCDUM2 3955 0 269 0 26 DUMMYA 7385 0 269 0 76 ENABLE 3885 0 269 0 27 DUMMYA 7315 0 269 0 77 DOTCLK 3815 0 269 0 28 DUMMYA 7245 0 269 0 78 DB17 3745 0 269 0 29 GNDDUM2 7175 0 269 0 79 DB16 3675 0 269 0 30 AGND 7105 0 269 0 80 GNDDUM5 3605 0 269 0 31 AGN...

Page 22: ...1M 2835 0 269 0 123 VDD 595 0 269 0 173 C11P 2905 0 269 0 124 VMON 525 0 269 0 174 C11P 2975 0 269 0 125 VCOM 455 0 269 0 175 C11P 3045 0 269 0 126 VCOM 385 0 269 0 176 C11P 3115 0 269 0 127 VCOM 315 0 269 0 177 C11P 3185 0 269 0 128 VCOM 245 0 269 0 178 C12M 3255 0 269 0 129 VCOM 175 0 269 0 179 C12M 3325 0 269 0 130 VCOM 105 0 269 0 180 C12M 3395 0 269 0 131 VCOM 35 0 269 0 181 C12M 3465 0 269 0...

Page 23: ...35 0 269 0 272 G12 9262 5 276 0 223 VGL 6405 0 269 0 273 G14 9247 5 157 0 224 VGL 6475 0 269 0 274 G16 9232 5 276 0 225 VGL 6545 0 269 0 275 G18 9217 5 157 0 226 VGL 6615 0 269 0 276 G20 9202 5 276 0 227 VGL 6685 0 269 0 277 G22 9187 5 157 0 228 VGL 6755 0 269 0 278 G24 9172 5 276 0 229 VGL 6825 0 269 0 279 G26 9157 5 157 0 230 VGL 6895 0 269 0 280 G28 9142 5 276 0 231 VGL 6965 0 269 0 281 G30 912...

Page 24: ...276 0 323 G114 8497 5 157 0 373 G214 7747 5 157 0 324 G116 8482 5 276 0 374 G216 7732 5 276 0 325 G118 8467 5 157 0 375 G218 7717 5 157 0 326 G120 8452 5 276 0 376 G220 7702 5 276 0 327 G122 8437 5 157 0 377 G222 7687 5 157 0 328 G124 8422 5 276 0 378 G224 7672 5 276 0 329 G126 8407 5 157 0 379 G226 7657 5 157 0 330 G128 8392 5 276 0 380 G228 7642 5 276 0 331 G130 8377 5 157 0 381 G230 7627 5 157 ...

Page 25: ...62 5 276 0 423 G314 6997 5 157 0 473 G414 6247 5 157 0 424 G316 6982 5 276 0 474 G416 6232 5 276 0 425 G318 6967 5 157 0 475 G418 6217 5 157 0 426 G320 6952 5 276 0 476 G420 6202 5 276 0 427 G322 6937 5 157 0 477 G422 6187 5 157 0 428 G324 6922 5 276 0 478 G424 6172 5 276 0 429 G326 6907 5 157 0 479 G426 6157 5 157 0 430 G328 6892 5 276 0 480 G428 6142 5 276 0 431 G330 6877 5 157 0 481 G430 6127 5...

Page 26: ... 4567 5 157 0 523 S682 5302 5 276 0 573 S632 4552 5 276 0 524 S681 5287 5 157 0 574 S631 4537 5 157 0 525 S680 5272 5 276 0 575 S630 4522 5 276 0 526 S679 5257 5 157 0 576 S629 4507 5 157 0 527 S678 5242 5 276 0 577 S628 4492 5 276 0 528 S677 5227 5 157 0 578 S627 4477 5 157 0 529 S676 5212 5 276 0 579 S626 4462 5 276 0 530 S675 5197 5 157 0 580 S625 4447 5 157 0 531 S674 5182 5 276 0 581 S624 443...

Page 27: ... 3067 5 157 0 623 S582 3802 5 276 0 673 S532 3052 5 276 0 624 S581 3787 5 157 0 674 S531 3037 5 157 0 625 S580 3772 5 276 0 675 S530 3022 5 276 0 626 S579 3757 5 157 0 676 S529 3007 5 157 0 627 S578 3742 5 276 0 677 S528 2992 5 276 0 628 S577 3727 5 157 0 678 S527 2977 5 157 0 629 S576 3712 5 276 0 679 S526 2962 5 276 0 630 S575 3697 5 157 0 680 S525 2947 5 157 0 631 S574 3682 5 276 0 681 S524 293...

Page 28: ... 1567 5 157 0 723 S482 2302 5 276 0 773 S432 1552 5 276 0 724 S481 2287 5 157 0 774 S431 1537 5 157 0 725 S480 2272 5 276 0 775 S430 1522 5 276 0 726 S479 2257 5 157 0 776 S429 1507 5 157 0 727 S478 2242 5 276 0 777 S428 1492 5 276 0 728 S477 2227 5 157 0 778 S427 1477 5 157 0 729 S476 2212 5 276 0 779 S426 1462 5 276 0 730 S475 2197 5 157 0 780 S425 1447 5 157 0 731 S474 2182 5 276 0 781 S424 143...

Page 29: ...1 772 5 157 0 823 S382 802 5 276 0 873 S340 787 5 276 0 824 S381 787 5 157 0 874 S339 802 5 157 0 825 S380 772 5 276 0 875 S338 817 5 276 0 826 S379 757 5 157 0 876 S337 832 5 157 0 827 S378 742 5 276 0 877 S336 847 5 276 0 828 S377 727 5 157 0 878 S335 862 5 157 0 829 S376 712 5 276 0 879 S334 877 5 276 0 830 S375 697 5 157 0 880 S333 892 5 157 0 831 S374 682 5 276 0 881 S332 907 5 276 0 832 S373...

Page 30: ...2272 5 157 0 923 S290 1537 5 276 0 973 S240 2287 5 276 0 924 S289 1552 5 157 0 974 S239 2302 5 157 0 925 S288 1567 5 276 0 975 S238 2317 5 276 0 926 S287 1582 5 157 0 976 S237 2332 5 157 0 927 S286 1597 5 276 0 977 S236 2347 5 276 0 928 S285 1612 5 157 0 978 S235 2362 5 157 0 929 S284 1627 5 276 0 979 S234 2377 5 276 0 930 S283 1642 5 157 0 980 S233 2392 5 157 0 931 S282 1657 5 276 0 981 S232 2407...

Page 31: ...5 157 0 1023 S190 3037 5 276 0 1073 S140 3787 5 276 0 1024 S189 3052 5 157 0 1074 S139 3802 5 157 0 1025 S188 3067 5 276 0 1075 S138 3817 5 276 0 1026 S187 3082 5 157 0 1076 S137 3832 5 157 0 1027 S186 3097 5 276 0 1077 S136 3847 5 276 0 1028 S185 3112 5 157 0 1078 S135 3862 5 157 0 1029 S184 3127 5 276 0 1079 S134 3877 5 276 0 1030 S183 3142 5 157 0 1080 S133 3892 5 157 0 1031 S182 3157 5 276 0 1...

Page 32: ...72 S41 5272 5 157 0 1123 S90 4537 5 276 0 1173 S40 5287 5 276 0 1124 S89 4552 5 157 0 1174 S39 5302 5 157 0 1125 S88 4567 5 276 0 1175 S38 5317 5 276 0 1126 S87 4582 5 157 0 1176 S37 5332 5 157 0 1127 S86 4597 5 276 0 1177 S36 5347 5 276 0 1128 S85 4612 5 157 0 1178 S35 5362 5 157 0 1129 S84 4627 5 276 0 1179 S34 5377 5 276 0 1130 S83 4642 5 157 0 1180 S33 5392 5 157 0 1131 S82 4657 5 276 0 1181 S...

Page 33: ...1223 G415 6232 5 157 0 1273 G315 6982 5 157 0 1224 G413 6247 5 276 0 1274 G313 6997 5 276 0 1225 G411 6262 5 157 0 1275 G311 7012 5 157 0 1226 G409 6277 5 276 0 1276 G309 7027 5 276 0 1227 G407 6292 5 157 0 1277 G307 7042 5 157 0 1228 G405 6307 5 276 0 1278 G305 7057 5 276 0 1229 G403 6322 5 157 0 1279 G303 7072 5 157 0 1230 G401 6337 5 276 0 1280 G301 7087 5 276 0 1231 G399 6352 5 157 0 1281 G299...

Page 34: ...G117 8467 5 276 0 1323 G215 7732 5 157 0 1373 G115 8482 5 157 0 1324 G213 7747 5 276 0 1374 G113 8497 5 276 0 1325 G211 7762 5 157 0 1375 G111 8512 5 157 0 1326 G209 7777 5 276 0 1376 G109 8527 5 276 0 1327 G207 7792 5 157 0 1377 G107 8542 5 157 0 1328 G205 7807 5 276 0 1378 G105 8557 5 276 0 1329 G203 7822 5 157 0 1379 G103 8572 5 157 0 1330 G201 7837 5 276 0 1380 G101 8587 5 276 0 1331 G199 7852...

Page 35: ...rename 1411 G39 9052 5 157 0 Pad No107 CS CSX rename 1412 G37 9067 5 276 0 Pad No109 WR SCL WRX_SCL rename 1413 G35 9082 5 157 0 Pad No110 RD RDX rename 1414 G33 9097 5 276 0 1415 G31 9112 5 157 0 1416 G29 9127 5 276 0 1417 G27 9142 5 157 0 1418 G25 9157 5 276 0 1419 G23 9172 5 157 0 1420 G21 9187 5 276 0 1421 G19 9202 5 157 0 1422 G17 9217 5 276 0 1423 G15 9232 5 157 0 1424 G13 9247 5 276 0 1425 ...

Page 36: ...36 of 181 Bump Arrangement 㪪 㪪㪈䌾㪪㪎㪉㪇䋬㩷 㪞㪈䌾㪞㪋㪊㪉䋬㩷 㪛㪬㪤㪤㪰㪩㪎㪄㪈㪇㪃㩷 㪫㪜㪪㪫㪦㪈㪈㪄㪈㪏㪃㩷 㪭㪞㪣㪛㪤㪰㪈㪄㪋㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㩷 㪠㪆㪦㩷㫇㫀㫅㫊㩷 㩿㪥㫆㪈㩷㵨㩷㪉㪍㪉㪀㩷 㩷 Unit um S 1 500um2 15 15 100 19 90 50 70 Unit um S 4 500um2 20 219 12 12 50 㩿㪥㫆㩷㪉㪍㪊㪄㪈㪋㪊㪋㪀 Figure 3 ...

Page 37: ... 141 VCOML S362 142 VCOML S363 143 VCOML S364 144 VCOML S365 145 GND 146 GND 147 GND 148 GND 149 GND 150 GND 151 GND 152 GND 153 GND 60 154 VGS 155 AGND 156 AGND 157 AGND 158 AGND 159 AGND 160 AGND 161 AGND 162 AGND 163 AGND 1uF 6V B 164 VTEST Open 165 VCIR Open 60 166 VREG1OUT 60 167 VCOMR 200kΩ 168 C11M 169 C11M 170 C11M 171 C11M 1uF 6V B 172 C11M 173 C11P 174 C11P 175 C11P 176 C11P 177 C11P 1uF...

Page 38: ...EF G15 G418 h00E00 h00E01 h00E02 h00E03 h00EEC h00EED h00EEE h00EEF G16 G417 h00F00 h00F01 h00F02 h00F03 h00FEC h00FED h00FEE h00FEF G17 G416 h01000 h01001 h01002 h01003 h010EC h010ED h010EE h010EF G18 G415 h01100 h01101 h01102 h01103 h011EC h011ED h011EE h011EF G19 G414 h01200 h01201 h01202 h01203 h012EC h012ED h012EE h012EF G20 G413 h01300 h01301 h01302 h01303 h013EC h013ED h013EE h013EF G417 G1...

Page 39: ...18 h00E00 h00E01 h00E02 h00E03 h00EEC h00EED h00EEE h00EEF G16 G417 h00F00 h00F01 h00F02 h00F03 h00FEC h00FED h00FEE h00FEF G17 G416 h01000 h01001 h01002 h01003 h010EC h010ED h010EE h010EF G18 G415 h01100 h01101 h01102 h01103 h011EC h011ED h011EE h011EF G19 G414 h01200 h01201 h01202 h01203 h012EC h012ED h012EE h012EF G20 G413 h01300 h01301 h01302 h01303 h013EC h013ED h013EE h013EF G417 G16 h1A000 ...

Page 40: ...w address control 7 γ correction 8 Panel Display Control Normally the data write instructions 5 are used the most frequently The internal GRAM address is updated automatically as data is written to the internal GRAM which in combination with the window address function contributes to minimizing data transfer and thereby lessens the load on the microcomputer The R61509V writes instructions consecut...

Page 41: ...out when this register is read forcibly Driver Output Control R001h R W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R W 1 0 0 0 0 0 SM 0 SS 0 0 0 0 0 0 0 0 Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SS Sets the shift direction of output from the source driver When SS 0 the source driver output shift from S1 to S720 When SS 1 the source driver output shift from S720 ...

Page 42: ...e address counter AC automatically as the data is written to the GRAM The ID 0 bit sets either increment or decrement in horizontal direction updates the address AD 7 0 The ID 1 bit sets either increment or decrement in vertical direction updates the address AD 8 16 The AM bit sets either horizontal or vertical direction in updating RAM address counter automatically when writing data to the intern...

Page 43: ...rring data via 16 bit or 8 bit interface Set DFM in accordance with selected interface and image data format in RAM write operation DFM 0 18bpp R G B 6 6 6 DFM 1 16bpp R G B 5 6 5 TRI Selects the format to transfer data bits via 16 bit or 8 bit interface In 8 bit interface operation TRI 0 16 bit RAM data is transferred in two transfers TRI 1 18 bit RAM data is transferred in three transfers In 16 ...

Page 44: ...l Increment 17 h00000 17 h00000 17 h00000 17 h00000 17 h00000 17 h00000 17 h00000 17 h00000 17 hAFEF 17 hAFEF 17 hAFEF 17 hAFEF 17 hAFEF 17 hAFEF 17 hAFEF 17 hAFEF 17 hAFEF 17 hAFEF 17 hAFEF 17 hAFEF 17 hAFEF 17 hAFEF 17 hAFEF Automatic Address Update ORG 0 AM ID Note When writing data within the window address area with ORG 0 any address within the window address area can be set as the starting p...

Page 45: ...displays partial images BASEE 1 A base image is displayed PTDE Partial display 1 enable bit PTDE 0 Partial display is turned off Only a base image is displayed on the panel PTDE 1 Partial image is displayed Set BASEE 0 to turn off the base image R W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R W 1 0 0 0 PTD E 0 0 0 BAS EE 0 0 0 0 0 0 0 0 Default 0 0 0 0 0 0 0 0 0 0 0 ...

Page 46: ... porch line Number of back porch line 8 h00 Setting inhibited Setting inhibited 8 h01 Setting inhibited Setting inhibited 8 h02 Setting inhibited 2 lines 8 h03 3 lines 3 lines 8 h04 4 lines 4 lines 8 h05 5 lines 5 lines 8 h06 6 lines 6 lines 8 h07 7 lines 7 lines 8 h08 8 lines 8 lines 8 h09 9 lines 9 lines 8 h0A 10 lines 10 lines 8 h0B 11 lines 11 lines 8 h0C 12 lines 12 lines 8 h0D 13 lines 13 li...

Page 47: ...ay Area Note The output timing to the panel is delayed by 2 line period from the synchronous signal VSYNCX input Figure 5 Front and Back Porch Periods Note on Setting BP and FP Set the BP and FP bits as follows in the following operation modes respectively Table 14 BP 2 lines FP 3 lines FP BP 256 lines ...

Page 48: ...0 V0 to V63 Register setting DC0 DC1 1 V63 V0 V0 V63 Register setting DC0 x 1 2 Note The power efficiency improved by halting grayscale amplifiers and slowing down the step up clock frequency can be obtained in non display drive period PTV Sets the VCOM output in non lit display area When PTV 1 frame inversion in non lit display area is selected Table 16 PTV VCOM operation in non lit display drive...

Page 49: ...0 0 0 COL When COL 1 the R61509V enters the eight color display mode RAM data rewrite operation is not required when setting the eight color display mode Set the 8 color mode instruction according to the 8 color mode sequence The electrical potential of liquid crystal drive in 8 color display mode is V0 V63 Selecting frame inversion is recommended to reduce power consumption Table 17 COL Display C...

Page 50: ...lay interface operation mode However switching between the RGB interface operation and the VSYNCX interface operation is prohibited Table 19 Display Interface DM 1 0 Display Interface 2 h0 Internal clock operations 2 h1 RGB interface 2 h2 VSYNC interface 2 h3 Setting inhibited RM Selects the interface for RAM access operation RAM access is possible only via the interface selected by the RM bit Set...

Page 51: ...il 25 2008 page 51 of 181 ENC 2 0 Sets the RAM write cycle via RGB interface Table 21 ENC 2 0 RAM Write Cycle frame periods 3 h0 1 frame 3 h1 2 frames 3 h2 3 frames 3 h3 4 frames 3 h4 5 frames 3 h5 6 frames 3 h6 7 frames 3 h7 8 frames ...

Page 52: ...polarity of DOTCLK pin DPL 0 input data on the rising edge of DOTCLK DPL 1 input data on the falling edge of DOTCLK EPL Sets the signal polarity of ENABLE pin EPL 0 writes data DB17 0 when ENABLE 0 and disables data write operation when ENABLE 1 EPL 1 writes data DB17 0 when ENABLE 1 and disables data write operation when ENABLE 0 HSPL Sets the signal polarity of HSYNCX pin HSPL 0 low active HSPL ...

Page 53: ...ion ratio of the internal clock frequency The R61509V s internal operation is synchronized with the frequency divided internal clock which is set according to the division ratio determined by DIVI 1 0 setting The frame frequency can be changed by setting RTNI and DIVI bits When changing the number of lines to drive the LCD panel adjust the frame frequency too For details see Frame Frequency Adjust...

Page 54: ...25 2008 page 54 of 181 Frame Frequency Calculation fosc Frame frequency Clocks per line x division ratio x line BP FP Hz fosc RC oscillation frequency Line Number of lines to drive the LCD NL bits Division ratio DIVI Clocks per line RTNI ...

Page 55: ... 0 internal clock see note 3 h4 4 internal clock see note 3 h1 1 3 h5 5 3 h2 2 3 h6 6 3 h3 3 3 h7 7 Note The internal clock is the frequency divided clock which is set by DIVI 1 0 bits SDTI 2 0 Sets the source output delay period from the reference point For the relationships between gate interface signals see Liquid Crystal Panel Interface Timing Table 25 SDTI 2 0 Source output delay period 3 h0 ...

Page 56: ...eriod The VCOM equalize operation is executed from VCOM alternating point defined by MCPI 2 0 for the period defined by VEQWI 2 0 This function is disabled when RGB interface is selected Table 26 VEQWI 2 0 VCOM Equalize period 3 h0 0 clocks 3 h1 1 clock 3 h2 2 clocks 3 h3 3 clocks 3 h4 4 clocks 3 h5 5 clocks 3 h6 6 clocks 3 h7 7 clocks Note The clock is the frequency divided clock which is set by ...

Page 57: ...ed only when the R61509V executes display operation in synchronization with internal clock Table 27 SEQWI 2 0 Source Equalize Period 3 h0 0 clocks 3 h1 1 clock 3 h2 2 clocks 3 h3 3 clocks 3 h4 4 clocks 3 h5 5 clocks 3 h6 6 clocks 3 h7 7 clocks Note The clock is the frequency divided clock which is set by DIVI 1 0 bits ...

Page 58: ...interface operation Table 28 MCPI 2 0 VCOM alternating timing 3 h0 Setting inhibited 3 h1 1 clock 3 h2 2 clocks 3 h3 3 clocks 3 h4 4 clocks 3 h5 5 clocks 3 h6 6 clocks 3 h7 7 clocks Note The clock is the frequency divided clock which is set by DIVI 1 0 bits R W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MC PI 2 MC PI 1 MC PI 0 Default 0...

Page 59: ...frequency is the closest to internal oscillation clock frequency 678KHz For details see Setting Example of Display Control Clock in RGB Interface Operation Table 29 Table 30 PCDIVH 2 0 Number of DOTCLK in High period PCDIVL 2 0 Number of DOTCLK in Low period 3 h0 Setting inhibited 3 h0 Setting inhibited 3 h1 1 clock 3 h1 1 clock 3 h2 2 clocks 3 h2 2 clocks 3 h3 3 clocks 3 h3 3 clocks 3 h4 4 clocks...

Page 60: ... enabled while the R61509V s display operation is synchronized with RGB interface signals Table 31 Division Ratio of DOTCLK RGB interface operation DIVE 1 0 Division ratio 2 h0 1 1 2 h1 1 2 2 h2 1 4 2 h3 1 8 Note Clock frequency for internal operation DOTCLK DIVE x PCDIVL PCDIVH For details see R014h R W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R W 1 0 0 0 0 0 0 DIV...

Page 61: ... 6 h26 38 clocks 6 h07 Setting inhibited 6 h27 39 clocks 6 h08 Setting inhibited 6 h28 40 clocks 6 h09 Setting inhibited 6 h29 41 clocks 6 h0A Setting inhibited 6 h2A 42 clocks 6 h0B Setting inhibited 6 h2B 43 clocks 6 h0C Setting inhibited 6 h2C 44 clocks 6 h0D Setting inhibited 6 h2D 45 clocks 6 h0E Setting inhibited 6 h2E 46 clocks 6 h0F Setting inhibited 6 h2F 47 clocks 6 h10 16 clocks 6 h30 4...

Page 62: ...en the R61509V s display operation is synchronized with DOTCLK DM 2 h1 For the relationships between signals see Liquid Crystal Panel Interface Timing Table 34 SDTE 2 0 Source output delay period 3 h0 0 clocks 3 h1 1 clock 3 h2 2 clocks 3 h3 3 clocks 3 h4 4 clocks 3 h5 5 clocks 3 h6 6 clocks 3 h7 7 clocks Notes 1 The number of clocks in the table setting is measured from the reference point 2 1 cl...

Page 63: ...h3 3 clocks 3 h7 7 clocks Notes 1 1 clock Number of data transfer pixel x DIVE division ratio x PCDIVL PCDIVH DOTCLK 2 The number of clocks is measured from the reference point The reference point is the alternating position of VCOM which is set by SDTE bits 㪭㪚㪦㪤㩷㫆㫌㫋㫇㫌㫋 㩷 㩷 㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴 㪞㪥㪛㩷㫃㪼㫍㪼㫃㩷 㪭㪜㪨㪮㪠㪲㪉㪑㪇㪴 㪭㪚㪠㩷㫃㪼㫍㪼㫃㩷 㩷 1 VEQW 2 0 0h 㪭㪚㪦㪤㩷㫆㫌㫋㫇㫌㫋 2 VEQWI 2 0 0h Figure 7 R W RS IB15 IB14 IB13 IB12 IB...

Page 64: ...s enabled when the R61509V executes display operation via RGB interface Table 36 SEQWE 2 0 Source Equalize Period 3 h0 0 clocks 3 h1 1 clock 3 h2 2 clocks 3 h3 3 clocks 3 h4 4 clocks 3 h5 5 clocks 3 h6 6 clocks 3 h7 7 clocks Note 1 clock number of data transfer pixel x DIVE Division ratio x PCDIVL PCDIVH DOTCLK ...

Page 65: ...OM alternating point 3 h0 Setting inhibited 3 h1 1 clock 3 h2 2 clocks 3 h3 3 clocks 3 h4 4 clocks 3 h5 5 clocks 3 h6 6 clocks 3 h7 7 clocks Note 1 clock number of data transfer pixel x DIVE Division ratio x PCDIVL PCDIVH DOTCLK R W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 MC PE 2 MC PE 1 MC PE 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 66: ...position of frame synchronous signal frame marker A pulse FMARK is output by starting from back porch during a 1H period when FMP 8 0 9 h000 high active amplitude IOVCC1 GND FMP 8 0 is used as a trigger signal for write operation in synchronization with frame Setting range 9 h000 FMP BP NL FP For details see FMARK Interface Table 39 R W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 ...

Page 67: ...e better the drivability of the LCD but it also increases the current consumption Adjust the constant current taking the trade off between the display quality and the current consumption into account In no display period set AP 1 0 2 h0 to halt operational amplifiers and step up circuits to reduce power consumption Table 40 Constant Current in Operational Amplifiers AP 1 0 Electricity in LCD drive...

Page 68: ...Step Up Circuits BT 2 0 DDVDH VCL VGH VGL 3 h0 Setting inhibited 3 h1 VCI1 DDVDH x 2 x 5 3 h2 DDVDH x 2 x 4 3 h3 VCI1 x2 x 2 VCI1 x 1 DDVDH x 3 x 6 VCI1 DDVDH x 3 3 h4 Setting inhibited 3 h5 VCI1 DDVDH x 2 x 5 3 h6 DDVDH x 2 x 4 3 h7 VCI1 x2 x 2 VCI1 x 1 VCI1 DDVDH x 2 x 5 VCI1 DDVDH x 3 Notes 1 The factors in the brackets show the step up factors from VCI1 2 Make sure DDVDH max 6 0V VGH max 18 0V...

Page 69: ...ncy 8 3 h4 Line frequency 16 3 h5 Setting inhibited 3 h6 Setting inhibited 3 h7 Setting inhibited R W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R W 1 0 0 0 0 0 DC1 2 DC1 1 DC1 0 0 DC0 2 DC0 1 DC0 0 0 VC 2 VC 1 VC 0 Default 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 1 fosc Internal clock frequency Number of clock per line RTN 4 0 RTNI or RTNE Division ratio DIV 1 0 DIVI or DIVE N ...

Page 70: ...tory The step up frequencies synchronize with display operation Clock count is reset at the beginning of 1H period DC0 2 0 Step up Circuit 1 Step up frequency fDCDC1 3 h0 Step up circuit 1 halts 3 h1 Setting inhibited 3 h2 Setting inhibited 3 h3 Setting inhibited 3 h4 FOSC 8 3 h5 FOSC 16 3 h6 FOSC 32 3 h7 Setting inhibited fosc Internal clock frequency Division ratio DIV 1 0 DIVI or DIVE N DC1 2 0...

Page 71: ... VC 2 0 Sets VCI voltage level VC 2 0 VCI1 voltage Reference voltage for step up operation 3 h0 Setting inhibited 3 h1 0 94 x VCILVL 3 h2 0 89 x VCILVL 3 h3 Setting inhibited 3 h4 Setting inhibited 3 h5 0 76 x VCILVL 3 h6 Setting inhibited 3 h7 1 00 x VCILVL ...

Page 72: ...08 NL 7 h6B front porch back porch 8 lines the number of lines to drive the LCD 432 lines Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference Reference point point point point point ...

Page 73: ...ial setting 0 VCOMR externally supplied 1 Internal electronic volume VRH 3 0 Sets the factor to generate VREG1OUT Table 45 Note Write VC and VRH bits so that VREG1OUT DDVDH 0 5V R W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 VRH 4 VRH 3 VRH 2 VRH 1 VRH 0 0 0 VCM R 1 0 PSON PON 0 0 0 0 R W 1 R W R W R W R W R W R W R W W W Default 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 VRH 4 ...

Page 74: ... VREG1OUT x 0 82 5 h16 VREG1OUT x 1 14 5 h7 VREG1OUT x 0 84 5 h17 VREG1OUT x 1 16 5 h8 VREG1OUT x 0 86 5 h18 VREG1OUT x 1 18 5 h9 VREG1OUT x 0 88 5 h19 VREG1OUT x 1 20 5 hA VREG1OUT x 0 90 5 h1A VREG1OUT x 1 22 5 hB VREG1OUT x 0 92 5 h1B VREG1OUT x 1 24 5 hC VREG1OUT x 0 94 5 h1C VREG1OUT x 1 26 5 hD VREG1OUT x 0 96 5 h1D VREG1OUT x 1 28 5 hE VREG1OUT x 0 98 5 h1E VREG1OUT x 1 30 5 hF VREG1OUT x 1...

Page 75: ...ion RM 0 the address AD16 0 is set when executing the instruction Table 47 GRAM Address setting range AD 16 0 GRAM Data Setting 17 h00000 17 h000EF Bitmap data on the first line 17 h00100 17 h001EF Bitmap data on the second line 17 h00200 17 h002EF Bitmap data on the third line 17 h00300 17 h003EF Bitmap data on the fourth line 17 h00400 17 h004EF Bitmap data on the fifth line 17 h1AC00 17 h1ACEF ...

Page 76: ...ally in write operation The format to develop data into 18 bits is different in different interface operation The GRAM data represents the grayscale level The R61509V automatically updates the address according to AM and ID 1 0 settings as it writes data in the GRAM The DFM bit sets the format to develop 16 bit data into the 18 bit data in 16 bit or 8 bit interface operation Note When writing data...

Page 77: ...data bus is invalid Valid data is sent to the data bus when the R61509V reads out the second and subsequent words When either 8 bit or 16 bit interface is selected the LSBs of R and B dot data are not read out Note This register is disabled in RGB interface operation First word Second word First word Second word Set ID AM HSA HEA VSA and VEA bits Set address N Dummy read invalid data to DB17 0 Fro...

Page 78: ...0 8 hFF Default VCM 6 0 Used to control VCOMH To use NVM data to adjust VCOMH specify the VCOMH level using VCM 6 0 write the same value to the NVM data write register NVDAT 14 8 R6F1h and then write the data to NVM NVM data is loaded to VCM 6 0 when power on reset when shutdown mode is exited or when CALB 1 is written When NVM data write is not executed VCM 6 0 7 h7F Default R W RS IB15 IB14 IB13...

Page 79: ...8 VREG1OUT x 0 844 7 h19 VREG1OUT x 0 592 7 h59 VREG1OUT x 0 848 7 h1A VREG1OUT x 0 596 7 h5A VREG1OUT x 0 852 7 h1B VREG1OUT x 0 600 7 h5B VREG1OUT x 0 856 7 h1C VREG1OUT x 0 604 7 h5C VREG1OUT x 0 860 7 h1D VREG1OUT x 0 608 7 h5D VREG1OUT x 0 864 7 h1E VREG1OUT x 0 612 7 h5E VREG1OUT x 0 868 7 h1F VREG1OUT x 0 616 7 h5F VREG1OUT x 0 872 7 h20 VREG1OUT x 0 620 7 h60 VREG1OUT x 0 876 7 h21 VREG1OU...

Page 80: ...7 h3B VREG1OUT x 0 728 7 h7B VREG1OUT x 0 984 7 h3C VREG1OUT x 0 732 7 h7C VREG1OUT x 0 988 7 h3D VREG1OUT x 0 736 7 h7D VREG1OUT x 0 992 7 h3E VREG1OUT x 0 740 7 h7E VREG1OUT x 0 996 7 h3F VREG1OUT x 0 744 7 h7F VREG1OUT x 1 000 Notes 1 Make sure the VCOMH level is between 3 0V to DDVDH 0 5 V 2 The above setting is enabled when internal electronic volume is selected for setting the VCOMH level ...

Page 81: ...ite data Set VSA 8 0 and VEA 8 0 before starting RAM write operation In setting make sure that 9 h000 VSA VEA 9 h1AF 17 h000 00 17 h1AF EF Notes 1 Make an window address area within the GRAM address area 2 Set an address within the window address area Window address area Window address area setting range 8 h00 HSA HEA 8 hEF HEA HSA 8 h4 9 h000 VSA VEA 9 h1AF HEA HSA VSA VEA Figure 9 GRAM Address M...

Page 82: ... PR0 P07 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 304 W 1 0 0 PI0 P3 1 PI0 P3 0 0 0 PI0 P2 1 PI0 P2 0 0 0 PI0 P1 1 PI0 P1 0 0 0 PI0 P0 1 PI0 P0 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 305 W 1 0 0 0 PR0 N01 4 PR0 N01 3 PR0 N01 2 PR0 N01 1 PR0 N01 0 0 0 0 PR0 N00 4 PR0 N00 3 PR0 N00 2 PR0 N00 1 PR0 N00 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 306 W 1 PR0 N04 3 PR0 N04 2 PR0 N04 1 PR0 N04 0...

Page 83: ...erence level for negative polarity output R4 PR0P05 3 0 PR0N05 3 0 Adjusts reference level for positive polarity output R5 Adjusts reference level for negative polarity output R5 PR0P06 4 0 PR0N06 4 0 Adjusts reference level for positive polarity output R6 Adjusts reference level for negative polarity output R6 PR0P07 4 0 PR0N07 4 0 Adjusts reference level for positive polarity output R7 Adjusts r...

Page 84: ...ally white Table 49 Non lit display area NDL Positive Negative 0 V63 V0 1 V0 V63 Note NDL setting is enabled in non lit display area in partial display operation VLE Vertical scroll display enable bit When VLE 1 the R61509V starts displaying the base image from the line of the physical display determined by VL 8 0 bits VL 8 0 sets the amount of scrolling which is the number of lines to shift the s...

Page 85: ...play Area REV GRAM Data Positive Polarity Negative Polarity 18 h00000 V63 V0 0 18 h3FFFFF V0 V63 18 h00000 V0 V63 1 18 h3FFFFF V63 V0 Note Source output of non lit display area is set by NDL bit during partial display mode VL 8 0 Sets the amount of scrolling of the base image The base image is scrolled in vertical direction and displayed from the line which is determined by VL Table 52 VL 8 0 Line...

Page 86: ...ines 6 h09 80 lines 6 h25 304 lines 6 h0A 88 lines 6 h26 312 lines 6 h0B 96 lines 6 h27 320 lines 6 h0C 104 lines 6 h28 328 lines 6 h0D 112 lines 6 h29 336 lines 6 h0E 120 lines 6 h2A 344 lines 6 h0F 128 lines 6 h2B 352 lines 6 h10 136 lines 6 h2C 360 lines 6 h11 144 lines 6 h2D 368 lines 6 h12 152 lines 6 h2E 376 lines 6 h13 160 lines 6 h2F 384 lines 6 h14 168 lines 6 h30 392 lines 6 h15 176 line...

Page 87: ...G N 200 G401 G 2N 32 6 h1A G209 G N 208 G417 G 2N 16 6 h1B G217 G N 216 G2 G 2N 431 6 h1C G225 G N 224 G18 G 2N 415 6 h1D G233 G N 232 G34 G 2N 399 6 h1E G241 G N 240 G50 G 2N 383 6 h1F G249 G N 248 G66 G 2N 367 6 h20 G257 G N 256 G82 G 2N 351 6 h21 G265 G N 264 G98 G 2N 335 6 h22 G273 G N 272 G114 G 2N 319 6 h23 G281 G N 280 G130 G 2N 303 6 h24 G289 G N 288 G146 G 2N 287 6 h25 G297 G N 296 G162 G...

Page 88: ...addresses of the RAM area respectively for the partial image 1 In setting make sure that PTSA PTEA R W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R 500h R W 1 0 0 0 0 0 0 0 PTD P 8 PTD P 7 PTD P 6 PTD P 5 PTD P 4 PTD P 3 PTD P 2 PTD P 1 PTD P 0 Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R 501h R W 1 0 0 0 0 0 0 0 PTS A 8 PTS A 7 PTS A 6 PTS A 5 PTS A 4 PTS A 3 PTS A 2 PT...

Page 89: ...itialized When TRSR 0 initialization of test registers halts Instruction Write R600h TRSR 1 R600h TRSR 0 㩷 Instruction Write Test registers are initialized 0 1ms or longer Figure 10 R W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R W 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TRSR Default value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ...

Page 90: ... start write operation using EOP bit NVM data written to NVDAT 14 8 are loaded to R280h VCM 6 0 when power on reset is executed or CALB 1 NVM data written to NVDAT 7 0 are loaded to R280h UID 7 0 when power on reset is executed or CALB 1 See NVM Control for details of write operation and required settings R W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 IB8 IB7 IB6 IB5 IB4 IB3 IB2 IB1 IB0 R 6F0h R W 1 0 0...

Page 91: ...㪴㩷 㪥㪭㩷 㪛㪘㪫㩷 㪲㪈㪴㩷 㪥㪭 㪛㪘㪫 㪲㪇㪴 㸣㩷㸣㩷 㸣㩷 㸣㩷 㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣㩷 㸣㩷 㸣㩷 㸣 㪥㪭㪤㩷 㪲㪈㪌㪴㩷 㪥㪭㪤㩷 㪲㪈㪋㪴㩷 㪥㪭㪤㩷 㪲㪈㪊㪴㩷 㪥㪭㪤㩷 㪲㪈㪉㪴㩷 㪥㪭㪤 㪲㪈㪈㪴 㪥㪭㪤 㪲㪈㪇㪴 㪥㪭㪤 㪲㪐㪴 㪥㪭㪤 㪲㪏㪴 㪥㪭㪤 㪲㪎㪴 㪥㪭㪤 㪲㪍㪴 㪥㪭㪤 㪲㪌㪴 㪥㪭㪤 㪲㪋㪴 㪥㪭㪤㩷 㪲㪊㪴㩷 㪥㪭㪤㩷 㪲㪉㪴㩷 㪥㪭㪤㩷 㪲㪈㪴㩷 㪥㪭㪤 㪲㪇㪴 㸣㩷 㸣㩷 㸣㩷 㸣㩷 㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣 㸣㩷 㸣㩷 㸣㩷 㸣 㪈㩷 㪭㪚㪤㩷 㪲㪍㪴㩷 㪭㪚㪤㩷 㪲㪌㪴㩷 㪭㪚㪤㩷 㪲㪋㪴㩷 㪭㪚㪤 㪲㪊㪴 㪭㪚㪤 㪲㪉㪴 㪭㪚㪤 㪲㪈㪴 㪭㪚㪤 㪲㪇㪴 㪬㪠㪛 㪲㪎㪴 㪬㪠㪛 㪲㪍㪴 㪬㪠㪛 㪲㪌㪴 㪬㪠㪛 㪲㪋㪴 㪬㪠㪛㩷 㪲㪊㪴㩷 㪬㪠㪛㩷 㪲㪉㪴㩷 㪬㪠㪛㩷 㪲㪈㪴㩷 㪬㪠㪛 㪲㪇㪴 Figure 11 NV...

Page 92: ...0 HSA 3 0 HSA 2 0 HSA 1 0 HSA 0 0 Window Address 211h Window Horizontal RAM Address End 0 0 0 0 0 0 0 0 HEA 7 1 HEA 6 1 HEA 5 1 HEA 4 0 HEA 3 1 HEA 2 1 HEA 1 1 HEA 0 1 212h Window Vertical RAM Address Start 0 0 0 0 0 0 0 VSA 8 0 VSA 7 0 VSA 6 0 VSA 5 0 VSA 4 0 VSA 3 0 VSA 2 0 VSA 1 0 VSA 0 0 213h Window Vertical RAM Address End 0 0 0 0 0 0 0 VEA 8 1 VEA 7 1 VEA 6 0 VEA 5 1 VEA 4 0 VEA 3 1 VEA 2 1 ...

Page 93: ...bit cell 2 RAM Data initialization The RAM data is not automatically initialized by the RESETX input It must be initialized by software in display off period D1 0 00 3 Output pin initial state see Note 1 LCD driver S1 S720 GND G1 G432 VGL GND 2 VCOM Halt GND output 3 VCOMH VCI 4 VCOML Halt GND output 5 VREG1OUT VGS 6 VCIOUT Hi z 7 DDVDH VCI 8 VGH DDVDH VCI clamp 9 VGL GND 10 VCL GND 11 FMARK Halt ...

Page 94: ...e inside logic regulator and makes a transition to the initial state During this period the state of the interface pins may become unstable For this reason do not enter a RESETX input in shutdown mode 6 When transferring instruction in either two or three transfers via 8 9 16 bit interface make sure to execute data transfer synchronization after reset operation ...

Page 95: ...r ON sequence VSYNC i F sequence 2 DM 10 RM 0 RGB i F 2 sequence 1 DM 01 RM 0 moving picture display RAM access via system i F while displaying moving picture moving picture display 262k color mode 8 color mode Partial display Display color control 262k 8 color display sequence 8 262k color display sequence Exit shut down mode Shut down mode DSTB 1 Deep standby set RGB i F 2 sequence 2 DM 01 RM 1 ...

Page 96: ...lay operation is synchronized with the frame synchronization signal VSYNCX The VSYNC interface enables a moving picture display via system interface by writing the data to the GRAM at faster than the minimum calculated speed in synchronization with the falling edge of VSYNCX In this case there are restrictions in setting the frequency and the method to write data to the internal RAM The R61509V op...

Page 97: ...n These signals must be supplied during the display operation via RGB interface The R61509V transfers display data in units of pixels via DB17 0 pins The display data is stored in the internal RAM The combined use of window address function can minimize the total number of data transfer for moving picture display by transferring only the data to be written in the moving picture RAM area when it is...

Page 98: ... RAM at faster than the calculated minimum speed via system interface from the falling edge of frame synchronous VSYNCX In this case there are restrictions in speed and method of writing RAM data For details see the VSYNC Interface section As external input only VSYNCX signal input is valid in this mode Other input via external display interface becomes disabled The front porch FP back porch BP an...

Page 99: ... Interface IM2 IM1 IM0 Interfacing Mode with Host Processor DB Pins Colors 0 0 0 80 system 18 bit interface DB17 0 262 144 0 0 1 80 system 9 bit interface DB17 9 262 144 0 1 0 80 system 16 bit interface DB17 10 DB8 1 262 144 see Note1 0 1 1 80 system 8 bit interface DB17 10 262 144 see Note2 1 0 Clock synchronous serial interface 65 536 1 1 0 Setting inhibited 1 1 1 Setting inhibited Notes 1 65 53...

Page 100: ...B 4 IB 3 IB 2 IB 1 IB 0 14 6 Instruction code Instruction code Input Instruction Device code Output Figure 15 18 bit Interface Data Format Instruction Write Device Code Read Instruction Read DB 17 DB DB DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 RAM data write 7 16 15 RAM data read GRAM write data Input R5 R4 ...

Page 101: ...B 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 14 6 Instruction Input Instruction code DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 IB 15 IB IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 14 6 Instruction code Device code read Instruction read Device code Output Note Device code cannot be read i...

Page 102: ...nput pins DB 2 DB 1 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 WD 17 WD 16 WD 15 WD 14 WD 13 WD 12 WD 11 WD 10 WD 9 WD 8 WD 7 WD 6 WD 5 WD 4 WD 3 WD 2 WD 1 WD 0 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 RAM data write 2 transfer mode TRI 1 DFM 1 Note Normal display in 262 144 colors 1 pixel First transfer Second transfer GRAM write data RGB ...

Page 103: ...oise and so on the 000H instruction is written four times consecutively to reset the upper and lower counters in order to restart the data transfer from upper 2 16 bits The data transfer synchronization when executed periodically can help the display system recover from runaway Make sure to execute data transfer synchronization after reset operation before transferring instruction WRX RDX RS 16 bi...

Page 104: ... 2 0 001 CSn RDX RD D15 0 CS DB17 9 DB8 0 Figure 22 9 bit Interface DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 IB 15 IB IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 14 Instruction write Input Instruction First transfer Second transfer Instruction code DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB ...

Page 105: ... Figure 24 9 bit Interface Data Format RAM Data Write RAM Data Read Data Transfer Synchronization in 9 bit Bus Interface Operation The R61509V supports data transfer synchronization function to reset the counters for upper and lower 9 bit transfers in 9 bit bus transfer mode When a mismatch occurs in upper and lower data transfers due to noise and so on the 00H instruction is written four times co...

Page 106: ...01 CSn RDX RDX D15 0 DB17 10 DB9 0 Figure 26 8 bit Interface DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 Instruction write Input Instruction Instruction code First transfer Second transfer IB 15 IB 14 IB 13 IB 12 IB 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB...

Page 107: ...3 G2 G1 G0 B5 B4 B3 B2 B1 B0 RAM data write 3 transfer mode TRI 1 DFM 1 First transfer Second transfer Third transfer Note Normal display in 262 144 colors 1 pixel Input GRAM write data Figure 28 8 bit Interface Data Format RAM Data Write R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 RD 17 RD 16 RD 15 RD 14 RD 13 RD 12 RD 11 RD 10 RD 9 RD 8 RD 7 RD 6 RD 5 RD 4 RD 3 RD 2 RD 1 RD 0 DB 17 DB ...

Page 108: ...o noise and so on the 00H instruction is written four times consecutively to reset the upper and lower counters in order to restart the data transfer from upper 8 bits The data transfer synchronization when executed periodically can help the display system recover from runaway Make sure to execute data transfer synchronization after reset operation before transferring instruction DB17 DB10 WRX RDX...

Page 109: ...hth bit of the start byte is R W bit which selects either read or write operation The R61509V receives data when the R W 0 and transfers data when the R W 1 When writing data to the GRAM via serial interface the data is written to the GRAM after it is transferred in two bytes The R61509V writes data to the GRAM in units of 18 bits by adding the same bits as the MSBs to the LSB of R and B dot data ...

Page 110: ... 11 IB 10 IB 9 IB 8 IB 7 IB 6 IB 5 IB 4 IB 3 IB 2 IB 1 IB 0 RAM data write First transfer upper Second transfer lower D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B5 1 pixel D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 Instruction Instruction code Instruction Input Input GRAM write data Note 65 536 color display in SPI Figure 31 Serial Interface Data Format ...

Page 111: ...ht bits read after start byte input is recognized as the upper byte of instruction Note Valid data is not sent until the R61509V reads five bytes from the GRAM after start byte input The R61509V sends valid data when it reads the sixth and subsequent bytes RAM read Upper 8 bits RAM read Lower 8 bits CSX input SCL input SDI input SDO output Start End CSX input SCL input SDI input CSX input SCL inpu...

Page 112: ...h the VSYNCX signal By writing data to the internal RAM at faster than the calculated minimum speed internal display operation speed margin it becomes possible to rewrite the moving picture data without flickering the display and display a moving picture via system interface The display operation is performed in synchronization with the internal clock signal generated from the internal oscillator ...

Page 113: ...etting the internal clock frequency possible causes of fluctuation must also be taken into consideration In this example the internal clock frequency allows for a margin of 7 for variances and guarantee that display operation is completed within one VSYNCX cycle 2 This example includes variances attributed to LSI fabrication process and room temperature Other possible causes of variances such as d...

Page 114: ... gives a theoretical value Possible causes of variances of internal oscillator should be taken into consideration Make enough margins in setting RAM write speed for VSYNC interface operation 2 The above example shows the values when writing over the full screen Extra margin will be created if the moving picture display area is smaller than that 0 16 67 60 Hz Display operation 16 Back porch 14 line...

Page 115: ...ster to R202h Display operation in synchronization with internal clocks VSYNC interface operation Display operation in synchronization with VSYNCX Display operation in synchronization with VSYNCX Internal clock operation Set internal clock operation mode DM1 0 00 and RM 0 Display operation in synchronization with internal clocks Note Continue VSYNC interface signals at least for one frame period a...

Page 116: ... this operation moving picture display is enabled via system interface by writing data at higher than the internal display operation frequency to a certain degree which guarantees rewriting the moving picture RAM area without causing flicker on the display The data is written in the internal RAM Therefore when moving picture is displayed data is written only to the moving picture display area with...

Page 117: ...tion frequency fosc Hz 678kHz 1 07 1 0 726 kHz variance is taken into account Notes 1 When setting the internal clock frequency possible causes of fluctuation must also be taken into consideration In this example the internal clock frequency allows for a margin of 7 for variances and guarantee that display operation is completed within one FMARK cycle 2 This example includes variances attributed t...

Page 118: ...g FMARK signal The above example of calculation gives a theoretical value Possible causes of variances of internal oscillator should be taken into consideration Make enough margin in setting RAM write speed for this operation FMP bit setting The microcomputer detects FMARK signal outputted at the position defined by FMP bit The R61509V outputs an FMARK pulse when the R61509V is driving the line sp...

Page 119: ...put position 9 h000 0 9 h001 1st line 9 h002 2nd line 9 h1BD 445th line 9 h1BE 446th line 9 h1BF 447 th line 9 h1C0 1FF Setting disabled FMI 2 FMI 1 FMI 0 FMARK Output interval 0 0 0 One frame period 0 0 1 2 frame periods 0 1 1 4 frame periods 1 0 1 6 frame periods Other setting Setting disabled ...

Page 120: ... porch FMARK output position FMP 9 h008 RAM physical line address Base image 0 1st line 1 2nd line 2 3rd line 3 4th line 4 5th line 5 6th line 6 7th line 7 8th line 8 1st line 9 2nd line 10 3rd line 439 432nd line 440 1st line 441 2nd line 442 3rd line 443 4th line 444 5th line 445 6th line 446 7th line 447 8th line AD 16 8 9 h13F AD 16 8 9 h002 AD 16 8 9 h000 AD 16 8 9 h001 Figure 41 ...

Page 121: ... made before and after the display period When RGB interface is used instructions should be transferred via clock synchronous serial interface RGB and 80 system bus interfaces cannot be used simultaneously VSYNCX 1 The front porch period continues until next VSYNCX input is detected 2 Make sure to match the VSYNCX HSYNCX and DOTCLK frequencies to the resolution of liquid crystal panel Moving pictu...

Page 122: ...hronization Hsync 2 10 16 1 DOTCLKCYC Horizontal Back Porch HBP 2 20 24 1 DOTCLKCYC Horizontal Address HAdr 240 1 DOTCLKCYC Horizontal Front Porch HFP 2 10 16 1 DOTCLKCYC Vertical Synchronization Vsync 1 2 4 1 Line Vertical Back Porch VBP 1 2 1 Line Vertical Address VAdr 432 1 Line Vertical Front Porch VFP 3 4 1 Line Note The values of typ are based on the following conditions the panel resolution...

Page 123: ...CLKD frequency and the internal oscillation clock 678kHz is minimized Set PCDIVL to PCDIVH or PCDIVH 1 Make sure number of PCLK frequency number of RTN clocks division ratio of DIV PCDIVH PCDIVL Setting example frame frequency 60Hz Internal clock Internal oscillation clock 678kHz 1 1 Div DIVE 2 0 2 b0 HFP 10 clocks FP 8 h8 BP 8 h8 NL 6B 432 lines Æ 59 35Hz PCLK Hsync 10 clocks HBP 20 clocks HFP 10...

Page 124: ... interface operation is as follows 16 18 Bit RGB Interface Timing 1H 1 clock 1H or more One frame Back porch period Front porch period HLW 1CLK DTST 1CLK VSYNCX HSYNCX DOTCLK ENABLE DB17 0 VSYNCX HSYNCX DOTCLK ENABLE DB17 0 Valid data Figure 45 Note VLW VSYNCX Low period HLW HSYNCX Low period DTST data transfer setup time ...

Page 125: ... RM 0 to enable RAM access via system interface When reverting to the RGB interface operation wait for the read write bus cycle time Then set RM 1 and the index register to R22h to start accessing RAM via RGB interface If there is a conflict between RAM accesses via two interfaces there is no guarantee that the data is written in the RAM The following is an example of rewriting still picture data ...

Page 126: ...6 bit ports while data enable signal ENABLE allows RAM access via RGB interface Instruction bits can be transferred only via system interface HOST PROCESSOR 16 2 Input DB 17 DB 16 DB 15 DB 14 DB 13 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB17 13 11 1 DB12 0 VSYNCX HSYNCX DOTCLK ENABLE R61509V RIM 1 Data format for the16 bit interface RIM 1 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4...

Page 127: ... DB17 0 while data enable signal ENABLE allows RAM access via RGB interface Instruction bits can be transferred only via system interface HOST PROCESSOR R61509V 18 DOTCLK ENABLE DB17 0 DB 17 DB 16 DB 15 DB 14 DB 13 DB 12 DB 11 DB 10 DB 9 DB 8 DB 7 DB 6 DB 5 DB 4 DB 3 DB 2 DB 1 DB 0 RIM 0 Data format for the 18 bit interface RIM 0 Input GRAM write data 1 pixel Note Normal display in 262 144 colors ...

Page 128: ... address counter every frame on the falling edge of VSYNCX Internal Clock Operation to RGB Interface 1 Operation via RGB interface RGB Interface 1 to Internal Clock Operation Internal clock operation AM 0 RAM address set Set DM1 0 01 and RM 1 for RGB interface Write data to RAM via RGB interface Wait one frame period or more Set index register to R202h Display operation in synchronization with int...

Page 129: ...the base image by setting PTDP 3 Set NL to specify the number of lines to drive the liquid crystal panel to display the base image 4 After display ON set display enable bits BASEE PTDE to display respective images Normal display BASEE 1 PTDE 0 Partial display BASEE 0 PTDE 1 5 Changes BASEE PTDE settings when turning on and off the full and partial displays 1 2 In driving the liquid crystal panel t...

Page 130: ...n Figure 50 RAM Address Display Position and Drive Position Restrictions in Setting Display Control Instruction There are restrictions in coordinates setting for display data display position and partial display Screen setting In setting the number of lines to drive the liquid crystal panel make sure that the total number of lines is 432 lines or less NL 432 lines Base image display The base image...

Page 131: ... RAM area Partial image RAM area Partial image Display area LCD panel physical line address RAM line address Display data output order Display screen 0 1st line 1 2nd line 2 3rd line Figure 51 Display RAM Address and Panel Display Position Note This figure shows the relationship between RAM line address and the display position on the panel In the R61509V s internal operation the data is written i...

Page 132: ... display The following is an example of settings for full screen display Table 67 Base image display instruction BASEE 1 NL 5 0 6 h35 PTDE 0 3 NL 432 lines 431 432nd line 1 2 4 5 432 9 h000 BSA 9 h000 BEA 9 h1AF LCD panel physical line address 0 1st line 1 2nd line 2 3rd line RAM line address Display data output order BASE image RAM area Base image Figure 52 Full Screen Display no Partial ...

Page 133: ...ble 68 Base image display instruction BASEE 0 NL 5 0 6 h35 partial image 1 display instruction PTDE 1 PTSA 8 0 9 h000 PTEA 8 0 9 h00F PTDP 8 0 9 h080 3 1 2 4 5 432 9 h1AF PTSA 9 000 PTEA 9 00F PTDP Display data output order RAM line address LCD panel physical line address Partial image display area Base image non lit display Partial image RAM area Base image RAM area NL 432 linrs 0 1st line 1 2nd ...

Page 134: ...aking the data wrap position into account The window address area must be made within the GRAM address map area Also the AD16 0 bits RAM address set register must be set to an address within the window address area Window address area setting range Horizontal direction 8 h00 HSA HEA 8 hEF Vertical direction 9 h000 VSA VEA 9 h1AF RAM Address setting range RAM address HSA AD7 0 HEA VSA AD16 8 VEA Wi...

Page 135: ...main Panel 176 431 429 1 Non bump view 240 Interchanging forward direction GS 0 3 4 G4ЈG3ЈG2ЈG1 G432ЈG431ЈG430ЈG3429 R61509V main Panel 176 2 4 Non bump view 240 432 Interchanging backward direction GS 1 432 430 Scan order Gate line No G4ЈG2ЈG431ЈG429 G3ЈG1 G432ЈG430 R61509V 1 2 216 main Panel Non bump view 240 432 Left right backward direction GS 1 215 217 218 432 431 1 Scan order Gate line No G2...

Page 136: ...stment registers R300 to R309 are disabled and the power supplies to V1 to V62 are halted The R61509V does not require GRAM data rewrite for 8 color display by writing the MSB to the rest in each dot data to display in 8 colors 2 R G B LCD V63 V0 B5 G5 R5 R5 R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B5 B4 B3 B2 B1 B0 B S L B S M LCD driver LCD driver LCD driver Display data GRAM 2 level grayscale control R...

Page 137: ...equation represent the relationship between liquid crystal drive duty and frame frequency The frame frequency can be changed by setting the 1H period adjustment bit RTNI and the operation clock frequency division ratio setting bit DIVI Equation for calculating frame frequency Hz BP FP Line tio DivisionRa line ocks NumberofCl fosc ency FrameFrequ fosc RC oscillation frequency Number of clocks per l...

Page 138: ...etting NL 432 lines BP 14 lines FP 2 lines fosc 678 kHz RTNI 4 0 DIVI 2 h0 DIVI 2 h1 5 h00 5 h0F 5 h10 95 Hz 47 Hz 5 h11 89 Hz 45 Hz 5 h12 84 Hz 42 Hz 5 h13 80 Hz 40 Hz 5 h14 76 Hz 38 Hz 5 h15 72 Hz 36 Hz 5 h16 69 Hz 34 Hz 5 h17 66 Hz 33 Hz 5 h18 63 Hz 32 Hz 5 h19 61 Hz 30 Hz 5 h1A 58 Hz 29 Hz 5 h1B 56 Hz 28 Hz 5 h1C 54 Hz 27 Hz 5 h1D 52 Hz 26 Hz 5 h1E 50 Hz 25 Hz 5 h1F 49 Hz 24 Hz ...

Page 139: ...ination with 8 color display mode Check the display quality when using low power consumption functions G41 G60 Non lit display area Non lit display area Partial image 20 lines Number of lines to drive LCD NL 6 h35 432 lines Base image display enable BASEE 0 Partial image display RAM area PTSA PTEA 9 h000 9 h013 Partial image display position PTDP 9 h028 Partial image display enable PTDE 1 Figure 5...

Page 140: ... signals in internal operation and RGB interface operations are as follows Internal Clock Operation FMARK G1 G2 S 3n 1 VCOM 1H FMP BP 1 NOWI 432nd line G432 R G B S 3n 2 S 3n 3 n 0to239 R G B R G B SDTI SDTI reference point reference point reference point reference point reference point reference point reference point reference point One Frame First line Second line Figure 58 ...

Page 141: ... 2 3 BP 1H 5DOTCLK FP One frame VSYNCX HSYNCX DOTCLK S 3n 1 ENABLE DB FMARK G1 G2 G3 RGB 432 1 G432 VCOM FMP BP 1 1H NOWE S 3n 2 S 3n 3 n 0 to 239 RGB RGB SDTE Note Transfer RGB data in one transfer via 16 bit port See note Reference point Reference point FIrst line Second line Third line 432nd line Figure 59 ...

Page 142: ...age level the difference between VREG1OUT and VGS is evenly divided into 8 grayscale reference voltages V0 V1 V8 V20 V43 V55 V62 and V63 Other 56 grayscale voltages are generated by setting the level at a certain interval between the reference voltages For grayscale voltage see Grayscale Voltage Calculation Formula 㪭㪇 㪭㪈 㪭㪏 㪭㪉㪇 㪭㪋㪊 㪭㪌㪌 㪭㪍㪉 㪭㪍㪊 Linear interpolation Interpolation adjustment Interpol...

Page 143: ...tment registers Reference level adjustment registers Table 70 Reference level adjustment registers Gamma Control Resistor Positive polarity Negative polarity R0 PR0P00 4 0 PR0N00 4 0 R1 PR0P01 4 0 PR0N01 4 0 R2 PR0P02 4 0 PR0N02 4 0 R3 PR0P03 3 0 PR0N03 3 0 R4 PR0P04 3 0 PR0N04 3 0 R5 PR0P05 3 0 PR0N05 3 0 R6 PR0P06 4 0 PR0N06 4 0 R7 PR0P07 4 0 PR0N07 4 0 R8 PR0P08 4 0 PR0N08 4 0 ...

Page 144: ... 5 h02 2R 4 h2 6R R0 PR0 00 4 0 5 h1F 31R R5 PR0 05 3 0 4 hF 19R 5 h00 1R 5 h00 2R 5 h01 2R 5 h01 3R 5 h02 3R 5 h02 4R R1 PR0 01 4 0 5 h1F 32R R6 PR0 06 4 0 5 h1F 33R 5 h00 2R 5 h00 1R 5 h01 3R 5 h01 2R 5 h02 4R 5 h02 3R R2 PR0 02 4 0 5 h1F 33R R7 PR0 07 4 0 5 h1F 32R 4 h0 4R 5 h00 2R 4 h1 5R 5 h01 3R 4 h2 6R 5 h02 4R R3 PR0 03 3 0 4 hF 19R R8 PR0 08 4 0 5 h1F 33R 4 h0 8R 4 h1 9R 4 h2 10R R4 PR0 0...

Page 145: ... factor for V2 to V7 See Grayscale Voltage Calculation Formula for IPV level PI0 0 1 0 PI0 1 1 0 IPV2 IPV3 IPV4 IPV5 IPV6 IPV7 2 h0 81 67 52 39 26 13 2 h1 78 61 43 33 22 11 2 h2 73 52 31 23 15 8 2 h0 2 h3 72 50 28 21 14 7 2 h0 80 68 56 42 28 14 2 h1 76 62 48 36 24 12 2 h2 70 52 35 26 17 9 2 h1 2 h3 69 50 31 23 16 8 2 h0 78 70 61 46 30 15 2 h1 74 63 53 39 26 13 2 h2 66 53 39 29 20 10 2 h2 2 h3 64 5...

Page 146: ... 2 h1 89 78 67 57 39 22 2 h2 92 85 77 69 48 27 2 h0 2 h3 93 86 79 72 50 28 2 h0 86 72 58 44 32 20 2 h1 88 76 64 52 38 24 2 h2 91 83 74 65 48 30 2 h1 2 h3 92 84 77 69 50 31 2 h0 85 70 54 39 30 22 2 h1 87 74 61 47 37 26 2 h2 90 80 71 61 47 34 2 h2 2 h3 91 82 73 64 50 36 2 h0 84 69 53 38 30 22 2 h1 86 73 59 46 36 27 2 h2 90 80 69 59 47 35 2 h3 2 h3 91 81 72 63 50 37 Note indicates P N ...

Page 147: ...V20 V8 V20 x 7 12 V45 V55 V43 V55 x 10 12 V14 V20 V8 V20 x 6 12 V46 V55 V43 V55 x 9 12 V15 V20 V8 V20 x 5 12 V47 V55 V43 V55 x 8 12 V16 V20 V8 V20 x 4 12 V48 V55 V43 V55 x 7 12 V17 V20 V8 V20 x 3 12 V49 V55 V43 V55 x 6 12 V18 V20 V8 V20 x 2 12 V50 V55 V43 V55 x 5 12 V19 V20 V8 V20 x 1 12 V51 V55 V43 V55 x 4 12 V20 ΔV x Σ R4 R8 SUMR V52 V55 V43 V55 x 3 12 V21 V43 V20 V43 x 22 23 V53 V55 V43 V55 x 2...

Page 148: ... V22 V22 V41 6 h0A V10 V53 V53 V10 6 h2A V42 V21 V21 V42 6 h0B V11 V52 V52 V11 6 h2B V43 V20 V20 V43 6 h0C V12 V51 V51 V12 6 h2C V44 V19 V19 V44 6 h0D V13 V50 V50 V13 6 h2D V45 V18 V18 V45 6 h0E V14 V49 V49 V14 6 h2E V46 V17 V17 V46 6 h0F V15 V48 V48 V15 6 h2F V47 V16 V16 V47 6 h10 V16 V47 V47 V16 6 h30 V48 V15 V15 V48 6 h11 V17 V46 V46 V17 6 h31 V49 V14 V14 V49 6 h12 V18 V45 V45 V18 6 h32 V50 V13...

Page 149: ...be adjusted 㓏 㔚 ᚑ VGL DDVDH C13M C13P C21M C21P C22M C22P C11M C11P VCI1 VCIOUT ജ ౝㇱၮḰ 㔚 ᚑ VCOM ജ VCOMR VREG1 ࠡࡘ VGH ࠬ ࠗࡃ S1 720 VCOM ࡌ ᢛ VCILVL VDD C12M C12P 㧝 㧞 1 2 3 4 5 6 G1 432 VGH ࠥ ࠗࡃ VGL VCC GND VCI AGND IOVCC GND VCL VCILVL VCOM VCOMH 16 17 VCOML R61509V See note 2 See note 1 VREG1OUT 7 8 9 10 11 15 12 13 14 Figure 61 Notes 1 The wiring resistances between the schottky diode and GND VGL m...

Page 150: ...C22P C11M C11P VCI1 VCIOUT ജ ౝㇱၮḰ 㔚 ᚑ VCOM ജ VCOMR VREG1 ࠡࡘ ࠬ ࠗࡃ S1 720 VCC GND VCI AGND VCOM ࡌ ᢛ VCILVL VDD C12M C12P 㧝 㧞 2 G1 432 VGH ࠥ ࠗࡃ VGL VCI IOVCC GND VCILVL VCOM VCOMH 16 17 VCOML VGL VGH VCL R61509V 11 See note 3 4 5 6 7 1 See note 2 8 9 10 12 13 14 See note 1 15 VREG1OUT Figure 62 Notes 1 The wiring resistances between the schottky diode and GND VGL must be 5Ω or less 2 The wiring resis...

Page 151: ... 6 V 1 VREG1OUT 3 VCI1 4 C11P C11M 5 C12P C12M 7 C13P C13M 14 VCL 16 VCOMH 17 VCOML 10 V 6 DDVDH 8 C21P C21M 9 C22P C22M 1µF B characteristics 25 V 10 VGH 12 VGL Table 78 Schottky Diode Specification Pin Connection VF 0 38 V 20 mA 25 C VR 25 V Recommended diode HS 226 13 GND VGL 11 DDVDH VGH Table 79 Variable Resistor Specification Pin Connection 200 kΩ 2 VCOMR Table 80 Internal Logic Power Supply...

Page 152: ...5 3 3V VCILVL 2 5 3 3V Figure 63 Notes 1 The DDVDH VGH VGL and VCL output voltages will become lower than their theoretical levels ideal voltages due to current consumption at each output level Make sure that output voltage level in operation maintains the following relationships DDVDH VREG1OUT 0 5V VCOML VCL 0 5V Also make sure VGH VGL 28V VCI VCL 6V When the alternating cycle of VCOM is high e g...

Page 153: ...Target Spec Rev 0 11 April 25 2008 page 153 of 181 Liquid Crystal Application Voltage Waveform and Electrical Potential VCOM Gn panel interface output Sn source driver output VGH VREG1OUT VCOMH VCOML Figure 64 ...

Page 154: ...㪴 㪭㪚㪤 㪲㪇㪴 㪬㪠㪛 㪲㪊㪴 㪬㪠㪛 㪲㪉㪴 㪬㪠㪛㩷 㪲㪇㪴 㪥㪭㪛㪘㪫㩷 㪲㪈㪌㪴 㪥㪭㪛㪘㪫㩷 㪲㪈㪋㪴 㪥㪭㪛㪘㪫㩷 㪲㪈㪊㪴 㪥㪭㪛㪘㪫 㪲㪈㪉㪴 㪥㪭㪛㪘㪫㩷 㪲㪈㪈㪴 㪥㪭㪛㪘㪫㩷 㪲㪈㪇㪴 㪥㪭㪛㪘㪫 㪲㪐㪴 㪥㪭㪛㪘㪫 㪲㪏㪴 㪥㪭㪛㪘㪫 㪲㪎㪴 㪥㪭㪛㪘㪫 㪲㪍㪴 㪥㪭㪛㪘㪫 㪲㪌㪴 㪥㪭㪛㪘㪫 㪲㪋㪴 㪥㪭㪛㪘㪫 㪲㪊㪴 㪥㪭㪛㪘㪫 㪲㪉㪴 㪥㪭㪛㪘㪫㩷 㪲㪈㪴 㪥㪭㪛㪘㪫㩷 㪲㪇㪴 㩷 㩷 㩷 㩷 㪬㪠㪛㩷 㪲㪈㪴 㩷 㩷 㪬㪠㪛 㪲㪎㪴 㪬㪠㪛 㪲㪍㪴 㪬㪠㪛 㪲㪋㪴 㪬㪠㪛 㪲㪌㪴 Display ON Sequence Complete the VCOMH level adjustment The display on the panel will flicker when the VCOMH level is adjusted internally S...

Page 155: ...re performed Power On reset Exit shutdown mode Data stored in the NVM is retained permanently even if power supply is turned off Table 81 Operation mode Power supply voltage TBD Time TBD Remarks Temperature TBD VPP1 9 2V 0 3V Write VPP3A Open or AGND Write period 150ms 50ms 20 C 30C VPP1 9 2V 0 3V Erase VPP3A 9 2V 0 3V Erase period 10ms 1ms x n time s N 30 total 300ms Verify erase operation at int...

Page 156: ...matically or by setting a command During the following sequence the data written to the NVM is automatically loaded to the internal register NVM data read Wait 1ms or more Except for the shutdown mode Index 6F0h Command 16 h0040 TE 1 b0 CALB 1 b1 EOP 1 0 2 b00 Index 280h VCM 6 0 UID 7 0 Figure 66 NVM Load Register Resetting Sequence ...

Page 157: ...0 CALB 0 EOP 2 h1 R6F0 16 h0090 TE 1 CALB 0 EOP 2 h1 150msr50ms TBD GND VPP1 9 2r0 3V VPP3A VPP3B GND GND VPP1 9 2r0 3V VPP3A GND 6F0h 16 h0040 CALB 1 NVM Write Sequence NVM Load Register Resetting Sequence 1ms or more Power ON reset Transfer synchronization 2msec or more 1msec or more 1msec or more NVM write setting NVM write start NVM write end Power supply VCC VCI IOVCC ON NVM write data set 1u...

Page 158: ...ower supply setting To erase data from NVM set the VC and BT bits as follows to make sure VGL VPP3A 9 5V R100h BT 2 0 3 h6 VGL 10 8V R101h VC 2 0 3 h7 VCI 2 7V Power supply ON sequence Fix VPP3B to GND Erase period 10ms 1ms NVM power supply ON NVM power supply OFF 1ms or more 1ms or more 1ms or more VPP1 9 2 0 3V VPP3A 9 2 0 3V GND GND R6F0h TE 1 EOP 1 0 2 h03 R6F0h TE 0 EOP 1 0 2 h00 R6F2h NVVRF ...

Page 159: ...Liquid crystal power supply ON DCDC ON state Display OFF state OR R102h PSON 1 PON 1 Power ON reset Transfer synchronization 1ms or more Power supply VCC VCI IOVCC ON VCC IOVCC VCI or VCC IOVCC VCI simultaneously Display ON sequence NVM erase sequence Instruction user setting R400h NL 5 0 R008h BP 7 0 FP 7 0 R300h R309h γ control R010h RTNI 4 0 DIVI 1 0 R100h BT 2 0 AP 1 0 R101h VC 2 0 DC0 2 0 DC1...

Page 160: ... 0 PSON 0 㪞㪥㪛 Power Supply OFF Sequence 5 frames or more A Liquid crystal power supply OFF DCDC OFF Display OFF state B Liquid crystal power supply ON DCDC ON state Display OFF state VCI IOVCC VCC or VCC IOVCC VCI simultaneously Power supply VCC VCI IOVCC OFF IOVCC VCC VCI Figure 70 ...

Page 161: ...ve to change the order please follow the following note Note Internal operation of the R61509V is unstable until VCC rises If IOVCC rose before VCC rises the R61509V may be in output status In this case do not send or receive any data before power supply is completed Changing order of voltage input will not cause troubles such as latchup or destruction of the LSI ...

Page 162: ... crystal power supply ON DCD ON state Display ON state B Liquid crystal power supply ON DCDC ON state Display OFF state C Liquid crystal power supply ON DCD ON state Display ON state Display ON Display OFF R007h BASEE 1 R007h BASEE 0 Transfer synchronization Transfer synchronization RS 0 DB 16 h0000 RS 0 DB 16 h0000 RS 0 DB 16 h0000 RS 0 DB 16 h0000 RS 0 DB 16 h0000 RS 0 DB 16 h0000 RS 0 DB 16 h00...

Page 163: ... Sequence Exit shutdown mode by inputting CSX Low 18 16 9 8 bit interface operation VDD startup Oscillation startup period Exit shutdown mode Input CSX Low 6 times Initialize the R61509V Automatic NVM data load 1ms or more 0 3ms or more Display OFF sequence Display ON sequence RAM data setting Data and RS Don t care Refresh sequence 2 High High Low or High Don t care Don t care Don t care Don t ca...

Page 164: ...d inputs of Index Write High Low 16 h0000 16 h0000 16 h0000 16 h0000 16 h0000 16 h0000 CSX WRX RDX RS Data 1ms or more 0 3ms or more RAM data setting Display ON sequence Display OFF sequence VDD startup Oscillation startup period Initialize the R61509V Refresh sequence 2 Set shutdown mode R100h DSTB 1 Exit shutdown mode 1 2 3 4 5 6 Wait 1ms User setting NL BP FP γ control RTNI DIVI and others Exec...

Page 165: ...setting Display ON sequence Refresh sequence 2 VDD startup Oscillation startup period Initialize the R61509V Set shutdown mode Display OFF sequence Exit shutdown mode 2 9 8 bit interface operation 0 3ms or more 1ms or more Automatic NVM data load RS Data High Low 00h 00h 00h 00h 00h FFh 00h 00h 00h 00h Upper IW Lower IW Upper IW Upper IW Upper IW Upper IW Lower IW Lower IW Lower IW Lower IW Set sh...

Page 166: ...44 color to 8 color mode Figure 75 Partial Display Setting Partial Display Setting Sequence Partial display setting R500h PTDP 8 0 R501h PTSA 8 0 R502h PTEA 8 0 Partial display Full screen display Set as required Full screen display 8 color display low power consumption settings R007h COL 1 R009h PTS Base image display ON Partial display OFF R007h BASEE 1 PTDE 0 Base image display OFF Partial disp...

Page 167: ... VCL 6 Make sure AGND VGL 7 Make sure VCI VGL 8 The DC AC characteristics of the die and wafer products are guaranteed at 85 Items Symbol Unit Value Note Power supply voltage 1 VCC IOVCC V 0 3 4 6 1 2 Power supply voltage 2 VCI AGND V 0 3 4 6 1 3 Power supply voltage 3 DDVDH AGND V 0 3 6 5 1 4 Power supply voltage 4 AGND VCL V 0 3 4 6 1 Power supply voltage 5 DDVDH VCL V 0 3 9 0 1 5 Power supply v...

Page 168: ...partial display on sub display Iop2 µA fosc 678kHz 64 line partial display IOVCC VCC 3 00V fFLM 40Hz Ta 25 RAM data 18h 000000 see other as well 300 5 6 Current consumption IOVCC IOGND VCC GND Shutdown mode Ishut1 µA IOVCC VCC 3 00V I80 IF Ta 25 0 1 1 0 5 6 Current consumption IOVCC IOGND VCC GND RAM access mode 1 IRAM1 mA IOVCC 2 40V VCC 3 00V tCYCW 110ns Ta 25 I80 8bit I F TRIREG 1 h1 Consecutiv...

Page 169: ...0 PR P01 PR N01 5 h02 PR P02 PR N02 5 h04 PR P03 PR N03 4 h8 PR P04 PR N04 4 hF PR P05 PR N05 4 h8 PR P06 PR N06 5 h04 PR P07 PR N07 5 h02 PR P08 PR N08 5 h04 PIR P0 PIR P1 PIR P2 PIR P3 2 h0 PIR N0 PIR N1 PIR N2 PIR N3 2 h0 0 1 2 No load on the panel 0 8 TBD 5 6 VPP1 AGND IVPP1W mA 30 0 6 NVM current consumption Write VPP3A AGND IVPP3AW mA VPP1 9 2V VPP3A GND Write period 1 0 6 VPP1 AGND IVPP1E m...

Page 170: ...DVDH VGH VGL VCL 1 uF B characteristics Iload2 100 uA No load on the panel 14 4 15 1 VGL V IOVCC VCC VCI 2 80 V fosc 678 kHz Ta 25 VC 3 h1 AP 3 h3 BT 3 h2 DC0 3 h4 div 1 8 DC1 3 h2 div 1 4 COL 0 D 2 h0 C11 C12 C13 C21 C22 1 uF B characteristics DDVDH VGH VGL VCL 1 uF B characteristics Iload3 100 uA No load on the panel 10 0 9 6 Step up output voltage VCLV V IOVCC VCC VCI 2 80 V fosc 678 kHz Ta 25 ...

Page 171: ...ower Supply Voltage VPP1 V 8 9 9 2 9 5 Erase V 0 3 0 0 0 3 Write Power Supply Voltage VPP3A V 9 5 9 2 8 9 Erase Output Voltage Range Ta 40 C 85 C GND AGND 0V Table 87 Item Symbol Unit Min Typ Max Condition Grayscale VCOM reference VREG1O UT V DDVDH 0 5 Source driver V GND 0 2 VREG1OUT VCOMH output VCOMH V VREG1OUT VCOML output VCOML V VCL 0 5 VCOM amplitude V 6 0 Step up output DDVDH V 4 5 6 0 Ste...

Page 172: ...YCW ns Figure A 75 TBD Bus cycle time Read tCYCR ns Figure A 450 TBD Write low level pulse width PWLW ns Figure A 30 TBD Read low level pulse width PWLR ns Figure A 170 TBD Write high level pulse width PWHW ns Figure A 25 TBD Read high level pulse width PWHR ns Figure A 250 TBD Write Read rise fall time tWRr WRf ns Figure A 15 Write RS to CSX WRX ns Figure A 0 TBD Setup time Read RS to CSX RDX tAS...

Page 173: ...hip select hold time tCH ns Figure B 60 TBD Serial input data setup time tSISU ns Figure B 30 TBD Serial input data hold time tSIH ns Figure B 30 TBD Serial output data delay time tSOD ns Figure B 130 TBD Serial output data delay time tSOH ns Figure B 5 TBD RGB Interface Timing Characteristics 18 16 bit RGB interface IOVCC 1 65V 3 30V TBD Table 91 Item Symbol Unit Test condition Min Typ Max VSYNC ...

Page 174: ...ision source output pins Time to reach the target voltage 35mV from VCOM polarity inversion timing R 10kohm C 30pF 25 TBD 10 VCOM output delay time tddv µs VCC IOVCC 2 80V VC 2 0 3 h7 VRH 4 0 5 h1F fosc 678kHz 432 line drive Ta 25 C PR P00 PR N00 5 h00 PR P01 PR N01 5 h02 PR P02 PR N02 5 h04 PR P03 PR N03 4 h8 PR P04 PR N04 4 hF PR P05 PR N05 4 h8 PR P06 PR N06 5 h04 PR P07 PR N07 5 h02 PR P08 PR ...

Page 175: ...e the configurations of input I O and output pins GND Output data IOVCC IOVCC IOVCC IOVCC IOVCC GND GND GND GND PMOS PMOS PMOS PMOS PMOS PMOS PMOS NMOS NMOS NMOS NMOS NMOS NMOS NMOS Input circuit Input circuit Input circuit Pins WR_SCL RDX Pins DB17 DB0 Pins FMARK SDO Pins RESETX IM2 1 IM0_ID VSYNCX HSYNCX DOTCLK ENABLE CSX RDX SDI Input enable CSX Input enable CSX Output circuit three states Outp...

Page 176: ...urce pins for the same display area This value is shown for reference Note 8 The average output voltage dispersion is the variance source output voltage of different chips of the same product The average source output voltage is measured for each chip with same display area Note 9 This applies to internal oscillators when using an internal RC oscillator Note 10 The liquid crystal driver output del...

Page 177: ...VIH VIH VIL VIH RS CSX WRX RDX tAS tAH PWHW PWHR tWRr tCYCW tCYCR VIH VIL DB17 0 VIH tDSW tH VOH VOL DB17 0 VOH PWLW PWLR VIH VIL Note 2 Note 1 Write Data Read Data Note 1 PWLW and PWLR are defined by the overlap period when CSX is Low and either of WRX or RDX is Low Note 2 Unused DB pins must be fixed at IOVCC or GND Note 2 Figure A 80 system Bus Interface ...

Page 178: ...VIL tscr VIL VIH CSX tSCYC VIH SCL VIH tCSU SDI VIH VIH VIL VIH tCH tSCH tSCL tscf VIH tSISU tSISH VOL1 SDO VOH1 VOL1 VOH1 tSOD tSOH Start S End P Input Data Input Data Output Data Output Data Figure B Clock Synchronous Serial Interface Timing Reset Operation VIL VIH RESETX tRES VIL trRES Figure C Reset Timing ...

Page 179: ...tENS tENH VIL VIL VIH VIL DOTCLK VIH PWDL PWDH VIH VIL DB17 0 VIH tPDS tSYNCS tCYCD trgbf trgbr trgbf trgbr Write Data Figure D RGB Interface Timing LCD Driver and VCOM Output Characteristics VCOM S1 720 tDDs tDDv Target voltage r35mV Target voltage r35mV Target voltage r35mV Target voltage r35mV Figure E LCD Driver and VCOM Output Timing ...

Page 180: ...a Renesas sales office beforehand Renesas shall have no liability for damages arising out of the uses set forth above 8 Notwithstanding the preceding paragraph you should not use Renesas products for the purposes listed below 1 artificial life support devices or systems 2 surgical implantations 3 healthcare intervention e g excision administration of medication etc 4 any other purposes that pose a...

Page 181: ...R61509V Target Spec Rev 0 11 April 25 2008 page 181 of 181 Revision Record Rev Date Page No Contents of Modification Drawn by Approved by 0 11 2008 04 25 First issue ...

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