Renesas M16C Series, User Manual, Page: 183 / 846

R01UH0092EJ0110 Rev.1.10 Page 150 of 807
Jul 31, 2012
M16C/64C Group 11. Bus
11.3.5.9 Software Wait States
The PM17 bit in the PM1 register, which is a software-wait-related bit, affects both the internal
memory and the external area.
Software wait states can be inserted to the external area by setting the PM17 bit, setting the CSiW bit
in the CSR register, and bits CSEi1W to CSEi0W in the CSE register for each
CSi
(i = 0 to 3). To use
the
RDY
signal, set the corresponding CSiW bit to 0 (wait state). See Table 11.10 “Bits and Bus
Cycles Related to Software Wait States (External Area)” for details.
Table 11.10 Bits and Bus Cycles Related to Software Wait States (External Area)
Area Bus Mode Setting of Software-Wait-Related Bits Software
Wait
Cycles Bus Cycles
PM17 CSiW CSEi1W to
CSEi0W
External
area Separate
bus 0 1 00b None 1 BCLK cycle
(read)
2 BCLK cycles
(write)
- 0 00b 1 (1
φ
+ 1
φ
)
2 BCLK cycles
(4)
- 0 01b 2 (1
φ
+ 2
φ
) 3 BCLK cycles
- 0 10b 3 (1
φ
+ 3
φ
) 4 BCLK cycles
1
0
(3) 00b 1 (1
φ
+ 1
φ
) 2 BCLK cycles
Multiplexed
bus -
0
(2)
00b
1
(5)
3 BCLK cycles
-
0
(2) 01b 2 3 BCLK cycles
-
0
(2) 10b 3 4 BCLK cycles
1
0
(2), (3) 00b
1
(5) 3 BCLK cycles
i = 0 to 3
−
indicates that either 0 or 1 can be set.
PM17: Bit in the PM1 register
CSiW: Bits in the CSR register
(1)
CSEi1W, CSEi0W: Bits in the CSE register
Notes:
1. To use the
RDY
signal, set the CSiW bit to 0 (wait state).
2. To access in multiplexed bus mode, set the CSiW bit to 0 (wait state).
3. To access an external area when the PM17 bit is 1, set the CSiW bit to 0 (wait state).
4. After reset, the PM17 bit is set to 0 (no wait state), bits CS0W to CS3W are set to 0 (wait
state), and the CSE register is set to 00h (one wait state for
CS0
to
CS3
). Therefore, all
external areas are accessed with one wait state.
5. When setting one wait in multiplexed bus, the bus cycle is the same as two waits.