Renesas M16C/60 Series User Manual Download Page 180 | Manualshive

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R01UH0136EJ0210 Rev.2.10

Page 147 of 800

Jul 31, 2012

M16C/64A Group

11. Bus

11.3.5.6

RDY

Signal

This signal is provided for accessing external devices which need to be accessed at low speed. If
input to the

RDY

pin is low at the last falling edge of BCLK in the bus cycle, one wait state is inserted

in the bus cycle. While in wait state, the following signals retain the state in which they were when the

RDY

signal was acknowledged:

A0 to A19, D0 to D15,

CS0

to

CS3

,

RD

,

WRL

,

WRH

,

WR

,

BHE

, ALE,

HLDA

Then, when input to the

RDY

pin is detected high at the falling edge of BCLK, the remaining bus cycle

is executed. Figure 11.4 shows Examples in Which Wait State Was Inserted into Read Cycle by

RDY

Signal. To use the

RDY

signal, set the corresponding bit (among bits CS3W to CS0W) in the CSR

register to 0 (with wait state). When not using the

RDY

signal, pull-up the

RDY

pin.

Figure 11.4

Examples in Which Wait State Was Inserted into Read Cycle by

RDY

Signal

11.3.5.7

BCLK Output

When the PM07 bit in the PM0 register is set to 0 (output enabled), a clock with the same frequency
as the CPU clock is output as BCLK from the BCLK pin. Refer to 8.4 “CPU Clock and Peripheral
Function Clocks”.

BCLK

RD

CSi

(i = 0 to 3)

RDY

tsu(RDY - BCLK)

BCLK

RD

CSi

(i = 0 to 3)

RDY

tsu(RDY - BCLK)

Separate bus

Multiplexed bus

Accept timing of RDY signal

Accept timing of RDY signal

tsu(RDY - BCLK)

: Wait using software

: Wait using RDY signal

: Duration for RDY input setup

The above diagrams assume bits CSEi1W to CSEi0W (i = 0 to 3) in the CSE register are 00b (one wait).

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Summary of Contents for M16C/60 Series

Page 1: ...ion on the product at the time of publication and is subject to change by Renesas Electronics Corp without notice Please review the latest information published by Renesas Electronics Corp through var...

Page 2: ...range heat radiation characteristics installation and other product characteristics Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electroni...

Page 3: ...supplied until the reset process is completed In a similar way the states of pins in a product that is reset by an on chip power on reset function are not guaranteed from the moment when power is sup...

Page 4: ...at the end of this manual summarizes primary modifications and additions to the previous versions For details please refer to the relative chapters or sections of this manual Type of Document Content...

Page 5: ...and pins are indicated by symbols Each symbol has a register bit pin identifier after the symbol Example PM03 bit in the PM0 register P3_5 pin VCC pin 2 Numbers A binary number has the suffix b excep...

Page 6: ...e detected 1 Example not detected See Note 1 See Note 2 See Note 4 See Note 3 Notes 1 Blank box Set this bit to 0 or 1 according to the function 0 Set this bit to 0 1 Set this bit to 1 X Nothing is as...

Page 7: ...r second CRC Cyclic Redundancy Check DMA Direct Memory Access DMAC Direct Memory Access Controller GSM Global System for Mobile Communications Hi Z High Impedance IEBus Inter Equipment Bus I O Input O...

Page 8: ...15 2 7 Static Base Register SB 15 2 8 Flag Register FLG 15 2 8 1 Carry Flag C Flag 15 2 8 2 Debug Flag D Flag 15 2 8 3 Zero Flag Z Flag 15 2 8 4 Sign Flag S Flag 15 2 8 5 Register Bank Select Flag B F...

Page 9: ...Reset 56 6 4 10 Cold Warm Start Discrimination 57 6 5 Notes on Resets 58 6 5 1 Power Supply Rising Gradient 58 6 5 2 Power On Reset 58 6 5 3 OSDR Bit Oscillation Stop Detect Reset Detect Flag 59 6 5 4...

Page 10: ...d Peripheral Function Clocks 99 8 4 1 CPU Clock and BCLK 99 8 4 2 Peripheral Function Clocks f1 fOCO S fC32 fC 99 8 5 Clock Output Function 101 8 6 System Clock Protection Function 101 8 7 Oscillator...

Page 11: ...k 129 9 6 2 Wait Mode 129 9 6 3 Stop Mode 129 9 6 4 Low Current Consumption Read Mode 130 9 6 5 Slow Read Mode 130 10 Processor Mode 131 10 1 Introduction 131 10 2 Registers 132 10 2 1 Processor Mode...

Page 12: ...0 to 10 183 13 3 6 Port Pi Direction Register PDi i 0 to 10 184 13 3 7 NMI SD Digital Filter Register NMIDF 185 13 4 Peripheral Function I O 186 13 4 1 Peripheral Function I O and Port Direction Bits...

Page 13: ...struction Interrupt 205 14 5 Hardware Interrupts 206 14 5 1 Special Interrupts 206 14 5 2 Peripheral Function Interrupts 206 14 6 Interrupts and Interrupt Vectors 207 14 6 1 Fixed Vector Tables 207 14...

Page 14: ...ce Protection Mode Disabled 230 15 4 2 Count Source Protection Mode Enabled 231 15 5 Interrupts 232 15 6 Notes on the Watchdog Timer 233 16 DMAC 234 16 1 Introduction 234 16 2 Registers 236 16 2 1 DMA...

Page 15: ...1 Common Operations 267 17 3 2 Timer Mode 269 17 3 3 Event Counter Mode When Not Using Two Phase Pulse Signal Processing 273 17 3 4 Event Counter Mode When Processing Two Phase Pulse Signal 277 17 3...

Page 16: ...i1 i 1 2 4 331 19 2 3 Three Phase PWM Control Register 0 INVC0 332 19 2 4 Three Phase PWM Control Register 1 INVC1 334 19 2 5 Three Phase Output Buffer Register i IDBi i 0 1 336 19 2 6 Dead Time Timer...

Page 17: ...4 20 4 Interrupts 390 20 5 Notes on Real Time Clock 391 20 5 1 Starting and Stopping the Count 391 20 5 2 Register Settings Time Data etc 391 20 5 3 Register Settings Compare Data 391 20 5 4 Time Read...

Page 18: ...ation of PMC0 and PMC1 440 22 4 Interrupts 443 22 5 Notes on Remote Control Signal Receiver 446 22 5 1 Starting Stopping PMCi 446 22 5 2 Reading the Register 446 22 5 3 Rewriting the Register 446 22 5...

Page 19: ...4 2 4 SI Oi Bit Rate Register SiBRG i 3 4 523 24 2 5 SI O3 4 Control Register 2 S34C2 523 24 3 Operations 524 24 3 1 Basic Operations 524 24 3 2 CLK Polarity Selection 524 24 3 3 LSB First or MSB Firs...

Page 20: ...after Transmitting Receiving a Slave Address or Data 569 25 3 9 Timeout Detection 570 25 3 10 Data Transmit Receive Examples 571 25 4 Interrupts 576 25 5 Notes on Multi master I2C bus Interface 579 25...

Page 21: ...Detection Assist Function Register AINRST 620 27 2 3 A D Register i ADi i 0 to 7 621 27 2 4 A D Control Register 2 ADCON2 622 27 2 5 A D Control Register 0 ADCON0 623 27 2 6 A D Control Register 1 ADC...

Page 22: ...he D A Converter 651 29 CRC Calculator 652 29 1 Introduction 652 29 2 Registers 653 29 2 1 SFR Snoop Address Register CRCSAR 653 29 2 2 CRC Mode Register CRCMR 654 29 2 3 CRC Data Register CRCD 654 29...

Page 23: ...1 Electrical Characteristics Common to 3 V and 5 V 700 31 1 1 Absolute Maximum Rating 700 31 1 2 Recommended Operating Conditions 701 31 1 3 A D Conversion Characteristics 703 31 1 4 D A Conversion C...

Page 24: ...6 32 5 5 PLL Frequency Synthesizer 757 32 5 6 Starting PLL Clock Oscillation 758 32 6 Notes on Power Control 759 32 6 1 CPU Clock 759 32 6 2 Wait Mode 759 32 6 3 Stop Mode 759 32 6 4 Low Current Consu...

Page 25: ...15 Notes on Real Time Clock 776 32 15 1 Starting and Stopping the Count 776 32 15 2 Register Settings Time Data etc 776 32 15 3 Register Settings Compare Data 776 32 15 4 Time Reading Procedure in Re...

Page 26: ...789 32 21 4 Register Access 789 32 21 5 A D Conversion Start 789 32 21 6 A D Operation Mode Change 789 32 21 7 State When Forcibly Terminated 790 32 21 8 A D Open Circuit Detection Assist Function 79...

Page 27: ...sion Interrupt Control Register ADIC 196 004Fh UART2 Transmit Interrupt Control Register S2TIC 195 0050h UART2 Receive Interrupt Control Register S2RIC 195 0051h UART0 Transmit Interrupt Control Regis...

Page 28: ...lect Register 0 TACS0 257 01D1h Timer A Count Source Select Register 1 TACS1 257 01D2h Timer A Count Source Select Register 2 TACS2 257 01D3h 01D4h 16 bit Pulse Width Modulation Mode Function Select R...

Page 29: ...r Register U0RB 461 024Fh 0250h UART Transmit Receive Control Register 2 UCON 463 0251h 0252h 0253h 0254h UART1 Special Mode Register 4 U1SMR4 464 0255h UART1 Special Mode Register 3 U1SMR3 466 0256h...

Page 30: ...0 544 02B7h I2C0 Control Register 2 S4D0 548 02B8h I2C0 Status Register 0 S10 550 02B9h I2C0 Status Register 1 S11 555 02BAh I2C0 Address Register 1 S0D1 538 02BBh I2C0 Address Register 2 S0D2 538 02B...

Page 31: ...595 035Ah CEC Receive Follower Address Set Register 1 CRADRI1 596 035Bh CEC Receive Follower Address Set Register 2 CRADRI2 596 035Ch 035Dh 035Eh 035Fh 0360h Pull Up Control Register 0 PUR0 179 0361h...

Page 32: ...649 03DDh 03DEh 03DFh 03E0h Port P0 Register P0 183 03E1h Port P1 Register P1 183 03E2h Port P0 Direction Register PD0 184 03E3h Port P1 Direction Register PD1 184 03E4h Port P2 Register P2 183 03E5h...

Page 33: ...r 2 PMC0DAT2 420 D08Fh PMC0 Receive Data Store Register 3 PMC0DAT3 420 D090h PMC0 Receive Data Store Register 4 PMC0DAT4 420 D091h PMC0 Receive Data Store Register 5 PMC0DAT5 420 D092h PMC0 Receive Bi...

Page 34: ...a multiplier for high speed operation processing This MCU consumes low power and supports operating modes that allow additional power control The MCU also uses an anti noise configuration to reduce em...

Page 35: ...w speed on chip oscillator 125 kHz PLL frequency synthesizer Oscillation stop detection Main clock oscillation stop restart detection function Frequency divider circuit Divide ratio selectable from 1...

Page 36: ...ings differentiate wave pattern for headers data 0 data 1 and special data 6 byte receive buffer 1 circuit only Operating frequency of 32 kHz Serial Interface UART0 to UART2 UART5 to UART7 Clock synch...

Page 37: ...ing temperature 20 C to 85 C R5F364A6NFB PLQP0100KB A R5F364A6DFA PRQP0100JD B Operating temperature 40 C to 85 C R5F364A6DFB PLQP0100KB A R5F364AENFA 256 KB 16 KB 4 KB 2 blocks 20 KB PRQP0100JD B Ope...

Page 38: ...emperature 20 C to 85 C D Operating temperature 40 C to 85 C Memory type F Flash memory R 5 F 3 6 4 A 6 D FA Renesas MCU Renesas semiconductor M16C 64A Group 100 pins Memory capacity Program ROM 1 RAM...

Page 39: ...s on MCU type 8 8 8 8 8 8 Port P5 Port P4 Port P3 Port P2 Port P1 Port P0 VCC2 ports M16C 60 Series CPU core R1H R1L R0H R0L R3 R2 A0 A1 FB Multiplier ROM 1 Memory RAM 2 SB ISP USP INTB PC FLG CRC cal...

Page 40: ...TXD2 SDA2 SDAMM TA0OUT 1 P8_4 INT2 ZP P7_3 CTS2 RTS2 TA1IN V P7_5 TA2IN W P10_7 AN7 KI3 P10_6 AN6 KI2 P10_5 AN5 KI1 P10_4 AN4 KI0 P5_6 ALE P5_5 HOLD P5_4 HLDA P5_3 BCLK P5_2 RD P5_7 RDY CLKOUT P6_3 T...

Page 41: ...P9_3 DA0 TB3IN PWM0 P9_4 DA1 TB4IN PWM1 P9_1 TB1IN PMC1 SIN3 P9_2 TB2IN PMC0 SOUT3 P8_2 INT0 P8_3 INT1 P8_5 NMI SD CEC 1 P9_0 TB0IN CLK3 P8_4 INT2 ZP P7_5 TA2IN W P7_3 CTS2 RTS2 TA1IN V P7_6 TA3OUT T...

Page 42: ...CEC 18 16 P8_4 INT2 ZP 19 17 P8_3 INT1 20 18 P8_2 INT0 21 19 P8_1 TA4IN U CTS5 RTS5 22 20 P8_0 TA4OUT U RXD5 SCL5 23 21 P7_7 TA3IN CLK5 24 22 P7_6 TA3OUT TXD5 SDA5 25 23 P7_5 TA2IN W 26 24 P7_4 TA2OU...

Page 43: ...65 P2_5 INT7 AN2_5 A5 A5 D5 A5 D4 68 66 P2_4 INT6 AN2_4 A4 A4 D4 A4 D3 69 67 P2_3 AN2_3 A3 A3 D3 A3 D2 70 68 P2_2 AN2_2 A2 A2 D2 A2 D1 71 69 P2_1 AN2_1 A1 A1 D1 A1 D0 72 70 P2_0 AN2_0 A0 A0 D0 A0 73...

Page 44: ...area with a separate bus D8 to D15 I O VCC2 Inputs or outputs data D8 to D15 while accessing an external area with a 16 bit separate bus A0 to A19 O VCC2 Outputs address bits A0 to A19 A0 D0 to A7 D7...

Page 45: ...rrupt INT3 to INT7 I VCC2 NMI interrupt input NMI I VCC1 Input for the NMI interrupt Key input interrupt input KI0 to KI3 I VCC1 Input for the key input interrupt Timer A TA0OUT to TA4OUT I O VCC1 I O...

Page 46: ...ain output Reference voltage input VREF I VCC1 Reference voltage input for the A D and D A converters A D converter AN0 to AN7 I VCC1 Analog input AN0_0 to AN0_7 AN2_0 to AN2_7 I VCC2 ADTRG I VCC1 Ext...

Page 47: ...banks C D Z S B O I U IPL R2 b31 R3 R2 A1 A0 FB b19 INTBL b15 b0 PC INTBH is the 4 upper bits of the INTB register and INTBL is the 16 lower bits b19 b0 b15 b0 FLG b15 b0 b15 b0 b7 b8 Data registers 1...

Page 48: ...m Counter PC The PC is 20 bits wide and indicates the address of the next instruction to be executed 2 6 User Stack Pointer USP and Interrupt Stack Pointer ISP The USP and ISP stack pointers SP are ea...

Page 49: ...inter Select Flag U Flag ISP is selected when the U flag is 0 USP is selected when the U flag is 1 The U flag becomes 0 when a hardware interrupt request is accepted or the INT instruction of software...

Page 50: ...1 In 4 MB mode Internal RAM Reserved area 00000h 0D000h SFR 00400h SFR 0D800h Internal ROM data flash 0E000h Internal ROM program ROM 2 10000h Reserved area Internal ROM program ROM 1 14000h FFFFFh Re...

Page 51: ...vector table for interrupts is allocated from FFFDCh to FFFFFh The 256 bytes beginning with the start address set in the INTB register compose the relocatable vector table for interrupts Figure 3 2 s...

Page 52: ...mode and memory expansion mode The PM10 bit in the PM1 register is 1 addresses 0E000h to 0FFFFh are used as data flash The PRG2C0 bit in the PRG2C register is 0 program ROM 2 enabled The PM13 bit in t...

Page 53: ...Processor Mode Register 0 PM0 0000 0000b CNVSS pin is low 0000 0011b CNVSS pin is high 2 0005h Processor Mode Register 1 PM1 0000 1000b 0006h System Clock Control Register 0 CM0 0100 1000b 0007h Syst...

Page 54: ...egister Symbol Reset Value 0020h 0021h 0022h 0023h 0024h 0025h 0026h Voltage Monitor Function Select Register VWCE 00h 0027h 0028h Voltage Detector 1 Level Select Register VD1LS 0000 1010b 2 0029h 002...

Page 55: ...X X000b 004Ch DMA1 Interrupt Control Register DM1IC XXXX X000b 004Dh Key Input Interrupt Control Register KUPIC XXXX X000b 004Eh A D Conversion Interrupt Control Register ADIC XXXX X000b 004Fh UART2 T...

Page 56: ...UART6 Bus Collision Detection Interrupt Control Register Real Time Clock Periodic Interrupt Control Register U6BCNIC RTCTIC XXXX X000b 006Fh UART6 Transmit Interrupt Control Register Real Time Clock...

Page 57: ...XXh 018Ah 018Bh 018Ch DMA0 Control Register DM0CON 0000 0X00b 018Dh 018Eh 018Fh 0190h DMA1 Source Pointer SAR1 XXh 0191h XXh 0192h 0Xh 0193h 0194h DMA1 Destination Pointer DAR1 XXh 0195h XXh 0196h 0X...

Page 58: ...Register TB21 XXh 01C5h XXh 01C6h Pulse Period Pulse Width Measurement Mode Function Select Register 1 PPWFS1 XXXX X000b 01C7h 01C8h Timer B Count Source Select Register 0 TBCS0 00h 01C9h Timer B Coun...

Page 59: ...0000 00X0b 01F3h PMC0 Function Select Register 3 PMC0CON3 00h 01F4h PMC0 Status Register PMC0STS 00h 01F5h PMC0 Interrupt Source Select Register PMC0INT 00h 01F6h PMC0 Compare Control Register PMC0CP...

Page 60: ...s Match Interrupt Register 2 RMAD2 00h 0219h 00h 021Ah X0h 021Bh 021Ch Address Match Interrupt Register 3 RMAD3 00h 021Dh 00h 021Eh X0h 021Fh 0220h Flash Memory Control Register 0 FMR0 0000 0001b Othe...

Page 61: ...de Register 4 U1SMR4 00h 0255h UART1 Special Mode Register 3 U1SMR3 000X 0X0Xb 0256h UART1 Special Mode Register 2 U1SMR2 X000 0000b 0257h UART1 Special Mode Register U1SMR X000 0000b 0258h UART1 Tran...

Page 62: ...00 0000b 0287h UART5 Special Mode Register U5SMR X000 0000b 0288h UART5 Transmit Receive Mode Register U5MR 00h 0289h UART5 Bit Rate Register U5BRG XXh 028Ah UART5 Transmit Buffer Register U5TB XXh 02...

Page 63: ...uffer Register U7TB XXh 02ABh XXh 02ACh UART7 Transmit Receive Control Register 0 U7C0 0000 1000b 02ADh UART7 Transmit Receive Control Register 1 U7C1 0000 0010b 02AEh UART7 Receive Buffer Register U7...

Page 64: ...Dh Timer B2 Interrupt Generation Frequency Set Counter ICTB2 XXh 030Eh Position Data Retain Function Control Register PDRF XXXX 0000b 030Fh 0310h Timer B3 Register TB3 XXh 0311h XXh 0312h Timer B4 Reg...

Page 65: ...Time Clock Day Data Register RTCWK XXXX X000b 0344h Real Time Clock Control Register 1 RTCCR1 0000 X00Xb 0345h Real Time Clock Control Register 2 RTCCR2 X000 0000b 0346h Real Time Clock Count Source S...

Page 66: ...ROINI bit in the OFS1 address is 0 the reset value is 1000 0000b Table 4 14 SFR Information 14 1 Address Register Symbol Reset Value 0360h Pull Up Control Register 0 PUR0 00h 0361h Pull Up Control Reg...

Page 67: ...7h 0398h DMA0 Source Select Register DM0SL 00h 0399h 039Ah DMA1 Source Select Register DM1SL 00h 039Bh 039Ch 039Dh 039Eh 039Fh 03A0h 03A1h 03A2h Open Circuit Detection Assist Function Register AINRST...

Page 68: ...03D2h 03D3h 03D4h A D Control Register 2 ADCON2 0000 X00Xb 03D5h 03D6h A D Control Register 0 ADCON0 0000 0XXXb 03D7h A D Control Register 1 ADCON1 0000 X000b 03D8h D A0 Register DA0 00h 03D9h 03DAh D...

Page 69: ...Table 4 17 SFR Information 17 1 Address Register Symbol Reset Value 03F0h Port P8 Register P8 XXh 03F1h Port P9 Register P9 XXh 03F2h Port P8 Direction Register PD8 00h 03F3h Port P9 Direction Regist...

Page 70: ...D08Ah D08Bh D08Ch PMC0 Receive Data Store Register 0 PMC0DAT0 00h D08Dh PMC0 Receive Data Store Register 1 PMC0DAT1 00h D08Eh PMC0 Receive Data Store Register 2 PMC0DAT2 00h D08Fh PMC0 Receive Data S...

Page 71: ...69h UART2 Bit Rate Register U2BRG 026Bh to 026Ah UART2 Transmit Buffer Register U2TB 0273h SI O3 Bit Rate Register S3BRG 0277h SI O4 Bit Rate Register S4BRG 0289h UART5 Bit Rate Register U5BRG 028Bh t...

Page 72: ...rite Instructions Function Mnemonic Transfer MOVDir Bit processing BCLR BMCnd BNOT BSET BTSTC and BTSTS Shifting ROLC RORC ROT SHA and SHL Arithmetic operation ABS ADC ADCF ADD DEC DIV DIVU DIVX EXTS...

Page 73: ...Symbol RW After Reset 00h b0 b5 b4 RW PRC6 RW b7 RW PRC0 RW PRC1 RW PRC2 RW PRC3 RW Bit Name Reserved bits Protect bit 6 Reserved bit Protect bit 0 Protect bit 1 Protect bit 2 Protect bit 3 Function...

Page 74: ...i bit to 1 i 0 1 3 6 2 Write to the register protected by the PRCi bit 3 Set the PRCi bit to 0 write protected PRC2 Protect bit 2 b2 After setting the PRC2 bit to 1 write enabled by writing to a given...

Page 75: ...PRC2 bit to 1 write enabled by writing to a given SFR the PRC2 bit becomes 0 write disabled Change the registers protected by the PRC2 bit in the next instruction after setting the PRC2 bit to 1 Make...

Page 76: ...t A rise in voltage on VCC1 N A Voltage monitor 0 reset A drop in voltage on VCC1 reference voltage Vdet0 N A Voltage monitor 1 reset A drop in voltage on VCC1 reference voltage Vdet1 B Voltage monito...

Page 77: ...W1C register Bits VW2C2 and VW2C3 in the VW2C register Bits PM00 and PM01 in the PM0 register SFR C VD1LS register SFR D Bits CM20 CM21 and CM27 in the CM2 register Table 6 3 I O Pins Pin I O Function...

Page 78: ...15 Watchdog Timer for registers used with the watchdog timer reset Refer to 8 7 Oscillator Stop Restart Detect Function for registers used with the oscillator stop detect reset Table 6 4 Registers Add...

Page 79: ...r 0 Symbol PM0 Address 0004h Bit Symbol Bit Name RW PM00 Reset Value 0000 0000b CNVSS pin is low 0000 0011b CNVSS pin is high RW b0 Function b1 b0 0 0 Single chip mode 0 1 Memory expansion mode 1 0 Do...

Page 80: ...0 0 Voltage monitor 1 reset 0 0 1 0 0 0 No change Voltage monitor 2 reset 0 1 0 0 0 0 No change Oscillator stop detect reset 1 0 0 0 0 0 No change Watchdog timer reset 0 0 0 1 0 0 No change Software...

Page 81: ...WDTON Watchdog timer start select bit b0 CSPROINI After reset count source protection mode select bit b7 These bits select the state of the watchdog timer after reset Set the WDTON bit to 0 watchdog...

Page 82: ...the power on reset or voltage monitor 0 reset Refer to 6 4 10 Cold Warm Start Discrimination This bit is enabled in single chip mode while disabled in boot mode LVDAS Voltage detector 0 start bit b6 S...

Page 83: ...input Input port P1 Input port Data input Input port Input port P2 P3 P4_0 to P4_3 Input port Address output undefined Address output undefined Input port P4_4 Input port CS0 output high level is out...

Page 84: ...FB Program counter PC Interrupt table register INTB User stack pointer USP Interrupt stack pointer ISP Static base register SB Flag register FLG 0000h 0000h 0000h C D Z S B O I U IPL 0000h 0000h 0000...

Page 85: ...dress XIN RESET RD WR CS0 RD WR CS0 VCC1 VCC2 Microprocessor mode BYTE high Microprocessor mode BYTE low Single chip mode Content of reset vector FFFFCh FFFFDh FFFFEh Content of reset vector FFFFCh FF...

Page 86: ...hen a low level signal is applied to the RESET pin while writing data to the internal RAM the internal RAM becomes undefined The procedures for generating a hardware reset are as follows When the powe...

Page 87: ...mes 0 cold start after power on reset Refer to 4 Special Function Registers SFRs for the remaining SFR states after reset The internal RAM is not reset Use the voltage monitor 0 reset together with th...

Page 88: ...n drops to Vdet1 or below fOCO S divided by 8 is automatically selected as the CPU clock after reset After tps 60 cycles of the CPU clock has elapsed the MCU executes the program at the address indica...

Page 89: ...underflows and the watchdog timer underflows Then the MCU executes the program at the address determined by the reset vector fOCO S divided by 8 is automatically selected as the CPU clock after reset...

Page 90: ...g 1 and remains unchanged at hardware reset voltage monitor 1 reset voltage monitor 2 reset oscillator stop detect reset watchdog timer reset or software reset In the cold warm start discrimination th...

Page 91: ...ss to 0 voltage monitor 0 reset enabled after hardware reset and the VDSEL1 bit to 0 Vdet0_2 In this case the voltage monitor 0 reset is enabled the VW0C0 bit and bit 6 in the VW0C register are 1 and...

Page 92: ...y a hardware reset but becomes 0 not detected from a voltage monitor 0 reset 6 5 4 Hardware Reset when VCC1 Vdet0 When a hardware reset is executed while VCC1 Vdet0 the voltage monitor 0 reset is not...

Page 93: ...els in the VD1LS register Fixed level Monitor None VW1C3 bit in the VW1C register VC13 bit in the VCR1 register Whether VCC1 is higher or lower than Vdet1 Whether VCC1 is higher or lower than Vdet2 Pr...

Page 94: ...oltage detector 0 signal Voltage detector 2 signal VCC1 VD1LS3 to VD1LS0 b3 VW1C3 bit in the VW1C register b3 VC13 bit in the VCR1 register Level selector VDSEL1 VC13 Bit in the VCR1 register VC27 VC2...

Page 95: ...2 Registers Address Register Name Register Symbol Reset Value 0019h Voltage Detector 2 Flag Register VCR1 0000 1000b 001Ah Voltage Detector Operation Enable Register VCR2 00h 0026h Voltage Monitor Fu...

Page 96: ...27 bit in the VCR2 register is 1 voltage detector 2 enabled Condition to become 0 VCC1 Vdet2 when the VW12E bit is 1 and the VC27 bit is 1 Conditions to become 1 VCC1 Vdet2 when the VW12E bit is 1 and...

Page 97: ...tage detector 2 enable bit b7 Voltage detector 2 is enabled when the VW12E bit in the VWCE register is set to 1 voltage monitors 1 and 2 enabled and the VC27 bit is 1 voltage detector 2 enabled Set bi...

Page 98: ...age monitors 1 and 2 enable bit b0 Set this bit to 1 enabled to set either or both bits VC26 and VC27 in the VCR2 register to 1 enabled b7 0 0 0 0 0 0 0 b6 b5 b4 b1 b2 b3 Voltage Monitor Function Sele...

Page 99: ...evert to the previous setting VD1LS3 to VD1LS0 Vdet1 select bit b3 to b0 When using voltage detector 1 the reset value cannot be used as is Only set the values shown in the register When not using det...

Page 100: ...e LVDAS bit in the OFS1 address is 1 this bit becomes 0 after hardware reset When using voltage monitor 0 reset set this bit to 1 b7 1 1 0 0 0 1 b6 b5 b4 b1 b2 b3 Voltage Monitor 0 Control Register Sy...

Page 101: ...After using voltage monitor 1 interrupt to exit stop mode to use it again to exit stop mode set the VW1C1 bit to 0 first and then to 1 b7 b6 b5 b4 b1 b2 b3 Voltage Monitor 1 Control Register Symbol V...

Page 102: ...1LS register again then set the VW1C3 bit The VW12E bit in the VWCE register becomes 0 from a reset When monitoring the voltage detector 1 signal level set the VW12E bit to 1 again VW1C6 Voltage monit...

Page 103: ...lect bit b1 After using the voltage monitor 2 interrupt to exit stop mode to use it again to exit stop mode set the VW2C1 bit to 0 first and then to 1 b7 b6 b5 b4 b1 b2 b3 Voltage Monitor 2 Control Re...

Page 104: ...bit is 0 voltage monitor 2 interrupt at Vdet2 passage and the VW2C1 bit is 1 digital filter disabled When the VW2C6 bit is 1 voltage monitor 2 reset at Vdet2 passage set the VW2C7 bit to 1 when VCC1...

Page 105: ...in voltage detector 0 is selectable Voltage detector 0 operates based on Vdet0 Set the VDSEL1 bit to 0 Vdet0_2 when using power on reset or voltage monitor 0 reset Refer to 6 4 10 Cold Warm Start Disc...

Page 106: ...n the VCC1 input voltage level passes Vdeti until when a reset or an interrupt is generated is up to three cycles of the sampling clock Since fOCO S stops in stop mode the digital filter does not func...

Page 107: ...r falls through Vdet0 The Vdet0 level can be selected by the VDSEL1 bit in the OFS1 address Figure 7 3 Voltage Monitor 0 Reset Generator Block Diagram Voltage detector 0 VC25 Internal reference voltag...

Page 108: ...Reset Operation Example Figure 7 4 Voltage Monitor 0 Reset Operation Example Table 7 6 Procedure for Setting Voltage Monitor 0 Reset Related Bits Step Processing 1 Set the VC25 bit in the VCR2 regist...

Page 109: ...ector 1 enabled Vdet1 can be monitored by using the VW1C3 bit in the VW1C register after td E A elapses 1 2 1 2 1 2 Voltage detector 1 VC26 VCC1 Internal reference voltage VW1C3 The voltage detector 1...

Page 110: ...e VW1C register to 0 digital filter enabled Set the VW1C1 bit in the VW1C register to 1 digital filter disabled 7 2 Set the VW1C6 bit in the VW1C register to 0 voltage monitor 1 interrupt Set the VW1C...

Page 111: ...hes Vdet1 or above VW1C1 VW1C2 VW1C3 VW1C6 VW1C7 Bits in the VW1C register Voltage monitor 1 interrupt request when VW1C6 is 0 Voltage monitor 1 interrupt request when VW1C6 is 0 VW1C2 bit When the VW...

Page 112: ...ster to 1 voltage detector 2 enabled Vdet2 can be monitored using the VC13 bit in the VCR1 register after td E A elapses 1 2 1 2 1 2 Voltage detector 2 VC27 Internal reference voltage VC13 The voltage...

Page 113: ...r enabled Set the VW2C1 bit in the VW2C register to 1 digital filter disabled 6 2 Set the VW2C6 bit in the VW2C register to 0 voltage monitor 2 interrupt Set the VW2C6 bit in the VW2C register to 1 vo...

Page 114: ...above VC13 Bit in the VCR1 register VW2C1 VW2C2 VW2C6 VW2C7 Bits in the VW2C register Voltage monitor 2 interrupt request when VW2C6 is 0 Voltage monitor 2 interrupt request when VW2C6 is 0 VW2C2 bit...

Page 115: ...tage monitor 1 interrupt and voltage monitor 2 interrupt share the same vector When using some functions together read the detect flags of the events in an interrupt processing program and determine t...

Page 116: ...clock oscillator Item Main Clock Oscillator PLL Frequency Synthesizer 125 kHz on chip oscillator Sub Clock Oscillator Application CPU clock source Peripheral function clock source CPU clock source Per...

Page 117: ...in the PM2 register XOUT Main clock oscillator CM02 CM04 CM10 1 stop mode Q S R WAIT instruction CM05 Q S R Software reset fC CPU clock CM07 Divider a 1 2 1 2 1 2 1 2 CM06 0 CM17 to CM16 00b CM06 0 C...

Page 118: ...port direction bits which share pins to 0 input mode Table 8 3 Registers Address Register Symbol Reset Value 0004h Processor Mode Register 0 PM0 0000 0000b CNVSS pin is low 0000 0011b CNVSS pin is hi...

Page 119: ...the BCLK pin b7 b6 b5 b4 b1 b2 b3 Processor Mode Register 0 Symbol PM0 Address 0004h Bit Symbol Bit Name RW PM00 Reset Value 0000 0000b CNVSS pin is low 0000 0011b CNVSS pin is high RW b0 Function b1...

Page 120: ...t 0 0 1 fC is output 0 1 0 f8 is output 0 1 1 f32 is output 1 0 0 f1 is output Only set the combinations listed above b7 b6 b5 b4 b1 b2 b3 System Clock Control Register 0 Symbol CM0 Address 0006h Bit...

Page 121: ...ect Function for details on main clock stop detection When the PM21 bit in the PM2 register is 1 clock change disabled this bit remains unchanged even when written to CM06 Main clock division select b...

Page 122: ...k The CPU clock source and the peripheral function clock f1 can be selected by the CM11 bit when the CM07 bit is 0 main clock PLL clock or on chip oscillator clock used as CPU clock The peripheral fun...

Page 123: ...bit is set to 1 on chip oscillator clock the CM14 bit is automatically set to 0 125 kHz on chip oscillator on and remains unchanged even when 1 is written to this bit Note that the 125 kHz on chip osc...

Page 124: ...estart detect function enabled and the CM23 bit is 1 main clock stopped do not set the CM21 bit to 0 main clock or PLL clock When the CM20 bit is 1 oscillator stop restart detect function enabled the...

Page 125: ...start detect interrupt is generated Use this bit in an interrupt routine to determine the factors of interrupts between the oscillator stop restart detect interrupt and other interrupts When the CM22...

Page 126: ...ngle Chip Mode Peripheral Clock Select Register b7 0 0 0 0 0 b6 b5 b4 b1 b2 b3 Symbol PCLKR Address 0012h Bit Symbol Bit Name RW Reset Value 0000 0011b b0 Function b4 b2 RW Reserved bits Set to 0 b7 b...

Page 127: ...sabled writing to bits PLC05 and PLC04 has no effect PLC07 Operation enable bit b7 When the PM21 bit in the PM2 register is 1 clock change disabled writing to the PLC07 bit has no effect b7 b6 b5 b4 b...

Page 128: ...bit is set to 1 it cannot be set to 0 by a program writing 0 has no effect PM25 Peripheral clock fC provide bit b5 The PM25 bit provides fC to the real time clock CEC function and remote control signa...

Page 129: ...en the main clock oscillator is not used setting the CM13 bit in the CM1 register to 1 enables to select the internal feedback resistor not connected Perform the following steps to start or stop the m...

Page 130: ...lating when the CM20 bit in the CM2 register is 1 oscillator stop restart detect function enabled and the CM27 bit is 1 oscillator stop restart detect interrupt the 125 kHz on chip oscillator automati...

Page 131: ...tor Follow the steps below to start the sub clock Refer to 8 2 Registers for details on register and bit access 1 Set the PU21 bit in the PUR2 register to 0 P8_4 P8_6 and P8_7 not pulled high 2 Set bi...

Page 132: ...is a bus reference clock In memory expansion or microprocessor mode a BCLK signal with the same frequency as the CPU clock can be output from the BCLK pin by setting the PM07 bit in the PM0 register t...

Page 133: ...de CPU clock CPU Timer B A D converter UART0 to UART2 Real time clock SI O3 SI O4 Multi master I2C bus interface UART5 to UART7 Pulse width modulator Remote control signal receiver CEC function Main c...

Page 134: ...en if they are written to The CM02 bit in the CM0 register peripheral function clock f1 in wait mode The CM05 bit in the CM0 register to prevent the main clock from being stopped The CM07 bit in the C...

Page 135: ...CM20 bit is 1 oscillator stop restart detect function enabled the MCU is initialized and then stops oscillator stop reset Refer to 4 Special Function Registers SFRs and 6 Resets The status can be can...

Page 136: ...When CM27 Bit is 1 Condition After Detection Main clock oscillator stop detected High speed mode Medium speed mode Oscillator stop restart detect interrupt is generated CM14 bit is 0 125 kHz on chip...

Page 137: ...t is enabled 8 8 Interrupt The oscillator stop restart detect interrupt is a non maskable interrupt The watchdog timer interrupt oscillator stop restart detect interrupt voltage monitor 1 interrupt an...

Page 138: ...om the CLKOUT pin is listed below Outputting the main clock 1 Set the PRC0 bit in the PRCR register to 1 write enabled 2 Set the CM11 bit in the CM1 register the CM07 bit in the CM0 register and the C...

Page 139: ...Also if a potential difference attributed to the noise occurs between the VSS level of the MCU and the VSS level of the crystal ceramic resonator an accurate clock is not input to the MCU 8 9 2 2 Lar...

Page 140: ...or in operation or a program runaway Figure 8 10 Wiring of Signal Line Whose Level Changes at High Speed 8 9 3 CPU Clock Technical update number TN M16C 109 0309 When an external clock is input from t...

Page 141: ...Table 8 9 Acceptable Range of Power Supply Ripple Symbol Parameter Standard Unit Min Typ Max f ripple Power supply ripple allowable frequency VCC1 10 kHz VP P ripple Power supply ripple allowable amp...

Page 142: ...it from 0 to 1 3 Wait for 1 ms 4 Change the bit from VC25 to VC27 that was originally 1 back to 1 voltage detector on 8 9 6 2 When Using 125 kHz On chip Oscillator Mode or 125 kHz On chip Oscil lator...

Page 143: ...bes how to reduce the amount of current consumption 9 2 Registers Refer to 8 Clock Generator for clock related registers Table 9 1 Registers Address Register Symbol Reset Value 0220h Flash Memory Cont...

Page 144: ...opped Set the FMSTP bit by a program located in an area other than the flash memory Set the FMSTP bit to 1 under the following condition A flash memory access error occurs while erasing or programming...

Page 145: ...mount of current consumption when reading the flash memory When rewriting the flash memory CPU rewrite mode set the FMR23 bit to 0 low current consumption read mode disabled Low current consumption re...

Page 146: ...rce When the FMR22 bit is 0 slow read mode disabled When the FMSTP bit is 1 flash memory stopped During the wake up operation when the FMSTP bit is changed from 1 to 0 tps Do not perform the operation...

Page 147: ...further reduced 9 3 1 1 High Speed Mode and Medium Speed Mode In high speed mode the main clock divided by 1 no division is used as the CPU clock In medium speed mode the main clock divided by 2 4 8 o...

Page 148: ...heral function clocks 9 3 1 5 Low Speed Mode fC is used as the CPU clock When the CM21 bit is 0 and the CM11 bit is 0 main clock f1 with the same frequency of the main clock divided by 1 is used as th...

Page 149: ...by 1 125 kHz on chip oscillator mode fOCO S divided by n 1 fOCO S divided by 1 Enabled Enabled 125 kHz on chip oscillator low power mode fOCO S divided by n 1 fOCO S divided by 1 Enabled Enabled Low s...

Page 150: ...CM0 Register Bits CM17 to CM16 CM06 bit No division 2 00b 0 Divide by 2 01b 0 Divide by 4 10b 0 Divide by 8 1 Divide by 16 11b 0 Any value from 00b to 11b Notes 1 While in high speed mode medium spee...

Page 151: ...e by 8 or divide by 16 When the clock division ratio is switched in PLL operating mode or high speed or medium speed mode the ratio changes in the order shown in Figure 9 2 To change the mode follow p...

Page 152: ...divided by 16 fOCO S divided by 4 fOCO S divided by 2 125 kHz on chip oscillator mode fOCO S divided by 1 fOCO S divided by 8 a f e CPU clock source CPU clock source When the clock division ratio is s...

Page 153: ...bit to 0 and the CM07 bit to 0 main clock selected as CPU clock source 3 Set the PLC07 bit to 0 PLL off e Entering 125 kHz on chip oscillator mode from high speed mode medium speed mode or low speed m...

Page 154: ...upt control register for the peripheral function interrupt which is used to exit wait mode Start the peripheral function which is used to exit wait mode if it is stopped 3 Set 000b interrupt disabled...

Page 155: ...ource Usable when counting external signals in event counter mode Remote control signal receiver Usable Usable when fC is supplied and is used as count source Usable when fOCO S or fC32 is supplied an...

Page 156: ...ring stop mode When using stop mode set the following 1 Set the I flag to 0 2 Set the interrupt priority level of bits ILVL2 to ILVL0 in the interrupt control register for the peripheral function inte...

Page 157: ...9 lists CPU Clock After Exiting Stop Mode Table 9 8 Resets and Interrupts to Exit Stop Mode and Conditions for Use Interrupt Reset Conditions for Use Interrupt Peripheral function interrupt INT Usabl...

Page 158: ...Do not access the flash memory during this wait time Set the FMSTP bit to 1 The flash memory stops operating low power state 1 Switch clock sources of the CPU clock Main clock stop etc 2 Processing Se...

Page 159: ...17 bit in the PM1 register is 1 one wait Figure 9 4 shows Setting and Canceling Slow Read Mode When using 125 kHz on chip oscillator clock or sub clock as the CPU clock source a wait is unnecessary te...

Page 160: ...ng and Canceling Low Current Consumption Read Mode Note 1 Do not rewrite bits FMR22 and FMR23 simultaneously Low current consumption read mode Set the CM07 bit to 1 sub clock used as a CPU clock Setti...

Page 161: ...state Set the unassigned pins to input state wait until the potential stabilizes and then enter wait mode or stop mode 9 5 2 A D Converter When not performing A D conversion set the ADSTBY bit in the...

Page 162: ...ad mode To enter wait mode from low current consumption read mode set the FMR23 bit in the FMR2 register to 0 low current consumption read mode disabled Do not enter wait mode from CPU rewrite mode To...

Page 163: ...top mode when the oscillator stop restart detect function is enabled To enter stop mode set the CM20 bit in the CM2 register to 0 oscillator stop restart detect function disabled Do not enter stop mod...

Page 164: ...sor Mode Features Processor Mode Access Space Pins Assigned as I O Ports Single chip mode SFR internal RAM internal ROM All pins are I O ports or peripheral function I O pins Memory expansion mode SFR...

Page 165: ...b CNVSS pin is high 0005h Processor Mode Register 1 PM1 0000 1000b 0010h Program 2 Area Control Register PRG2C XXXX XX00b b7 b6 b5 b4 b1 b2 b3 Processor Mode Register 0 Symbol PM0 Address 0004h Bit Sy...

Page 166: ...e FMR01 bit in the FMR0 register is 1 CPU rewrite mode Table 10 4 Data Flash Addresses 0E000h to 0FFFFh PM10 Bit in PM1 Register 0 1 Processor Mode Single chip mode Reserved area Data flash Memory exp...

Page 167: ...al RAM Addresses 00400h up to 03FFFh 15 KB are available addresses 04000h to 0CFFFh cannot be used The entire area is usable Program ROM 1 Addresses D0000h up to FFFFFh 192 KB are available addresses...

Page 168: ...and user boot code area Refer to 30 7 1 User Boot Function for details Table 10 7 Program ROM 2 Addresses 10000h to 13FFFh PRG2C0 Bit in PRG2C Register 0 1 Processor Mode Single chip mode Program ROM...

Page 169: ...pin and then the MCU is reset by hardware reset power on reset or voltage monitor 0 reset the internal ROM cannot be accessed regardless of the value of bits PM01 to PM00 Table 10 9 lists Bits PM01 t...

Page 170: ...Program ROM 2 can be used when the PRG2C0 bit in the PRG2C register is 0 program ROM 2 enabled Single Chip Mode SFR Internal RAM Reserved area Internal ROM program ROM 1 00000h 00400h XXXXXh YYYYYh F...

Page 171: ...in memory expansion mode or microprocessor mode Separate bus or multiplexed bus selectable Data bus width selectable 8 or 16 bits Number of address buses selectable 12 16 or 20 buses 4 chip select ou...

Page 172: ...mode or microprocessor mode When the CSiW bit is 0 wait state the number of wait states can be selected using bits CSEi1W to CSEi0W in the CSE register b7 b6 b5 b4 b1 b2 b3 Chip Select Control Registe...

Page 173: ...hip Select Expansion Control Register Symbol CSE Address 001Bh Bit Symbol Bit Name RW Reset Value 00h b0 Function b1 b0 0 0 1 wait 1 1 0 1 2 waits 1 2 1 0 3 waits 1 3 1 1 Do not set CS0 wait expansion...

Page 174: ...us Hold Both the internal and external buses are in a hold state under the following condition Rewriting the flash memory in EW1 mode while auto programming or auto erasing When the bus is in hold sta...

Page 175: ...ry The data flash of the internal ROM is affected by both the PM17 bit in the PM1 register and the FMR17 bit in the FMR1 register Table 11 3 Bits and Bus Cycles Related to Software Wait States SFR and...

Page 176: ...dress are multiplexed When the input level to the BYTE pin is high 8 bit data bus D0 to D7 and A0 to A7 are multiplexed When the input level to the BYTE pin is low 16 bit data bus D0 to D7 and A1 to A...

Page 177: ...ines D0 to D7 When input to the BYTE pin is low 16 bit width the data bus is comprised of 16 lines D0 to D15 Do not change the input level to the BYTE pin 11 3 5 3 Chip Select Signal The chip select s...

Page 178: ...Si The chip select signal changes state but the address bus does not BCLK Read signal Data bus Address bus CSi Access to the external area indicated by CSi Access to the internal ROM or internal RAM A...

Page 179: ...e 1 byte of data to an even address H H L Write 1 byte of data to an odd address H L L Write data to both even and odd addresses Table 11 7 Operation of the RD WR and BHE Signals Data Bus Width RD WR...

Page 180: ...Inserted into Read Cycle by RDY Signal To use the RDY signal set the corresponding bit among bits CS3W to CS0W in the CSR register to 0 with wait state When not using the RDY signal pull up the RDY pi...

Page 181: ...4_4 CS0 0 I O ports CS0 1 CS0 P4_5 CS1 0 I O ports CS1 1 CS1 P4_6 CS2 0 I O ports CS2 1 CS2 P4_7 CS3 0 I O ports CS3 1 CS3 P5_0 PM02 0 WR PM02 1 5 WRL 5 WRL 5 P5_1 PM02 0 BHE PM02 1 5 WRH 5 WRH 5 P5_2...

Page 182: ...M or RAM Accessed A0 to A19 Address output Retain the last accessed address of external area or SFR D0 to D15 Read High impedance High impedance Write Data output Undefined RD WR WRL WRH RD WR WRL WRH...

Page 183: ...ternal area Separate bus 0 1 00b None 1 BCLK cycle read 2 BCLK cycles write 0 00b 1 1 1 2 BCLK cycles 4 0 01b 2 1 2 3 BCLK cycles 0 10b 3 1 3 4 BCLK cycles 1 0 3 00b 1 1 1 2 BCLK cycles Multiplexed bu...

Page 184: ...ait States 2 Separate Bus One Wait State 1 1 WD Bus cycle 2 Bus cycle 1 3 Separate Bus Two Wait States 1 2 WD A A Bus cycle 3 Bus cycle 3 RD BCLK BCLK CSi RD Data Address CSi CSi RD Data Address RD WD...

Page 185: ...E 3 Multiplexed Bus Three Wait States 1 3 Bus cycle 4 Bus cycle 4 RD A Address Data RD ALE Bus cycle 3 2 Multiplexed Bus One or Two Wait States 1 2 Bus cycle 3 BCLK CSi BCLK CSi BCLK RD Data Address R...

Page 186: ...4 2 External Bus When a hardware reset power on reset or voltage monitor 0 reset is performed with a high level input on the CNVSS pin the internal ROM cannot be read 11 4 3 External Access Immediatel...

Page 187: ...s referred to as the CSi area 12 2 Registers Table 12 2 lists registers related to the memory expansion function Refer to 10 Processor Mode for the PM1 register Table 12 1 Memory Space Expansion Funct...

Page 188: ...bits PM15 to PM14 in the PM1 register are 11b 4 MB mode No register bits If necessary set to 0 The read value is 0 b7 b6 b5 b4 b1 b2 b3 Data Bank Register Symbol DBR Address 000Bh Bit Symbol Bit Name...

Page 189: ...rved external area 5 Notes 1 When the PM13 bit in the PM1 register is 0 15 KB of the internal RAM and 192 KB of the internal ROM can be used See the table below for addresses XXXXXh and YYYYYh 2 When...

Page 190: ...otes 1 See the table below for addresses XXXXXh and YYYYYh 2 When the PM10 bit is 0 this area is used as an external area when the bit is 1 this area is used as internal ROM data flash 3 When the PRG2...

Page 191: ...e CSi pin function differs depending on the area to be accessed 12 3 2 1 Addresses 04000h to 3FFFFh C0000h to FFFFFh The CSi signal is output from the CSi pin same operation as 1 MB mode except the la...

Page 192: ...s 0 15 KB of the internal RAM and 192 KB of the internal ROM can be used See the table below for addresses XXXXXh and YYYYYh 2 When the PM10 bit is 0 this area is used as an external area when the bit...

Page 193: ...able below for addresses XXXXXh and YYYYYh 2 When the PM10 bit is 0 this area is used as an external area when the bit is 1 this area is used as internal ROM data flash 3 When the PRG2C0 bit in the PR...

Page 194: ...the accessed address to be offset by 40000h allowing even data overlapping at a bank boundary to be accessed in succession In memory expansion mode where the PM13 bit is 1 each 512 KB bank can be acce...

Page 195: ...1 0 1 0 1 0 1 0 1 0 0 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BFFFFh 40000h BF...

Page 196: ...1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1...

Page 197: ...Fh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0000h FFFFh 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1...

Page 198: ...f ports Total 88 CMOS output 85 N channel open drain output 3 Input output VCC2 level P0 to P5 VCC1 level P6 to P10 Input output level Select input or output for each individual port by a program Sele...

Page 199: ...ction input A in Figure 13 1 P3_0 to P3_7 P4_0 to P4_3 P5_0 to P5_4 P5_6 N A N A N A P0_0 to P0_7 P2_0 to P2_3 P2_6 P2_7 P10_0 to P10_3 N A Available N A P5_5 Available HOLD N A N A P8_2 to P8_4 P9_1...

Page 200: ...g input B in Figure 13 2 P9_6 N A Available P4_4 P6_0 P6_4 P7_3 to P7_5 P8_1 P9_0 P9_2 Available N A P5_7 Available RDY N A P9_5 Available Available Pull up selection Data bus Port latch Note 1 Output...

Page 201: ...n input A in Figure 13 3 Analog input B in Figure 13 3 P1_4 N A N A P1_5 to P1_7 Available N A PCR0 bit in the PCR register Data bus Port latch Pull up selection Note 1 Direction register Input to res...

Page 202: ...al function input A in Figure 13 4 Analog input B in Figure 13 4 P1_0 Available N A Pull up selection Data bus Note 1 Output from peripheral functions Enables peripheral function output PCR0 bit in th...

Page 203: ...input A in Figure 13 5 Analog input B in Figure 13 5 P1_1 to P1_3 Available N A Pull up selection Data bus Note 1 Output from peripheral functions Enables peripheral function output PCR0 bit in the PC...

Page 204: ...gure 13 6 Analog input B in Figure 13 6 P4_5 P6_1 to P6_3 P6_5 to P6_7 P7_2 P7_6 P7_7 P8_0 Available N A Pull up selection Data bus Port latch Note 1 Output from peripheral functions Enables periphera...

Page 205: ...ction input A in Figure 13 7 Analog input B in Figure 13 7 P4_6 P4_7 Available N A Pull up selection Data bus Port latch Note 1 Output from peripheral functions Enables peripheral function output CMOS...

Page 206: ...s N channel Open Drain Output Port Peripheral Function I O Peripheral function input A in Figure 13 8 Analog input B in Figure 13 8 P7_0 P7_1 Available N A Data bus Port latch Note 1 Input to respecti...

Page 207: ...igure 13 9 I O Ports NMI Data bus Port latch Output from peripheral functions Enables peripheral function output Note 2 SD input NMI interrupt input Digital filter PM24 bit NMI enabled CEC input PM24...

Page 208: ...ion Note 1 Data bus Note 1 fC Rf Rd CM04 bit XCIN XCOUT CM04 bit CM04 bit in the CM0 register P8_6 P8_7 Direction register Pull up selection CM04 bit in the CM0 register Direction register Port latch...

Page 209: ...Figure 13 11 P9_3 P9_4 Available N A Data bus Direction register Port latch Pull up selection Analog output Bits DA0E and DA1E D A output enabled Bits DA0E and DA1E in the DACON register D A output e...

Page 210: ...Group 13 Programmable I O Ports Figure 13 12 I O Pins BYTE BYTE signal input Note 1 CNVSS CNVSS signal input Note 1 RESET RESET signal input Note 1 Internal signal Note 1 symbolizes a parasitic diode...

Page 211: ...Ah Port P4 Direction Register PD4 00h 03EBh Port P5 Direction Register PD5 00h 03ECh Port P6 Register P6 XXh 03EDh Port P7 Register P7 XXh 03EEh Port P6 Direction Register PD6 00h 03EFh Port P7 Direct...

Page 212: ...is 1 pulled high and the direction bit is 0 input mode the corresponding pin is pulled high b7 b6 b5 b4 b1 b2 b3 Pull Up Control Register 0 Symbol PUR0 Address 0360h Bit Symbol Bit Name RW Reset Valu...

Page 213: ...he direction bit is 0 input mode the corresponding pin is pulled high In memory expansion and microprocessor modes pins are not pulled high although the bit values can be modified PU14 P6_0 to P6_3 pu...

Page 214: ...s pulled high PU21 P8_4 P8_6 P8_7 pull up b1 When the PU21 bit is 1 pulled high and the direction bit is 0 input mode the corresponding pin is pulled high The P8_5 pin is not pulled high b7 b6 b5 b4 b...

Page 215: ...nction PCR0 RW No register bits If necessary set to 0 The read value is undefined b2 b1 PCR5 RW PCR6 RW PCR7 RW INT6 input enable bit INT7 input enable bit Key input enable bit 0 Enabled 1 Disabled 0...

Page 216: ...rol pins A0 to A19 D0 to D15 CS0 to CS3 RD WRL WR WRH BHE ALE RDY HOLD HLDA and BCLK cannot be modified writing a value has no effect Since P7_0 P7_1 and P8_5 are N channel open drain ports when set t...

Page 217: ...A0 to A19 D0 to D15 CS0 to CS3 RD WRL WR WRH BHE ALE RDY HOLD HLDA and BCLK cannot be modified writing a value has no effect b7 b6 b5 b4 b1 b2 b3 b0 Bit Symbol Bit Name RW Function PDi_0 Port Pi_0 dir...

Page 218: ...1 NMI interrupt enabled it cannot be set to 0 by a program Change the NMIDF register before setting the PM24 bit to 1 NMI SD Digital Filter Register Symbol NMIDF Address 0369h Bit Symbol Bit Name RW R...

Page 219: ...pheral function A and peripheral function B share a pin input and output are as follows When the pin functions as input for peripheral functions A and B The same signal is input as an input signal for...

Page 220: ...3 14 NMI SD Digital Filter Operation Example 13 4 4 CNVSS Pin The built in pull up resistor of the CNVSS pin is activated after watchdog timer reset hardware reset power on reset or voltage monitor 0...

Page 221: ...ort to output mode and leaving it open be aware that the port remains in input mode until it is switched to output mode by a program after reset For this reason the voltage level on the pin becomes un...

Page 222: ...e level on the pin becomes undefined causing the power supply current to increase while the port remains in input mode Furthermore since the values of the direction registers can be changed by noise o...

Page 223: ...TB2SC register is 1 three phase output forcible cutoff by input on SD pin enabled the following pins become high impedance P7_2 CLK2 TA1OUT V P7_3 CTS2 RTS2 TA1IN V P7_4 TA2OUT W P7_5 TA2IN W P8_0 TA...

Page 224: ...BC 1 Interrupt by the MCU hardware Non maskable interrupt 2 Peripheral function INT timers etc Refer to 14 6 2 Relocatable Vector Tables Interrupt by the peripheral functions in the MCU Maskable inter...

Page 225: ...pt Control Register S2RIC XXXX X000b 0051h UART0 Transmit Interrupt Control Register S0TIC XXXX X000b 0052h UART0 Receive Interrupt Control Register S0RIC XXXX X000b 0053h UART1 Transmit Interrupt Con...

Page 226: ...Interrupt Control Register S7RIC XXXX X000b 007Bh I2C bus Interface Interrupt Control Register IICIC XXXX X000b 007Ch SCL SDA Interrupt Control Register SCLDAIC XXXX X000b 0205h Interrupt Source Selec...

Page 227: ...rocessor Mode Register 2 Symbol PM2 Address 001Eh Bit Symbol Bit Name RW b0 Reset Value XX00 0X01b b0 Function Reserved bit b2 b3 Set to 1 PM24 PM25 Set to 0 0 NMI interrupt disabled 1 NMI interrupt e...

Page 228: ...IR Interrupt request bit 0 Interrupt not requested 1 Interrupt requested RW b7 b4 No register bits If necessary set to 0 The read value is undefined b2 b1 b0 0 0 0 Level 0 interrupt disabled 0 0 1 Le...

Page 229: ...register to 0 falling edge i 0 to 5 When bits IFSR30 and IFSR31 in the IFSR3A register are 1 both edges set the POL bit in registers INT6IC and INT7IC to 0 falling edge Set the POL bit in the S3IC or...

Page 230: ...30 Reset Value 00h b0 Function IFSR31 IFSR34 0 One edge 1 Both edges RW RW RW 0 One edge 1 Both edges 0 UART5 transmission NACK 1 CEC2 INT6 interrupt polarity select bit INT7 interrupt polarity select...

Page 231: ...T7 transmission NACK 1 Remote control 1 IFSR22 Interrupt request source select bit 0 Not used 1 I2 C bus interface RW IFSR23 Interrupt request source select bit 0 Not used 1 SCL SDA RW IFSR24 Interrup...

Page 232: ...sure the corresponding POL bit in registers S3IC and S4IC is set to 0 falling edge b7 b6 b5 b4 b1 b2 b3 Interrupt Source Select Register Symbol IFSR Address 0207h Bit Symbol Bit Name RW Reset Value 00...

Page 233: ...Address match interrupt 1 enable bit 0 Interrupt disabled 1 Interrupt enabled No register bits If necessary set to 0 The read value is undefined RW RW 0 Interrupt disabled 1 Interrupt enabled b7 b6 b5...

Page 234: ...rrupt Register i i 0 to 3 Symbol Address Setting Range Function RW Address setting register for address match interrupt b19 to b0 RW 00000h to FFFFFh No register bits If necessary set to 0 The read va...

Page 235: ...Register Symbol PCR Address 0366h Bit Symbol RW Reset Value 0000 0XX0b b0 Bit Name Function PCR0 RW No register bits If necessary set to 0 The read value is undefined b2 b1 PCR5 RW PCR6 RW PCR7 RW INT...

Page 236: ...interrupt enabled it cannot be set to 0 by a program Change the NMIDF register before setting the PM24 bit to 1 NMI SD Digital Filter Register Symbol NMIDF Address 0369h Bit Symbol Bit Name RW Reset...

Page 237: ...le these interrupts The interrupt priority order cannot be changed by using the interrupt priority level Interrupt Software non maskable interrupt Hardware Undefined instruction UND instruction Overfl...

Page 238: ...A BRK interrupt occurs when the BRK instruction is executed 14 4 4 INT Instruction Interrupt An INT instruction interrupt occurs when the INT instruction is executed Software interrupt numbers 0 to 63...

Page 239: ...tails on this function refer to 8 Clock Generator 14 5 1 5 Voltage Monitor 1 Voltage Monitor 2 Interrupt The interrupt is generated by the voltage detector For details on the voltage detector refer to...

Page 240: ...ector Tables Interrupt Source Vector Table Addresses Address L to Address H Reference Undefined instruction UND instruction FFFDCh to FFFDFh M16C 60 M16C 20 M16C Tiny Series Software Manual Overflow I...

Page 241: ...Interface SI O3 and SI O4 SI O3 INT4 2 36 to 39 0024h to 0027h 9 UART2 start stop condition detection bus collision detection 4 40 to 43 0028h to 002Bh 10 23 Serial Interface UARTi i 0 to 2 5 to 7 DM...

Page 242: ...6 20 Real Time Clock 23 Serial Interface UARTi i 0 to 2 5 to 7 UART6 transmit NACK6 real time clock compare 2 4 188 to 191 00BCh to 00BFh 47 UART6 receive ACK6 2 192 to 195 00C0h to 00C3h 48 UART7 sta...

Page 243: ...pt not requested The IR bit can be set to 0 by a program Do not write 1 to this bit 14 7 1 3 Bits ILVL2 to ILVL0 and IPL Interrupt priority levels can be selected by setting bits ILVL2 to ILVL0 Table...

Page 244: ...1 within the CPU 3 Flags I D and U in the FLG register are set as follows The I flag is set to 0 interrupt disabled The D flag is set to 0 single step interrupt disabled The U flag is set to 0 ISP sel...

Page 245: ...l Interrupt is Accepted Table 14 10 IPL Level Set in IPL When Software or Special Interrupt is Accepted Interrupt Source Level Set in IPL Watchdog timer NMI oscillator stop restart detect voltage moni...

Page 246: ...ted by the U flag Otherwise it is the ISP Figure 14 6 Register Save Operation Address Contents of previous stack Stack SP SP value before interrupt request is accepted m m 1 m 2 m 3 m 4 Stack status b...

Page 247: ...edged For maskable interrupts peripheral function interrupts any priority level can be selected using bits ILVL2 to ILVL0 However if two or more maskable interrupts have the same priority level their...

Page 248: ...5 CEC2 UART5 receive ACK5 UART5 start stop condition detection bus collision detection CEC1 DMA2 INT1 UART7 receive ACK7 UART7 start stop condition detection bus collision detection remote control 0 T...

Page 249: ...equest Restored IPL 14 8 INT Interrupt The INTi interrupt i 0 to 7 is triggered by the edges of external inputs The edge polarity is selected using the IFSRi bit in the IFSR register or the IFSR30 or...

Page 250: ...key input interrupt request When using any pin from KI0 to KI3 for the key input interrupt do not use all four pins AN4 to AN7 as analog input pins While input to any pin from P10_4 to P10_7 is low i...

Page 251: ...its previous state by using the POP or similar instructions before the interrupt request was accepted and then use a jump instruction to return Refer to 14 7 5 Saving Registers for PC values saved to...

Page 252: ...ing program and determine the source of the interrupt Table 14 13 lists Bits Used for Non Maskable Interrupt Source Discrimination Table 14 13 Bits Used for Non Maskable Interrupt Source Discriminatio...

Page 253: ...r the first instruction after reset only all interrupts are disabled 14 13 3 NMI Interrupt When not using the NMI interrupt set the PM24 bit in the PM2 register to 0 NMI interrupt dis abled The NMI in...

Page 254: ...Procedure for Changing the Interrupt Generate Source Use the MOV instruction to set the IR bit to 0 interrupt not requested 3 Disable interrupts 2 3 Change the interrupt source including a mode chang...

Page 255: ...he internal bus and the instruction queue buffer Example 1 Using the NOP instruction to pause the program until the interrupt control register is modified INT_SWITCH1 FCLR I Disable interrupts AND B 0...

Page 256: ...cessary for the signal input to pins INT0 through INT7 regardless of the CPU operation clock If the POL bit in registers INT0IC to INT7IC bits IFSR7 to IFSR0 in the IFSR register or bits IFSR31 to IFS...

Page 257: ...ode wait mode bus hold None Watchdog timer counter refresh timing Reset refer to 6 Resets Write 00h and then FFh to the WDTR register Underflow Operation when the timer underflows Watchdog timer inter...

Page 258: ...DC 00XX XXXXb Note 1 When the CSPROINI bit in the OFS1 address is 0 the reset value becomes 1000 0000b b7 b6 b5 b4 b1 b2 b3 Voltage Monitor 2 Control Register Symbol VW2C Address 002Ch Bit Symbol Bit...

Page 259: ...ing Once counting starts do not change the CSPRO bit Condition to become 0 Reset when the CSPROINI bit in the OFS1 address is 1 This flag remains unchanged even if 0 is written by a program Conditions...

Page 260: ...Register WDTS The WDTS register is enabled when the WDTON bit in the OFS1 address is 1 watchdog timer is in a stopped state after reset b7 Watchdog Timer Refresh Register Symbol WDTR Address 037Dh RW...

Page 261: ...read bits WDC4 to WDC0 more than three times to determine the values b7 0 b6 b5 b4 b1 b2 b3 Watchdog Timer Control Register Symbol WDC Address 037Fh Bit Symbol Bit Name RW WDC0 Reset Value 00XX XXXXb...

Page 262: ...processor mode clear the internal ROM 15 3 1 Optional Function Select Address 1 OFS1 WDTON Watchdog timer start select bit b0 CSPROINI After reset count source protection mode select bit b7 Set the WD...

Page 263: ...low Count start conditions Set the WDTON bit in the OFS1 address to select the watchdog timer operation after reset WDTON bit is 1 watchdog timer is in stop state after reset The watchdog timer counte...

Page 264: ...ed even if 1 is written and the MCU does not enter stop mode Table 15 4 Watchdog Timer Specifications Count Source Protection Mode Enabled Item Specification Count source fOCO S The 125 kHz on chip os...

Page 265: ...stop restart detect interrupt voltage monitor 1 interrupt and voltage monitor 2 interrupt share an vector When using multiple functions read the detect flag in an interrupt process program to determin...

Page 266: ...10 Rev 2 10 Page 233 of 800 Jul 31 2012 M16C 64A Group 15 Watchdog Timer 15 6 Notes on the Watchdog Timer After the watchdog timer interrupt is generated use the WDTR register to refresh the watchdog...

Page 267: ...o UART2 UART5 to 7 reception ACK interrupt request 6 SI O3 SI O4 interrupt request 2 A D conversion interrupt request 1 Software trigger 1 Channel priority DMA0 DMA1 DMA2 DMA3 DMA0 takes precedence Tr...

Page 268: ...r SAR3 DMA3 forward address pointer DMA0 source pointer SAR0 DMA0 destination pointer DAR0 DMA0 forward address pointer DMA1 destination pointer DAR1 DMA1 source pointer SAR1 DMA1 forward address poin...

Page 269: ...DAR1 XXh 0195h XXh 0196h 0Xh 0198h DMA1 Transfer Counter TCR1 XXh 0199h XXh 019Ch DMA1 Control Register DM1CON 0000 0X00b 01A0h DMA2 Source Pointer SAR2 XXh 01A1h XXh 01A2h 0Xh 01A4h DMA2 Destination...

Page 270: ...direction this register can be written to at any time If the DAD bit is 1 and the DMAE bit is 1 DMA enabled the DMAi forward address pointer can be read from this register Otherwise the value written...

Page 271: ...transfer counter in either of the following cases The DMAE bit in the DMiCON register is set to 1 DMA enabled single transfer mode repeat transfer mode The DMAi transfer counter underflows repeat tra...

Page 272: ...DAD bit and or DSD bit to 0 address direction fixed DMAi Control Register i 0 to 3 Symbol DM0CON DM1CON DM2CON DM3CON Address Bit Symbol RW DMBIT Reset Value DMASL DMAS DMAE DSD RW RW RW RW DAD RW b7...

Page 273: ...Register i 0 to 3 Symbol DM0SL DM1SL DM2SL DM3SL Address 0398h 039Ah 0390h 0392h Bit Symbol RW Reset Value 00h 00h 00h 00h b0 b5 DMS RW Bit Name Function DSEL0 DSEL1 DSEL2 DSEL3 DSEL4 DMA request sour...

Page 274: ...on 1 0 1 0 0 b UART6 reception 1 0 1 0 1 b UART7 transmission 1 0 1 1 0 b UART7 reception 1 0 1 1 1 b 1 1 X X X b X 0 or 1 Do not set Table 16 4 Source of DMA Request DMA1 DSEL4 to DSEL0 DMS 0 Basic S...

Page 275: ...1 0 1 0 0 b UART6 reception 1 0 1 0 1 b UART7 transmission 1 0 1 1 0 b UART7 reception 1 0 1 1 1 b 1 1 X X X b X 0 or 1 Do not set Table 16 6 Source of DMA Request DMA3 DSEL4 to DSEL0 DMS is 0 Basic S...

Page 276: ...1 data transfers start immediately after a DMA request is generated so the DMAS bit in almost all cases is 0 when read in a program Read the DMAE bit to determine whether the DMAC is enabled When a DM...

Page 277: ...th an odd address the source read cycle increments by one bus cycle compared to a source address starting with an even address When a 16 bit unit of data is transferred with a 16 bit data bus and the...

Page 278: ...Source 1 BCLK Address bus RD signal WR signal Data bus CPU used CPU used Source Dummy cycle Destination Destination Destination Destination 1 Transfers are performed in 8 bit or 16 bit units and the t...

Page 279: ...n 1 1 1 1 Odd 1 1 1 1 8 bit BYTE high Even N A N A 1 1 Odd N A N A 1 1 16 bit transfers DMBIT 0 16 bit BYTE low Even 1 1 1 1 Odd 2 2 2 2 8 bit BYTE high Even N A N A 2 2 Odd N A N A 2 2 DMBIT Bit in t...

Page 280: ...on Example in Single Transfer Mode DMA CPU DMA CPU DMA CPU CPU Bus Undefined 02h 01h 00h FFh When a DMA transfer begins the DMAS bit becomes 0 Underflow Set to 0 by an interrupt request acknowledgemen...

Page 281: ...eat Transfer Mode Figure 16 4 Operation Example in Repeat Transfer Mode DMA CPU DMA CPU DMA CPU Bus Undefined 02h 01h 00h When a transfer begins the DMAS bit becomes 0 Underflow Set to 0 by an interru...

Page 282: ...d simultaneously the higher channel prioritized DMA0 is received first and data transfer starts After one DMA0 transfer is completed the bus access privilege is returned to the CPU When the CPU has co...

Page 283: ...ON sometimes becomes 1 DMA requested i 0 to 3 Therefore set the DMAS bit to 0 DMA not requested after the DMS bit or bits DSEL4 to DSEL0 in the DMiSL register are changed Refer to 14 13 Notes on Inter...

Page 284: ...set the value to be written to the DMAS bit to 1 to retain its state immediately before writing Similarly when writing to the DMAE bit with a read modify write instruction set the DMAS bit to 1 to ret...

Page 285: ...ther timers One shot timer mode The timer outputs a single pulse before it reaches the count 0000h Pulse width modulation mode PWM mode The timer outputs pulses of given width and cycle successively P...

Page 286: ...th TB5IN TMOD1 to TMOD0 00b 11b 10b 01b TA0TGH to TA0TGL i 0 to 4 TCK1toTCK0 TMOD1toTMOD0 Bits in the TAiMR register TAiTGH to TAiTGL Bits in the ONSF register or TRGSR register TCS7 to TCS0 Bits in r...

Page 287: ...t timer TMOD1 to TMOD0 10b Pulse width modulation programmable output TMOD1 to TMOD0 11b TAiIN Timer B2 overflow 1 Count source select TAj overflow 1 TAiS Toggle flip flop TAiOUT Decrement TAiUD TAk o...

Page 288: ...Xb 01D5h Timer A Waveform Output Function Select Register TAPOFS XXX0 0000b 01D8h Timer A Output Waveform Change Enable Register TAOW XXX0 X00Xb 0302h Timer A1 1 Register TA11 XXh 0303h XXh 0304h Time...

Page 289: ...t enabled in single chip mode 0 Selected by setting bits CM01 to CM00 in the CM0 register 1 Output f1 PCLK0 Timers A and B clock select bit clock source for timers A and B the dead time timer and mult...

Page 290: ...ct bit b6 b5 b4 0 0 0 f1TIMAB or f2TIMAB 0 0 1 f8TIMAB 0 1 0 f32TIMAB 0 1 1 f64TIMAB 1 0 0 Do not set 1 0 1 fOCO S 1 1 0 fC32 1 1 1 Do not set TCS5 RW RW TCS4 RW TCS6 RW TCS3 0 TCK0 TCK1 enabled TCS0...

Page 291: ...b1 b2 b3 Symbol PWMFS Address 01D4h Reset Value 0XX0 X00Xb b0 Function Bit Symbol Bit Name RW b7 RW Reserved bit 16 bit Pulse Width Modulation Mode Function Select Register Set to 0 RW PWMFS4 b3 Timer...

Page 292: ...mbol Bit Name RW No register bits If necessary set to 0 The read value is undefined Timer A Waveform Output Function Select Register TA3OUT output polar control bit RW RW POFS4 POFS3 TA4OUT output pol...

Page 293: ...TAiOUT output the falling edge when the POFSi bit is 1 The value before the update is reloaded when the TAiOW bit is 0 output waveform change disabled b7 b6 b5 b4 b1 b2 b3 Symbol TAOW Address 01D8h R...

Page 294: ...s not work the output level on the TAiOUT pin remains low and a timer Ai interrupt request is not generated b15 b8 b7 Symbol TA0 TA1 TA2 TA3 TA4 Address 0327h to 0326h 0329h to 0328h 032Bh to 032Ah 03...

Page 295: ...fj Count source frequency 0001h to FFFFh Programmable output mode WO When n is a setting value of TAi1 register and m is a setting value of TAi register high level duration m fj low level duration n f...

Page 296: ...1 trigger selected by setting bits TA0TGH to TA0TGL When bits TA0TGH to TA0TGL are 00b the active edge of input signals can be selected by setting the MR1 bit in the TA0MR register When bits TA0TGH to...

Page 297: ...ter When bits TAiTGH to TAiTGL are set to 01b 10b or 11b an event or a trigger occurs when an interrupt request of the selected timer is generated An event or trigger can occur while interrupts are di...

Page 298: ...g two phase pulse signal processing b7 b6 b5 b4 b1 b2 b3 Symbol UDF Address 0324h Reset Value 00h b0 Function Bit Symbol Bit Name RW Increment Decrement Flag RW 0 Decrement 1 Increment Timer A0 increm...

Page 299: ...033Ah Reset Value 00h b0 Function Bit Symbol Bit Name RW Timer Ai Mode Register i 0 to 4 Function varies with the operation mode MR1 RW MR2 RW MR3 RW TCK1 RW Function varies with operation mode TCK0 R...

Page 300: ...nt source from n reloads a value in the reload register at the next count source after the value becomes 0000h and continues decrementing When incrementing the counter reloads a value in the reload re...

Page 301: ...ls Main clock divided by 1 no division PLL clock divided by 1 no division fOCO S divided by 1 no division Table 17 5 Timer A Count Sources Count Source Bit Setting Value Remarks PCLK0 TCS3 TCS2 to TCS...

Page 302: ...n Set the TAiS bit to 0 stop counting Interrupt request generation timing Timer underflow TAiIN pin function I O port or gate input TAiOUT pin function I O port or pulse output Read from timer The cou...

Page 303: ...t source TAPOFS POFSi Select the output polarity when the MR0 bit in the TAiMR register is 1 pulse output TAOW TAiOW Set to 0 TAi1 15 to 0 does not need to be set TABSR TAiS Set to 1 when starting cou...

Page 304: ...ol Bit Name RW Timer Mode Timer Ai Mode Register i 0 to 4 RW b1 b0 0 0 Timer mode Operation mode select bit RW TMOD1 TMOD0 TCK0 MR3 RW Set to 0 in timer mode TCK1 RW Count source select bit b7 b6 0 0...

Page 305: ...ming diagram assumes the following The MR0 bit in the TAiMR register 1 pulse output Bits MR2 to MR1 in the TAiMR register 10b counts while a low level signal is applied to the TAiIN pin The TAi regist...

Page 306: ...register value and continues counting When selecting free run type the timer continues counting without reloading Number of counts When selecting reload type FFFFh n 1 for increment n 1 for decrement...

Page 307: ...ting unnecessary TAPOFS POFSi Select the output polarity when the MR0 bit in the TAiMR register is 1 pulse output TAOW TAiOW Set to 0 TAi1 15 to 0 setting unnecessary TABSR TAiS Set to 1 when starting...

Page 308: ...sing Timer Ai Mode Register i 0 to 4 RW MR1 Count polarity select bit 0 Counts falling edge of an external signal 1 Counts rising edge of an external signal RW TCK0 Count operation type select bit 0 R...

Page 309: ...e output The TCK0 bit in the TAiMR register 0 reload type TAiUD bit in the UDF register 0000h TAiOUT output Low level output at count stop Output inverted at underflow or overflow IR bit in the TAiIC...

Page 310: ...lecting free run type the timer continues counting without reloading Number of counts When selecting reload type FFFFh n 1 when incrementing n 1 when decrementing n setting value of the TAi register 0...

Page 311: ...0 TACS0 to TACS2 7 to 0 setting unnecessary TAPOFS POFSi Set to 0 TAOW TAiOW Set to 0 TAi1 15 to 0 setting unnecessary TABSR TAiS Set to 1 when starting counting Set to 0 when stopping counting ONSF...

Page 312: ...0h b0 Function Bit Symbol Bit Name RW Event Counter Mode When Using Two Phase Pulse Signal Processing Timer Ai Mode Register i 2 to 4 MR1 TCK0 Count operation type select bit 0 Reload type 1 Free run...

Page 313: ...ile the input signal to the TAkOUT pin k 3 4 is high the timer increments at both rising and falling edges of the input signal to pins TAkOUT and TAkIN If the phase relationship is such that the input...

Page 314: ...ing edge can be selected as the active edge by setting the POL bit in the INT2IC register The Z phase pulse width must be equal to or greater than one clock cycle of the timer A3 count source The coun...

Page 315: ...rs External trigger input from the TAiIN pin Timer B2 overflow or underflow Timer Aj overflow or underflow j i 1 except j 4 if i 0 Timer Ak overflow or underflow k i 1 except k 0 if i 4 The TAiOS bit...

Page 316: ...he TAiMR register is 1 pulse output TAOW TAiOW Set to 0 TAi1 15 to 0 setting unnecessary TABSR TAiS Set to 1 when starting counting Set to 0 when stopping counting ONSF TAiOS Set to 1 when starting co...

Page 317: ...TA0MR to TA4MR Address 0336h to 033Ah Reset Value 00h b0 Function Bit Symbol Bit Name RW One Shot Timer Mode Timer Ai Mode Register i 0 to 4 RW b1 b0 1 0 One shot timer mode Operation mode select bit...

Page 318: ...operations 0000h TAiIN input TAiOUT output High level output at count start IR bit in the TAiIC register Retrigger while counting Reload and stop counting when 0000h is set n After retrigger n 1 Reloa...

Page 319: ...set value of the TAi register lower address n set value of the TAi register upper address fj count source frequency Count start condition The TAiS bit of the TABSR register is set to 1 start counting...

Page 320: ...count source TAPOFS POFSi Select the output polarity TAOW TAiOW Set to 0 TAi1 15 to 0 setting unnecessary TABSR TAiS Set to 1 when starting counting Set to 0 when stopping counting ONSF TAiOS Set to 0...

Page 321: ...t Value 00h b0 Function Bit Symbol Bit Name RW Pulse Width Modulation PWM Mode Timer Ai Mode Register i 0 to 4 RW b1 b0 1 1 PWM mode or programmable output mode Operation mode select bit RW TMOD1 TMOD...

Page 322: ...ten 65535 n 65535 65535 Count stopped Becomes 0 by a program Count stopped Low level output at count stop Interrupt not requested n 65535 n n fj 65535 fj Set to 0 by accepting an interrupt request or...

Page 323: ...TAiS bit in the TABSR is the trigger The MR3 bit in the TAiMR register 1 8 bit PWM mode 0000h TAiOUT output IR bit in the TAiIC register TAiS bit in the TABSR register TAi register Operates as an 8 b...

Page 324: ...unt start conditions The TAiS bit of the TABSR register is set to 1 start counting The TAiS bit is 1 and external trigger input from the TAiIN pin The TAiS bit is 1 and one of the following external t...

Page 325: ...iOW Set to 0 to disable output waveform change and set to 1 to enable output waveform change TAi1 15 to 0 Set a low level pulse width 2 TABSR TAiS Set to 1 when starting counting Set to 0 when stoppin...

Page 326: ...36h to 033Ah Reset Value 00h b0 Function Bit Symbol Bit Name RW Programmable Output Mode Timer Ai Mode Register i 1 2 4 RW b1 b0 1 1 PWM mode or programmable output mode Operation mode select bit RW T...

Page 327: ...e TABSR register n1 Count stopped Set to 0 by a program Count stopped m1 m1 fj Set to 0 by accepting an interrupt request or by a program The rising edge of the TAiIN pin input is the trigger Count st...

Page 328: ...de or programmable output mode Make sure to follow the procedure below when setting the TMOD1 bit to 1 Refer to 14 13 Notes on Interrupts for details 1 Set bits ILVL2 to ILVL0 in the TAiIC register to...

Page 329: ...ccurs when an interrupt request of the selected timer is generated An event or trigger occurs while an interrupt is disabled because an interrupt request signal is generated regardless of the I flag I...

Page 330: ...ts a high level signal when it is 1 After one cycle of the CPU clock the IR bit in the TAiIC register becomes 1 interrupt requested 17 5 4 2 Delay between the Trigger Input and Timer Output As the one...

Page 331: ...the timer Ai interrupt IR bit set the IR bit to 0 by a program after the changes listed above are made 17 5 5 2 Stop While Counting When setting the TAiS bit to 0 count stopped during PWM pulse output...

Page 332: ...utput mode To use the timer Ai interrupt IR bit set the IR bit to 0 by a program after the changes listed above are made 17 5 6 2 Stop While Counting When setting the TAiS bit to 0 count stopped durin...

Page 333: ...r mode The timer counts an internal count source Event counter mode The timer counts pulses from an external device or overflows and underflows of other timers Pulse period pulse width measurement mod...

Page 334: ...0b Timer mode 10b Pulse period pulse width measurement mode 00b Timer mode 10b Pulse period pulse width measurement mode 00b Timer mode 10b Pulse period pulse width measurement mode 00b Timer mode 10b...

Page 335: ...ter TBiS Bits in the TABSR register or TBSR register TCS0 to TCS7 Bits in the registers TBCS0 to TBCS3 PPWFS12 to PPWFS10 Bits in the PPWFS1 register PPWFS22 to PPWFS20 Bits in the PPWFS2 register TCK...

Page 336: ...1 Register TB31 XXh 01E1h XXh 01E2h Timer B4 1 Register TB41 XXh 01E3h XXh 01E4h Timer B5 1 Register TB51 XXh 01E5h XXh 01E6h Pulse Period Pulse Width Measurement Mode Function Select Register 2 PPWF...

Page 337: ...bit enabled in single chip mode 0 Selected by setting bits CM01 to CM00 in the CM0 register 1 Output f1 PCLK0 Timers A and B clock select bit clock source for timers A and B the dead time timer and m...

Page 338: ...urement result can be read by reading the TBi register when bits PPWFS12 to PPWFS10 in the PPWFS1 register and bits PPWFS22 to PPWFS20 in the PPWFS2 register are 0 While counting the counter value can...

Page 339: ...result can be read by reading the TBi 1 register When these bits are 0 the value in this register is undefined b15 b7 b7 b0 Setting Range Mode Function RW b8 b0 0000h to FFFFh Measures a pulse period...

Page 340: ...ent mode function select bit PPWFS12 RW 0 Measurement result is stored in the TB2 register The TB21 register is not used 1 The counter value is read from the TB2 register Measurement result is stored...

Page 341: ...2 enabled TBi count source option specified bit b7 b4 No register bits If necessary set to 0 The read value is undefined b7 b6 b5 b4 b1 b2 b3 Symbol TBCS0 TBCS2 Address 01C8h 01E8h Reset Value 00h 00h...

Page 342: ...RW RW RW RW TA4S RW TA3S Timer B0 count start flag Timer B1 count start flag TB1S Timer A4 count start flag Timer A1 count start flag TA1S RW Timer A2 count start flag RW TA2S Timer A0 count start fl...

Page 343: ...with the operation mode b1 b0 0 0 Timer mode 0 1 Event counter mode 1 0 Pulse period measurement mode Pulse width measurement mode 1 1 Do not set Operation mode select bit RW RW TMOD1 TMOD0 Function...

Page 344: ...n the reload register at the next count source after the value becomes 0000h and continues decrementing The value written in the TBi register is reflected in the counter and the reload register at the...

Page 345: ...ils Main clock divided by 1 no division PLL clock divided by 1 no division fOCO S divided by 1 no division Table 18 4 Timer B Count Sources Count Source Bit Setting Value Remarks PCLK0 TCS3 TCS2 to TC...

Page 346: ...n timing Timer underflow TBiIN pin function I O port Read from timer Count value can be read by reading the TBi register Write to timer When not counting The value written to the TBi register is writt...

Page 347: ...0 in timer mode RW MR1 MR0 No register bit If necessary set to 0 The read value is undefined Write 0 in timer mode The read value is undefined in timer mode Count source select bit b7 b6 0 0 f1TIMAB o...

Page 348: ...unt stop condition Set the TBiS bit to 0 stop counting Interrupt request generation timing Timer underflow TBiIN pin function Count source input Read from timer Count value can be read by reading the...

Page 349: ...b3 b0 Function Bit Symbol Bit Name RW b4 No register bit If necessary set to 0 The read value is undefined RW b1 b0 0 1 Event counter mode Operation mode select bit RW TMOD1 TMOD0 RO MR3 Write 0 in ev...

Page 350: ...Set to 0 by accepting an interrupt request or by a program TBiIN input Count start Count stop by TBiS bit i 0 to 5 The above assumes the following Bits MR1 to MR0 in the TBiMR register 10b the fallin...

Page 351: ...surement pulse is input 1 Timer overflow The MR3 bit in the TBiMR register becomes 1 overflowed at the same time an overflow occurs TBiIN pin function Measurement pulse input Read from timer When bits...

Page 352: ...are 1 PPWFS1 to PPWFS2 PPWFS12 to PPWFS10 PPWFS22 to PPWFS20 Set to 1 to read the counter value while counting TBCS0 to TBCS3 7 to 0 Select the count source TABSR TBSR TBiS Set to 1 when starting coun...

Page 353: ...source select bit b7 b6 0 0 f1TIMAB or f2TIMAB 0 1 f8TIMAB 1 0 f32TIMAB 1 1 fC32 b4 No register bit If necessary set to 0 The read value is undefined MR3 RO Timer Bi overflow flag 0 No overflow 1 Ove...

Page 354: ...Transfer to the TBi register Measured value 3 Becomes 0000h Measured value 4 Measured value 3 Measured value 1 Undefined value Set to 0 by accepting an interrupt request or by a program Transfer to t...

Page 355: ...et to 0 by writing to the TBiMR register Transfer to the TBi register Measured value 3 Measured value 2 Becomes 0000h Transfer to the TBi register Measured value 1 Becomes 0000h Undefined value Measur...

Page 356: ...t the IFSR26 bit in the IFSR2A register to 0 timer B3 When using the timer B4 interrupt set the IFSR27 bit in the IFSR2A register to 0 timer B4 Table 18 11 Timer B Interrupt Related Registers Address...

Page 357: ...before it starts counting and after a value is set in the TBi register while not counting the set value is read 18 5 3 Timer B Event Counter Mode 18 5 3 1 Reading the Timer While counting the counter...

Page 358: ...ons between Count Start and the First Measurement When a count is started and the first active edge is input an undefined value is transferred to the reload register At this time a timer Bi interrupt...

Page 359: ...form of triangular wave modulation is output Output data is updated every cycle of the carrier wave and an output waveform is generated Sawtooth wave modulation mode Three phase PWM waveform of sawtoo...

Page 360: ...INV11 bit to 1 0001h to FFFFh fi Count source frequency f1TIMAB f2TIMAB f8TIMAB f32TIMAB f64TIMAB fOCO S fC32 Dead time width or no dead time p Setting value of the DTT register 01h to FFh fi Count so...

Page 361: ...g the TA4S bit to 0 signal is set to 0 When setting the TA1S bit to 0 signal is set to 0 When setting the TA2S bit to 0 signal is set to 0 Trigger Trigger Trigger TA4 register TA41 register TA1 regist...

Page 362: ...et the port direction bits which share pins to 0 input mode When not using the three phase output forced cutoff function input a high level signal to the SD pin 2 Set the port direction bits which sha...

Page 363: ...gister TA21 XXh 0305h XXh 0306h Timer A4 1 Register TA41 XXh 0307h XXh 0308h Three Phase PWM Control Register 0 INVC0 00h 0309h Three Phase PWM Control Register 1 INVC1 00h 030Ah Three Phase Output Bu...

Page 364: ...TA11 TA21 and TA41 are used in three phase mode 1 of triangular wave modulation mode When the INV15 bit in the INVC1 register is set to 0 dead time enabled some high and low side turn on signals whos...

Page 365: ...ter b7 b6 b5 b4 b1 b2 b3 Three Phase PWM Control Register 0 Symbol INVC0 Address 0308h Bit Symbol Bit Name RW INV00 Reset Value 00h RW b0 Function INV01 RW RW INV02 Three phase motor control timer fun...

Page 366: ...f the INV06 Bit Item INV06 is 0 INV06 is 1 Mode Triangular wave modulation mode Sawtooth wave modulation mode Transfer timing from registers IDB0 and IDB1 to three phase output shift register Transfer...

Page 367: ...ecrements whenever timer B2 underflows Enabled INV13 bit Disabled Enabled when INV11 is 1 and INV06 is 0 b7 b6 b5 b4 b1 b2 b3 Three Phase PWM Control Register 1 Symbol INVC1 Address 0309h Bit Symbol B...

Page 368: ...of the following conditions are met set the INV16 bit to 1 rising edge of the three phase output shift register output The INV15 bit is 0 dead time timer enabled Bits Dij and DiBj always have differe...

Page 369: ...s set to 0 dead time enabled No dead time can be set when the INV15 bit is set to 1 dead time disabled Select a trigger by the INV16 bit in the INVC1 register and a count source by the INV12 bit in th...

Page 370: ...er start do not set the ICTB2 register when timer B2 underflows When bits INV01 to INV00 are 11b the first interrupt is generated when timer B2 underflows n 1 times if a setting value in the ICTB2 cou...

Page 371: ...or control timer output is disabled INV03 bit in the INVC0 register becomes 0 Then the target pins become high impedance regardless of the functions those pins are using After a forced cutoff input a...

Page 372: ...t level at IDW pin is retained 0 Low level 1 High level W phase position data retain bit PDRW RO Select polarity of a retain trigger When the INV14 bit is 0 active low 0 Falling edge of high side outp...

Page 373: ...ort P8_1 output function select bit Port Function Control Register PFC1 RW 0 I O port P8_0 1 Three phase PWM output U phase output Port P8_0 output function select bit PFC0 RW 0 I O port P7_3 1 Three...

Page 374: ...is stopped also generates a trigger for timers A1 A2 and A4 The frequency of timer B2 interrupt requests can be selected for three phase motor control timers In triangular wave modulation three phase...

Page 375: ...ontrol timer output enabled i U V or W j 0 1 During the period other than dead time the high and low side output signals always output opposite level signals If either of the conditions above is not m...

Page 376: ...r The INV03 bit in the INVC0 register becomes 0 three phase motor control timer output disabled The INV05 bit in the INVC0 register becomes 1 simultaneous conduction detected Pins U U V V W and W beco...

Page 377: ...The functions of the three phase PWM waveform output pins can be protected from being rewritten due to an unexpected program operation To prevent rewrite follow these steps 1 Set the TPRC0 bit to 1 2...

Page 378: ...pin input is sampled for every sampling clock When the same sampled level is detected three times in a row the level is transferred to the internal circuit Refer to 13 4 3 NMI SD Digital Filter To ret...

Page 379: ...is generated the state of the IDU pin is transferred to the PDRU bit in the PDRF register The value is retained until the next trigger of the U phase waveform output Figure 19 5 shows Position Data R...

Page 380: ...n Setting value of the TAi register 0001h to FFFFh fi Count source frequency f1TIMAB f2TIMAB f8TIMAB f32TIMAB f64TIMAB fOCO S fC32 Differences from three phase mode 1 Reference cycle Timer B2 cycle on...

Page 381: ...isabled INV16 Select a trigger for the dead time timer 7 Set to 0 IDB0 IDB1 5 to 0 Set the output logic of the three phase output shift registers DTT 7 to 0 Set the dead time ICTB2 3 to 0 Set the freq...

Page 382: ...nting TB0S Not used for three phase motor control timer TB1S Not used for three phase motor control timer TB2S Set to 1 when starting counting and to 0 when stopping counting TA1MR TA2MR TA4MR TMOD1 t...

Page 383: ...ve assumes the following In the INVC1 register The INV16 bit is 1 the dead time timer is triggered on the rising edge of the three phase output shift register The INV15 bit is 0 dead time timer enable...

Page 384: ...lling edge of one shot pulse for timers A1 A2 and A4 followed by the values set in the IDB1 register Consequently the three phase PWM output changes Afterward the values in registers IDB0 and IDB1 alt...

Page 385: ...S fC32 Differences from three phase mode 0 Reference cycle Twice the cycle of timer B2 cycle of the carrier wave Timer B2 reload timing Select either of the following Timer B2 underflow Timer A outpu...

Page 386: ...rrier wave state detect flag INV14 Select the active level either active high or active high INV15 Select dead time enabled or disabled INV16 Select a trigger for the dead time timer 7 Set to 0 IDB0 I...

Page 387: ...0 when stopping counting TA3S Not used for three phase motor control timer TA4S Set to 1 when starting counting and to 0 when stopping counting TB0S Not used for three phase motor control timer TB1S...

Page 388: ...00 are 11b and the ICTB2 register is 1h timer B2 interrupt at timer B2 underflow while the timer A1 reload control signal is 1 In the INVC1 register The INV16 bit is 1 the dead time timer is triggered...

Page 389: ...while timer A1 is stopped and the value is inverted at every start trigger signal for timers A1 A2 and A4 Thus if the cycle of the carrier wave starts at the first timer B2 underflow the first half co...

Page 390: ...rom the next carrier wave cycle Figure 19 8 shows Update Timing of Registers TAi and TAi1 in Three Phase Mode 1 Figure 19 8 Update Timing of Registers TAi and TAi1 in Three Phase Mode 1 TAi register a...

Page 391: ...the IDB1 register become output signals for each phase internal signal and consequently the three phase PWM output changes Afterward the values in registers IDB0 and IDB1 alternately become an output...

Page 392: ...2TIMAB f64TIMAB fOCO S fC32 Differences from triangular wave modulation mode Reference cycle Timer B2 cycle cycle of the carrier wave Timer B2 reload timing Timer B2 underflow Three phase PWM waveform...

Page 393: ...r the dead time timer INV13 Disabled INV14 Select the active level either active high or active high INV15 Select dead time enabled or disabled INV16 Select a trigger for the dead time timer 7 Set to...

Page 394: ...and to 0 when stopping counting TA3S Not used for three phase motor control timer TA4S Set to 1 when starting counting and to 0 when stopping counting TB0S Not used for three phase motor control timer...

Page 395: ...trigger for timers A1 A2 and A4 The INV15 bit is 0 dead time timer enabled The INV16 bit is 0 the dead time timer is triggered on the falling edge of timers A4 A1 and A2 one shot pulse The ICTB2 regi...

Page 396: ...nal and consequently the three phase PWM output changes Then the following two actions are repeated 1 The setting levels are transferred to the three phase output shift register by a transfer trigger...

Page 397: ...st is generated at the falling edge of timer Ai one shot pulse internal signal i 1 2 4 Refer to 14 7 Interrupt Control for details of interrupt control Table 19 20 lists Timer A1 A2 and A4 Interrupt R...

Page 398: ...efer to 17 5 Notes on Timer A and 18 5 Notes on Timer B 19 5 2 Influence of SD When a low level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 three phase output forci...

Page 399: ...Count start condition 1 count started is written to the TSTART bit in the RTCCR1 register Count stop condition 0 count stopped is written to the TSTART bit in the RTCCR1 register Interrupt request ge...

Page 400: ...Bit in the RTCCHR register RTCWK Bits WK2 to WK0 in the RTCWK register RTCHR Bits HR11 to HR10 and HR03 to HR00 in the RTCHR register RTCMIN Bits MN12 to MN10 and MN03 to MN00 in the RTCMIN register R...

Page 401: ...lock Hour Data Register RTCHR XX00 0000b 0343h Real Time Clock Day Data Register RTCWK XXXX X000b 0344h Real Time Clock Control Register 1 RTCCR1 0000 X00Xb 0345h Real Time Clock Control Register 2 RT...

Page 402: ...d the following bits when the BSY bit is 0 not while data is updated Bits SC12 to SC10 and SC03 to SC00 in the RTCSEC register Bits MN12 to MN10 and MN03 to MN00 in the RTCMIN register Bits HR11 to HR...

Page 403: ...to MN00 in the RTCMIN register when bits TSTART and TCSTF in the RTCCR1 register are both 0 count stopped Read these bits when the BSY bit in the RTCSEC is 0 not while data is updated b7 b6 b5 b4 b1...

Page 404: ...HR10 and HR03 to HR00 in the RTCHR register when bits TSTART and TCSTF in the RTCCR1 register are both 0 count stopped Read these bits when the BSY bit in the RTCSEC register is 0 not while data is u...

Page 405: ...to bits WK2 to WK0 in the RTCWK register when bits TSTART and TCSTF in the RTCCR1 register are both 0 count stopped Read these bits when the BSY bit in the RTCSEC register is 0 not while data is upda...

Page 406: ...0 count stopped It takes the time for up to three cycles of the count source until the TCSTF bit becomes 0 after setting the TSTART bit to 0 During this time do not access registers associated with th...

Page 407: ...00 in the RTCHR register are 12 to 23 The RTCPM bit changes as follows while counting Becomes 0 when the RTCPM bit is 1 p m while the clock increments from 11 59 59 23 59 59 for 24 hour mode to 00 00...

Page 408: ...cessary set to 0 The read value is undefined Compare mode select bit b6 b5 0 0 No compare mode 0 1 Compare mode 1 1 0 Compare mode 2 1 1 Compare mode 3 SEIE RW Periodic interrupt triggered every secon...

Page 409: ...RTCCHR register set bits SEIE MNIE and HRIE to 1 Table 20 4 Periodic Interrupt Sources Factor Interrupt Source Interrupt Enable Bit Periodic interrupt triggered every week Value in RTCWK register is...

Page 410: ...the PM2 register to 1 peripheral clock fC provided Refer to 8 Clock Generator for details on fC b7 0 b6 b5 b4 b1 b2 b3 Real Time Clock Count Source Select Register Symbol RTCCSR Address 0346h Bit Sym...

Page 411: ...b6 b4 Set a value between 00 and 59 by the BCD code Write to these bits when the BSY bit in the RTCSEC register is 0 not while data is updated b7 b6 b5 b4 b1 b2 b3 Real Time Clock Second Compare Data...

Page 412: ...it b6 b4 Set a value between 00 and 59 by the BCD code Write to these bits when the BSY bit in the RTCSEC register is 0 not while data is updated b7 b6 b5 b4 b1 b2 b3 Real Time Clock Minute Compare Da...

Page 413: ...a m p m compare bit b6 This bit is enabled when the H12H24 bit in the RTCCR1 register is either 0 12 hour mode or 1 24 hour mode When the H12H24 bit is 1 set the following When bits HCMP11 to HCMP10...

Page 414: ...te hour day and week When a periodic interrupt is generated the IR bit in the RTCTIC register becomes 1 interrupt request Figure 20 3 shows Real Time Clock Basic Operating Example Figure 20 4 shows Ti...

Page 415: ...TCMIN RTCHR and RTCWK Setting of RTCCR2 register TSTART bit in RTCCR1 register 1 TCSTF bit in RTCCR1 register 1 RTCTIC register 00h RTCCIC register 00h Setting of registers RTCTIC and RTCCIC IR bit 0...

Page 416: ...egister 00h Setting of registers RTCTIC and RTCCIC IR bit 0 select interrupt priority level Select interrupt source Start real time clock operation Confirmation of RTCPM bit in RTCCR1 register and reg...

Page 417: ...The RTCPM bit in the RTCCR1 register 2 Bits for compare data are as follows Bits SCMP12 to SCMP10 and SCMP03 to SCMP00 in the RTCCSEC register Bits MCMP12 to MCMP10 and MCMP03 to MCMP00 in the RTCCMIN...

Page 418: ...k to the reset value and counting stops Compare match interrupt request generated RTCMIN RTCHR RTCPM Compare Compare Compare Values of RTCPM RTCHR RTCMIN RTCSEC and count operation 0 01 23 43 Values o...

Page 419: ...COUT pin the state before stop is retained Set to 0 by a program The state before stop is retained Count started Count stopped 46 Undefined 0 RTCPM bit BSY bit Bit in RTCSEC register RTCSEC Bits SC12...

Page 420: ...RTCCR2 are 1 compare by seconds minutes and hours Interrupt enabled y Bits SCMP12 to SCMP10 and SCMP03 to SCMP00 in the RTCCSEC register are 4 and 5 respectively second setting 45 Bits MCMP12 to MCMP1...

Page 421: ...n the RTCCR2 register are 1 compare by seconds minutes and hours Interrupt enabled y Bits SCMP12 to SCMP10 and SCMP03 to SCMP00 in the RTCCSEC register are 4 and 5 respectively second setting 45 Bits...

Page 422: ...e RTCCR2 register are 1 compare by seconds minutes and hours Interrupt enabled y Bits SCMP12 to SCMP10 and SCMP03 to SCMP00 in the RTCCSEC register are 4 and 5 respectively second setting 45 Bits MCMP...

Page 423: ...interrupt control Table 20 5 lists Real Time Clock Interrupt Associated Registers The real time clock shares interrupt vectors and interrupt control registers with other peripheral functions To use pe...

Page 424: ...after setting the TSTART bit to 0 During this time do not access registers associated with the real time clock other than the TCSTF bit Note 1 Registers associated with the real time clock RTCSEC RTC...

Page 425: ...ing to Figure 20 11 Time Data Reading Figure 20 11 Time Data Reading Using read results if they are the same value twice 1 Read the values necessary from time data bits 2 Read the same bit as 1 and co...

Page 426: ...shows Block Diagram of PWM and Table 21 2 lists I O Ports Table 21 1 PWM Specifications Item Specification Resolution 8 bits Count source f1 divided by 2 4 8 or 16 PWM Cycle Unit s m PWMPREi register...

Page 427: ...MPRE0 00h 0373h PWM0 Register PWMREG0 00h 0374h PWM1 Prescaler PWMPRE1 00h 0375h PWM1 Register PWMREG1 00h 0376h PWM Control Register 1 PWMCON1 00h PWM0 register prelatch The above shows an example bl...

Page 428: ...source select bit b7 b6 Set these bits to select a count source for the PWMi prescaler Prescalers PWM0 and PWM1 share the same count source b7 0 0 0 b6 b5 b4 b1 b2 b3 PWM Control Register 0 Symbol PW...

Page 429: ...gister latch and the PWMi register and then the associated PWMi waveform is output When rewriting the PWMPREi and PWMREGi register values while the PWMENi bit in the PWMCON1 register is 0 PWMi output...

Page 430: ...al function 1 1 0 PWMi output level maintained 2 1 PWMi pulse output 1 0 0 or 1 I O port or pin for other peripheral function I O port or pin for other peripheral function 1 1 0 PWMi output level main...

Page 431: ...i bit in the PWMCON1 register is changed from 1 PWMi output enabled to 0 PWMi output disabled during PWMi output Registers PWMPREi and PWMREGi retain the value before the PWMi output is disabled When...

Page 432: ...ister latch 00h n n FFh High level is output in this cycle when PWMi register latch is FFh n 28 1 m 1 fj m 1 n fj PWMi prescaler latch m n1 28 1 m1 1 fj PWMENi bit in the PWMCON1 register PWMi prescal...

Page 433: ...64 Count operation Increment Operation modes Pattern match mode Determines that external pulse matches specified pattern Input capture mode Measures width and period of external pulse Pattern match mo...

Page 434: ...EN PMC0RBIT PMC0 PMCiD0PMIN PMCiD0PMAX PMCiD1PMIN PMCiD1PMAX CPFLG i 0 1 INFLG CEFLG Bits in registers PMC1CON2 and PMC0CON2 REFLG DRFLG PTHDFLG PTD0FLG PTD1FLG Bits in registers PMC0STS and PMC1STS S...

Page 435: ...n bits sharing pins to 0 input mode Divided by 8 Divided by 4 00b 01b 10b 11b 00b 01b 10b 11b Sampling clock of PMC1 digital filter 00b 01b 10b 11b PMC0CON3 register CSRC1 to CSRC0 f1 Timer B1 underfl...

Page 436: ...r Pattern Set Register Min PMC0HDPMIN 0000 0000b D081h XXXX X000b D082h PMC0 Header Pattern Set Register Max PMC0HDPMAX 0000 0000b D083h XXXX X000b D084h PMC0 Data 0 Pattern Set Register Min PMC0D0PMI...

Page 437: ...ter 3 PMC1CON3 00h 01FCh PMC1 Status Register PMC1STS X000 X00Xb 01FDh PMC1 Interrupt Source Select Register PMC1INT X000 X00Xb D094h PMC1 Header Pattern Set Register Min PMC1HDPMIN 0000 0000b D095h X...

Page 438: ...f necessary set to 0 Read as undefined value b7 b5 b7 b6 b5 b4 b1 b2 b3 Symbol PMC0CON0 Address 01F0h Reset Value 00h b0 Function Bit Symbol Bit Name RW PMC0 Function Select Register 0 0 Operation dis...

Page 439: ...if data 0 data 1 or special data is detected before the header is detected the following occur The REFLG bit in the PMCiSTS register becomes 1 error occurs Bits PTD0FLG PTD1FLG and SDFLG in the PMCiS...

Page 440: ...nters operate simultaneously b3 Reserved bit Set to 0 b5 b4 No register bits If necessary set to 0 Read as undefined value EXSDEN EXHDEN RW RW RW Special pattern detect block select bit 0 PMC0 1 PMC1...

Page 441: ...N Header pattern detect block select bit b7 Use these bits when PMC0 and PMC1 are linked and operated in pattern match mode Otherwise set them to 0 Set bits EXHDEN to EXSDEN to 01b or 10b when setting...

Page 442: ...overflow interrupt enable bit PSEL0 Input pin select bit PSEL1 b7 b6 0 0 Same as PMC1 Set bits PSEL1 to PSEL0 in the PMC1CON2 register to select 0 1 PMC0 pin 1 0 Do not set 1 1 Do not set RW RW RO RO...

Page 443: ...Measurement timing selected by bits TYP1 to TYP0 in the PMCiCON1 register Condition to become 1 Counter overflow the counter becomes 0000h from FFFFh PSEL1 PSEL0 Input pin select bit b7 b6 Change thes...

Page 444: ...1 0 fC 1 1 Timer B2 underflow RW RW CSRC1 CDIV0 Count source divisor select bit b7 b6 0 0 No division 0 1 Divided by 8 1 0 Divided by 32 1 1 Divided by 64 CDIV1 RW Mode select bit b3 b2 b1 b0 0 0 0 0...

Page 445: ...buffer full 48 bits received PTHDFLG Header pattern match flag 0 Not match 1 Match RO RO PTD0FLG Data 0 pattern match flag 0 Not match 1 Match RO Data 1 pattern match flag PTD1FLG 0 Not match 1 Match...

Page 446: ...n the PMC0CON0 register Table 22 5 lists Conditions for Changing the REFLG Bit Table 22 5 Conditions for Changing the REFLG Bit Bit Setting 1 Conditions for Changing the REFLG Bit to 1 2 Conditions fo...

Page 447: ...3 Conditions to become 0 The EN bit in the PMCiCON0 register is 0 PMCi operation disabled The DRFLG bit in the PMCiSTS register changes from 0 to 1 The value of the PMC0RBIT register changes from 48 t...

Page 448: ...ary set to 0 Read as undefined value b3 No register bit If necessary set to 0 Read as undefined value b7 No register bit If necessary set to 0 Read as undefined value b7 b6 b5 b4 b1 b2 b3 Symbol PMC0I...

Page 449: ...cial data detection set registers PMCiHDPMIN and PMCiHDPMAX to 0000h Setting value n Minimum width maximum width of header or special data pattern Count source Symbol PMC0HDPMAX PMC1HDPMAX Address D08...

Page 450: ...0 pattern The PMCiD1PMIN register value The PMCiD0PMIN register value The PMCiD1PMAX register value The PMCiD0PMAX register value The above shows the case for independent operation For independent ope...

Page 451: ...register value PMCiD1PMIN register value PMCiD1PMAX register value Value other than 0000h Setting value n minimum width maximum width of data 0 1 pattern count source b7 Symbol PMC0D0PMIN PMC1D0PMIN...

Page 452: ...unt Register PMC0RBIT The bit position of the storing buffer is specified by counting detected data 0 or data 1 When the receive bit count exceeds 48 it returns to 1 The header and special data are no...

Page 453: ...hanges from 0 to 1 next frame reception starts the PMC0DATi register is sequentially overwritten from the first bit in the PMC0DAT0 register The header and special data are not stored When the EN bit...

Page 454: ...C0DAT0 register are compared CPEN Compare enable bit b4 When the CPEN bit is 1 compare enabled values from registers PMC0CPD and PMC0DAT0 are compared When storing received data if the compared result...

Page 455: ...3 PMC0 Compare Data Register PMC0CPD This register is enabled when the CPEN bit in the PMC0CPC register is 1 compare enabled Bits to be compared are selected by bits CPN2 to CPN0 in the PMC0CPC regist...

Page 456: ...gnal Receiver Block Diagram 3 3 PMCi Count Source When using fC set the PM25 bit in the PM2 register to 1 peripheral clock fC provided Refer to 8 Clock Generator for details of fC When using timer B1...

Page 457: ...tial cycles when the FIL bit in the PMCiCON0 register is 1 digital filter enabled that level is transferred to the internal circuit The sampling clock of the digital filter is the count source Select...

Page 458: ...ources Clock sources One of the following fC f1 Timer B2 underflow Count source of PMC1 One of the following fC f1 Timer B1 underflow Timer B2 underflow Division No division divided by 8 divided by 32...

Page 459: ...EXHDEN Set to 0 PMCiCON2 ENFLG Flag indicating PMC0 operated stopped Flag indicating PMC1 operated stopped INFLG Input signal flag Input signal flag CEFLG Not used Not used CEINT Set to 0 Set to 0 PS...

Page 460: ...atch flag interrupt PMC0CPC CPN0 Select bits to be compared when using compare function CPN1 CPN2 CPEN Set to 1 when using compare function PMC0CPD 0 to 7 Set compare value when using compare function...

Page 461: ...ion PMCiTIM register a b Count stops Count starts c Counter operation PMCiTIM register c a b Count stopped Count started e Counter operation PMCiTIM register c d e c d i 0 1 TYP1 to TYP0 Bits in the P...

Page 462: ...N bit in the PMC0CON0 register is 1 special data enabled special data can be detected When detecting special data set the HDEN bit in the PMC0CON0 register to 0 header disabled 22 3 2 3 Receive Data B...

Page 463: ...ared results match the CPFLG bit in the PMC0STS register becomes 1 compare match Figure 22 8 Receive Buffer and Compare Function 0000 0000b 0000 0000b 1111 0110b 0 4 Data 0 Data 0 Data 1 Data 1 Data 1...

Page 464: ...22 11 Pattern Match Mode Specifications Combined Operation Item Content PMC0 Circuit PMC1 Circuit Count sources Clock sources Count source of PMC1 One of the following fC f1 Timer B1 underflow Timer B...

Page 465: ...the same value as PMC0 TYP1 CSS Set to 0 EXSDEN Select block in which header and special pattern is detected EXHDEN PMCiCON2 ENFLG Flag indicating PMCi operated stopped Not used INFLG Input signal fla...

Page 466: ...when using compare function CPN1 CPN2 CPEN Set to 1 when using compare function PMC0CPD 0 to 7 Set compare value when using compare function PMCiHDPMIN 0 to 10 Set minimum value of header pattern or s...

Page 467: ...PMC0STS register becomes 1 error occurs Bits PTD0FLG PTD1FLG and SDFLG in the PMC0STS register remain unchanged Registers PMC0DAT0 to PMC0DAT5 remain unchanged 22 3 3 3 Status Flag and Interrupt When...

Page 468: ...1 to 8 bits of the remote control signal can be detected When using the compare function set the following Set the CPEN bit in the PMC0CPC register to 1 compare enabled Select bits to be compared by s...

Page 469: ...MC1 Circuit Count sources Clock sources One of the following fC f1 Timer B2 underflow Count source of PMC1 One of the following fC f1 Timer B1 underflow Timer B2 underflow Division No division divided...

Page 470: ...nter overflow flag CEINT Set to 1 when using counter overflow interrupt Set to 1 when using counter overflow interrupt PSEL0 Set to 01b Set to 10b PSEL1 PMCiCON3 CRE Set to 1 Set to 1 CFR Set to 1 Set...

Page 471: ...measure interrupt SDINT Set to 0 PMC0CPC CPN0 Set to 000b CPN1 CPN2 CPEN Set to 0 PMC0CPD 0 to 7 Set to 00h PMCiHDPMIN 0 to 10 Set to 0000h Set to 0000h PMCiHDPMAX 0 to 10 Set to 0000h Set to 0000h P...

Page 472: ...n an interrupt request is accepted or by setting the bit to 0 PMCiTIM register IR bit IR bit IR bit PMCiTIM register PMCiTIM register CEFLG bit d Bits TYP1 to TYP0 are 10b pulse width measurement i 0...

Page 473: ...rcuit PMC1 Circuit Count sources Clock sources Count source of PMC1 One of the following fC f1 Timer B1 underflow Timer B2 underflow Division No division No division divided by 8 divided by 32 or divi...

Page 474: ...lag CEFLG Counter overflow flag Counter overflow flag CEINT Set to 1 when using counter overflow interrupt Set to 1 when using counter overflow interrupt PSEL0 Set to 01b Set to 10b PSEL1 PMCiCON3 CRE...

Page 475: ...iCON2 register becomes 1 counter overflow and stays 1 until the next measurement Table 22 20 Registers and Setting Values in Input Capture Mode Simultaneous Count Operation 2 2 1 Register Bit Function...

Page 476: ...Changes from 1 to 0 PMCiINT DRINT Header match The measured result is within the range set by registers PMCiHDPMIN and PMCiHDPMAX when header is enabled PMCiSTS PTHDFLG PMCiINT PTHDINT Data 0 1 match...

Page 477: ...easure interrupt request SDFLG CEFLG REINT BFULINT PTHDINT PTDINT TIMINT SDINT CEINT CPFLG DRFLG DRINT PMC1 interrupt IR bit in the PMC1IC register REFLG PTD0FLG PTD1FLG Timer measure interrupt reques...

Page 478: ...it in the IFSR2A register to 1 remote control signal receiver 0 To use the remote control signal receiver 1 interrupt set the IFSR25 bit in the IFSR2A register to 1 remote control signal receiver 1 Ta...

Page 479: ...rn match mode Using an interrupt Set the DRINT bit in the PMCiINT register to 1 data reception complete interrupt enabled and read the registers within the PMCi interrupt routine Monitoring by a progr...

Page 480: ...of 800 Jul 31 2012 M16C 64A Group 22 Remote Control Signal Receiver 22 5 4 Combined Operation When using combined operation set same value to bits TYP1 to TYP0 in the PMC0CON1 register and bits TYP1...

Page 481: ...l I O mode Clock asynchronous serial I O mode UART mode Special mode 1 I2C mode The simplified I2C bus interface is supported Special mode 2 The transmit receive clock polarity and phase are selectabl...

Page 482: ...1SIO or f2SIO f8SIO f32SIO Internal External RTS0 CTS0 TXD0 Transmit receive unit CTS RTS disabled CTS RTS disabled CTS RTS selected Receive clock Transmit clock CLK1 to CLK0 00b 01b 10b CKDIR CKPOL U...

Page 483: ...D1 Transmit receive unit Receive clock Transmit clock CLK1 to CLK0 00b 01b 10b CKDIR UART reception UART transmission Clock sync type CKDIR 0 1 PCLK1 f1SIO or f2SIO 1 2 1 2 1 8 f8SIO 1 4 f32SIO f1SIO...

Page 484: ...ous type when external clock is selected CLKi Clock source selection f1SIO or f2SIO f8SIO f32SIO Internal External RTSi CTSi TXDi Transmit receive unit CTS RTS disabled CTS RTS disabled CTS RTS select...

Page 485: ...s UART 7 bits UART 9 bits clock sync type Clock sync type clock sync type RXDi UART 8 bits UART 9 bits Data bus D7 D6 D5 D4 D3 D2 D1 D0 D8 0 0 0 0 0 0 0 PAR Inverted Not inverted Error signal output c...

Page 486: ...U0C1 00XX 0010b 024Eh UART0 Receive Buffer Register U0RB XXh 024Fh XXh 0250h UART Transmit Receive Control Register 2 UCON X000 0000b 0254h UART1 Special Mode Register 4 U1SMR4 00h 0255h UART1 Special...

Page 487: ...e Register 4 U6SMR4 00h 0295h UART6 Special Mode Register 3 U6SMR3 000X 0X0Xb 0296h UART6 Special Mode Register 2 U6SMR2 X000 0000b 0297h UART6 Special Mode Register U6SMR X000 0000b 0298h UART6 Trans...

Page 488: ...it Symbol Bit Name RW Reset Value 0000 0011b b0 Function b4 b2 RW Reserved bits Set to 0 b7 b6 RW Reserved bits Set to 0 PCLK5 RW Clock output function expansion bit enabled in single chip mode 0 Sele...

Page 489: ...bit 0 1 stop bit 1 2 stop bit RW CKDIR Internal external clock select bit 0 Internal clock 1 External clock RW PRY Odd even parity select bit Enabled when PRYE is 1 0 Odd parity 1 Even parity RW IOPOL...

Page 490: ...g or I2C mode write to this register in 16 bit units or in 8 bit units from upper byte to lower byte b7 b0 Function RW Setting Range If set value is n UiBRG divides the count source by n 1 WO 00h to F...

Page 491: ...select bit RW RW RW CTS RTS function select bit Enabled when CRD is 0 0 CTS function selected 1 RTS function selected b1 b0 0 0 f1SIO or f2SIO selected 0 1 f8SIO selected 1 0 f32SIO selected 1 1 Do n...

Page 492: ...annel transistor of the CMOS output buffer always off but not to change pins TXDi SDAi and SCLi to open drain output completely Refer to the electrical characteristics for the input voltage range UFOR...

Page 493: ...W Receive enable bit 0 Reception disabled 1 Reception enabled 0 Transmission disabled 1 Transmission enabled Transmit buffer empty flag 0 Data present in UiTB register 1 No data present in UiTB regist...

Page 494: ...ce disabled The RE bit in the UiC1 register is 0 reception disabled Condition to become 1 The RI bit in the UiC1 register is 1 data present in UiRB register and the last bit of the next data is receiv...

Page 495: ...nous serial I O mode or to 010b I2C mode The read value is undefined Conditions to become 0 Bits SMD2 to SMD0 in the UiMR register are 000b serial interface disabled The RE bit in the UiC1 register is...

Page 496: ...le bit UART0 transmit interrupt source select bit U1RRM UART Transmit Receive Control Register 2 RW RW RW RW UART0 continuous receive mode enable bit 0 Continuous receive mode disabled 1 Continuous re...

Page 497: ...CL SDA output select bit b3 This bit is used in master mode of I2C mode To set this bit to 1 preset the IICM bit in the UiSMR register to 1 I2C mode Do not set this bit to 1 when the IICM bit is 0 Set...

Page 498: ...o insert bit 3 b7 This bit is used in slave mode of I2C mode To set this bit to 1 preset the IICM bit in the UiSMR register to 1 I2C mode Do not set this bit to 1 when the IICM bit is 0 SCLHI SCL outp...

Page 499: ...b4 b1 b2 b3 b0 Function Bit Symbol Bit Name RW DL1 RW DL0 SDAi digital delay setup bit b7 b6 b5 0 0 0 No delay 0 0 1 1 to 2 cycles of UiBRG count source 0 1 0 2 to 3 cycles of UiBRG count source 0 1...

Page 500: ...it state wait state cleared 1 Hold the SCLi pin low after the eighth bit is received 0 Use NACK ACK interrupt 1 Use transmit receive interrupt Clock synchronization bit 0 Clock synchronization disable...

Page 501: ...t Name RW BBS ABC IICM ACSE Set to 0 Reserved bit I2C mode select bit b3 0 No auto clear function 1 Auto clear at bus collision Auto clear function select bit of transmit enable bit RW RW RW RW RW Bus...

Page 502: ...enabled The TI bit in the UiC1 register is 0 data presents in UiTB register When CTS function is selected input on the CTSi pin is low Reception start conditions To start reception satisfy the followi...

Page 503: ...ly when transmitting CLKi Output Transmit receive clock output The CKDIR bit in the UiMR register 0 Input Transmit receive clock input The CKDIR bit in the UiMR register 1 Set the port direction bit s...

Page 504: ...polarity UFORM Select LSB first or MSB first UiC1 TE Set to 1 to enable transmission reception TI Transmit buffer empty flag RE Set to 1 to enable reception RI Reception complete flag UjIRS Select so...

Page 505: ...receive enabled Write dummy data to the UiTB register Data is transferred from the UARTi receive register to the UiRB register 0 1 Set to 0 by an interrupt request acknowledgment or by a program D0 D...

Page 506: ...receive clock D1 D2 D3 D4 D5 D6 D7 D1 D2 D3 D4 D5 D6 D7 D0 D0 TXDi RXDi CLKi 1 CKPOL bit in the UiC0 register is 0 transmit data is output at the falling edge and the receive data is input at the ris...

Page 507: ...ata and starting the next transmission Figure 23 8 shows Operation Example in Continuous Receive Mode Figure 23 8 Operation Example in Continuous Receive Mode 1 UFORM bit in the UiC0 register is 0 LSB...

Page 508: ...an internal clock Figure 23 10 Transmit Receive Clock Output from Multiple Pins D0 D1 D2 D3 D4 D5 D6 D7 Transmit receive clock TXDi not inverted 1 UiLCH bit in the UiC1 register is 0 not inverted 2 U...

Page 509: ...egister is 0 enable CTS RTS of UART0 The CRS bit in the U0C0 register is 1 output RTS of UART0 The CRD bit in the U1C0 register is 0 enable CTS RTS of UART1 The CRS bit in the U1C0 register is 0 input...

Page 510: ...led Start bit detection Interrupt request generation timing For transmission one of the following conditions can be selected The UiIRS bit in the UiC1 or UCON register is 0 transmit buffer empty When...

Page 511: ...0 can be used as an input port only when transmitting CLKi I O Input output port The CKDIR bit in the UiMR register 0 Input Transmit receive clock input The CKDIR bit in the UiMR register 1 Set the po...

Page 512: ...t can be selected when character bit length is 8 bits Set to 0 when character bit length is 7 or 9 bits UiC1 TE Set to 1 to enable transmission TI Transmit buffer empty flag RE Set to 1 to enable rece...

Page 513: ...m the UiTB register to the UARTi transmit register Stop bit TE bit in the UiC1 register TI bit in the UiC1 register TXEPT bit in the UiC0 register IR bit in the SiTIC register TE bit in the UiC1 regis...

Page 514: ...ve clock RI bit in UiC1 register RTSi Stop bit 1 0 0 1 High Low IR bit in SiRIC register 0 1 Set to 0 by an interrupt request acknowledgment or by a program Transferred from UARTi receive register to...

Page 515: ...3 13 Example of Bit Rates and Settings Bit Rate bps Count Source of UiBRG Peripheral Function Clock f1 16 MHz Peripheral Function Clock f1 24 MHz Set Value of UiBRG n Bit Rate bps Set value of UiBRG n...

Page 516: ...D4 D5 D6 SP D0 D1 D2 D3 D4 D5 D6 SP D0 TXDi RXDi CLKi 2 UFORM bit in the UiC0 register 1 MSB first D6 D5 D4 D3 D2 D1 D0 D7 TXDi RXDi CLKi ST ST D7 P D7 P SP SP ST ST P P D6 D5 D4 D3 D2 D1 D0 D7 i 0 t...

Page 517: ...0 to 2 5 to 7 The above assumes the following The CKPOL bit in the UiC0 register is 0 transmit data output at the falling edge of the transmit receive clock The UFORM bit in the UiC0 register is 0 LS...

Page 518: ...he U0C0 register is 1 output RTS of UART0 The CRD bit in the U1C0 register is 0 enable CTS RTS of UART1 The CRS bit in the U1C0 register is 0 input CTS of UART1 The RCSP bit in the UCON register is 1...

Page 519: ...r bit length 8 bits Transfer clock Master mode The CKDIR bit in the UiMR register is 0 internal clock fj 2 n 1 fj f1SIO f2SIO f8SIO f32SIO n setting value of the UiBRG register 03h to FFh Slave mode T...

Page 520: ...i UARTi UARTi R UARTi transmit NACKi interrupt request UARTi receive ACKi interrupt request DMA1 DMA3 request 9th bit IICM 1 and IICM2 0 S R Q Bus busy Start stop condition detection interrupt request...

Page 521: ...DIR Set to 0 Set to 1 4 to 6 Set to 0 Set to 0 IOPOL Set to 0 Set to 0 UiC0 CLK1 CLK0 Select the count source for the UiBRG register Disabled CRS Disabled because CRD is 1 Disabled because CRD is 1 TX...

Page 522: ...le SDAi output Set to 1 to disable SDAi output 7 Set to 0 Set to 0 UiSMR3 0 2 4 NODC Set to 0 Set to 0 CKPH Set to 1 Set to 1 DL2 to DL0 Set the amount of SDAi digital delay Set the amount of SDAi dig...

Page 523: ...edge of the 9th bit of SCLi Falling edges of the 8th bit of SCLi and rising edges of the 9th bit of SCLi UARTi transmission output delay Not delayed Delayed Delayed Read RXDi and SCLi pin levels Poss...

Page 524: ...SCLi D0 Transmit interrupt Transfer to UiRB register The above diagram assumes the CKDIR bit in the UiMR register is 1 slave selected Receive interrupt DMA1 DMA3 request b15 b9 b8 b7 b0 D0 D7 D6 D5 D4...

Page 525: ...gure 23 21 Detecting Start and Stop Conditions 23 3 3 2 Generating Start and Stop Conditions A start condition is generated by setting the STAREQ bit in the UiSMR4 register i 0 to 2 5 to 7 to 1 start...

Page 526: ...te 1 Set to 0 or 1 by a program 2 Master mode when CKPH is 1 2 1 7 3 8 9 Start condition generation interrupt request generated Stop condition detection interrupt request generated Stop condition dete...

Page 527: ...DRATE Reset the UiBRG value to target bit rate Note 1 After a stop condition is generated when generating the next start condition after setting the STSPSEL bit in the UiSMR4 register to 0 and waiting...

Page 528: ...sfer to UiRB Register and Interrupt Timing The clock speed increase makes it difficult to secure the required time for ACK generation and data transmit procedure The I2C mode supports a function of wa...

Page 529: ...the logical AND of the internal clock and SCLi The synchronized period starts from one clock prior to an internally generated clock and ends when the ninth clock is completed The CSC bit can be set t...

Page 530: ...r than SCL clock bit rate setting To calculate the effective value of SCL clock take the SCL clock rise time tR into consideration The following is an example of an SCL clock calculation Example of an...

Page 531: ...27 UiTB Register Setting SDA Output Figure 23 28 Byte Data Transmission Set bits DL2 to DL0 in the UiSMR3 register to add no delays or a delay of one to eight UiBRG count source clock cycles to SDAi...

Page 532: ...1 if the CKPH bit in the UiSMR3 register is 1 the same data as when the IICM2 bit is 0 can be read To read the data read the UiRB register after the rising edge of ninth bit of the corresponding clock...

Page 533: ...n is detected the serial interface operates as follows The transmit shift register is initialized and the UiTB register value is transferred to the transmit shift register Doing so starts the data tra...

Page 534: ...pt one of the following conditions can be selected The UiIRS bit in the UiC1 or UCON register is 0 transmit buffer empty When transferring data from the UiTB register to the UARTi transmit register at...

Page 535: ...k output The CKDIR bit in the UiMR register 0 TXDi Output Serial data output Dummy data is output when performing reception only RXDi Input Serial data input Set the port direction bits sharing pins t...

Page 536: ...n the UiSMR3 register UFORM Select the LSB first or MSB first UiC1 TE Set to 1 to enable transmission reception TI Transmit buffer empty flag RE Set to 1 to enable reception RI Reception complete flag...

Page 537: ...mit receive clock polarity and phase are the same for the master and slaves to be used for communication Figure 23 33 shows the Transmit and Receive Timing in Master Mode Internal Clock Figure 23 33 T...

Page 538: ...lect the count source for the UiBRG register CRS Disabled because CRD is 1 TXEPT Transmit register empty flag CRD Set to 1 NCH Select TXDi pin output format 3 CKPOL Set to 0 UFORM Set to 0 UiC1 TE Set...

Page 539: ...ust be met before the falling edge of RXD When the SSS bit is 0 the serial interface starts sending data one transmit receive clock cycle after the transmission start condition is met TXDi RXDi ST D0...

Page 540: ...register is 0 internal clock fi 16 n 1 fi f1SIO f2SIO f8SIO f32SIO n setting value of the U2BRG register 00h to FFh The CKDIR bit is 1 external clock fEXT 16 n 1 fEXT input from the CLK2 pin n setting...

Page 541: ...the internal clock or external clock STPS Set to 0 PRY Set to 1 in direct format or 0 in inverted format PRYE Set to 1 IOPOL Set to 0 U2C0 CLK0 CLK1 Select the count source for the U2BRG register CRS...

Page 542: ...form consisting of the transmit waveform from the transmitter and parity error signal from the TXD2 pin is generated Data is transferred from the U2TB register to the UART2 transmit register Note 1 RE...

Page 543: ...ile outputting a parity error signal the PER bit is cleared to 0 no parity error and at the same time the TXD2 output again goes high When transmitting a transmission complete interrupt request is gen...

Page 544: ...numbered parity is used to determine whether a parity error occurs For inverted format set the PRYE bit to 1 the PRY bit to 0 odd parity the UFORM bit to 1 MSB first and the U2LCH bit to 1 inverted Wh...

Page 545: ...ransmit Interrupt Control Register S2TIC XXXX X000b 0050h UART2 Receive Interrupt Control Register S2RIC XXXX X000b 0051h UART0 Transmit Interrupt Control Register S0TIC XXXX X000b 0052h UART0 Receive...

Page 546: ...in the UiMR register are not set to 010b I2C mode When the RI bit in the UiC1 register is changed from 0 no data in the UiRB register to 1 data present in the UiRB register the IR bit in the SiRIC reg...

Page 547: ...Reception When the RTS function is used with an external clock the RTSi pin i 0 to 2 5 to 7 outputs a low level signal which informs the transmitting side that the MCU is ready for a receive operation...

Page 548: ...der byte in the UiTB register for each receive operation If the reception is started while an external clock is selected and the TXEPT bit in the UiC0 register is 1 no data present in transmit registe...

Page 549: ...lculation example of hold and setup times when generating a start stop condition Calculation example when setting 100 kbps UiBRG count source f1 20 MHz UiBRG register setting value n 100 1 SDA digital...

Page 550: ...s started in slave mode and the TXEPT bit in the UiC0 register is 1 no data present in transmit register meet the last requirement when the external clock is high Requirements to start transmission in...

Page 551: ...clock Selectable functions CLK polarity selection Whether data is input output at the rising or falling edge of the transmit receive clock can be selected LSB first or MSB first selection Whether to s...

Page 552: ...i Output Serial data output SMi3 bit in the SiC register 1 SMi2 bit in the SiC register 0 SINi Input Serial data input SMi3 bit in the SiC register 1 Port direction bits sharing pins 0 Dummy data is i...

Page 553: ...ress Register Symbol Reset Value 0012h Peripheral Clock Select Register PCLKR 0000 0011b 0270h SI O3 Transmit Receive Register S3TRR XXh 0272h SI O3 Control Register S3C 0100 0000b 0273h SI O3 Bit Rat...

Page 554: ...Bit Name RW Reset Value 0000 0011b b0 Function b4 b2 RW Reserved bits Set to 0 b7 b6 RW Reserved bits Set to 0 PCLK5 RW Clock output function expansion bit enabled in single chip mode 0 Selected by se...

Page 555: ...nd the SMi2 bit to 0 SOUTi output b7 b6 b5 b4 b1 b2 b3 Symbol S3C S4C Address 0272h 0276h Reset Value 0100 0000b 0100 0000b b0 Function Bit symbol Bit Name RW SI Oi Control Register i 3 4 RW SMi2 SOUT...

Page 556: ...interface enabled after setting bits SM26 and SM27 b7 Symbol S3BRG S4BRG Address 0273h 0277h Reset Value Undefined Undefined b0 Function RW SiBRG divides the count source by n 1 where n set value 00h...

Page 557: ...ister to select the transmit receive clock polarity Figure 24 2 shows Polarity of Transmit Receive Clock Figure 24 2 Polarity of Transmit Receive Clock 2 When the SMi4 bit 1 D1 D2 D3 D4 D5 D6 D7 D1 D2...

Page 558: ...3 Bit Order 1 The SMi5 bit in the SiC register is set to 0 LSB first D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D0 TXDi RXDi CLKi 2 The SMi5 bit in the SiC register is set to 1 MSB first D6 D5 D4 D...

Page 559: ...g between 0 5 to 1 0 cycles of the transmit receive clock After 8 bits of data have been transmitted received the transmit receive clock from the CLKi pin stops Figure 24 4 shows SI Oi Operation Timin...

Page 560: ...5 shows SOUT3 Pin Level after Transmission Figure 24 5 SOUT3 Pin Level after Transmission SOUT3 output CLK3 output The above SOUT3 example assumes the following The SM32 bit in the S3C register is 0 S...

Page 561: ...t in the SiC register is 0 external clock write to the SiTRR register and SMi7 bit in the SiC register under the following conditions When the SMi4 bit in the SiC register is 0 transmit data is output...

Page 562: ...i3 bit Setting the SOUTi initial value to high 1 Port selection switching I O port SOUTi D0 i 3 4 Initial value high Port output D0 Example When High Is Selected for the SOUTi Initial Value This diagr...

Page 563: ...e interrupt vector and interrupt control register with other peripheral functions To use the following interrupts set the bits as follows SI O3 Set the IFSR6 bit in the IFSR register to 0 SI O3 SI O4...

Page 564: ...while transmission reception is stopped Read receive data from the SiTRR register while transmission reception is stopped The IR bit in the SiIC register becomes 1 interrupt requested during output of...

Page 565: ...ard Master transmission Master reception Slave transmission Slave reception Bit rate 16 1 kbps to 400 kbps fVIIC 4 MHz I O pins Serial data line SDAMM SDA Serial clock line SCLMM SCL Interrupt request...

Page 566: ...If slave address match is detected an ACK is returned If the slave address match is not detected a NACK is returned and no further data is transmitted received Up to three slave addresses can be set G...

Page 567: ...Data controller STSP SEL SIS SIP SSC 4 SSC 3 SSC 2 SSC 1 SSC 0 Clock divider Clock controller Noise filter Interrupt generator Timeout detector SCL SDA interrupt request f1IIC f2IIC PCLKR register PCL...

Page 568: ...clock Table 25 4 Registers Address Register Symbol Reset Value 0012h Peripheral Clock Select Register PCLKR 0000 0011b 02B0h I2C0 Data Shift Register S00 XXh 02B2h I2C0 Address Register 0 S0D0 0000 00...

Page 569: ...t Symbol Bit Name RW Reset Value 0000 0011b b0 Function b4 b2 RW Reserved bits Set to 0 b7 b6 RW Reserved bits Set to 0 PCLK5 RW Clock output function expansion bit enabled in single chip mode 0 Selec...

Page 570: ...SB bit 7 is transmitted first synchronizing with the SCLMM clock Every time 1 bit data is output the S00 register value is shifted 1 bit to the left When the I2C interface is a receiver data is transf...

Page 571: ...when not setting the slave address However when the MSLAD bit in the S4D0 register is 0 registers S0D1 and S0D2 are disabled Only the slave address set to the S0D0 register is compared with address th...

Page 572: ...CLMM I O ports or other peripheral pins The S00 register is write disabled The I2C bus system clock hereinafter called fVIIC stops S10 register ADR0 bit 0 general call not detected AAS bit 0 slave add...

Page 573: ...e IHR bit resets the I2C interface if there is an anomaly during transmission reception When the ES0 bit in the S1D0 register is 1 I2C interface enabled and then the IHR bit is set to 1 reset the I2C...

Page 574: ...rate in fast mode Do not set the CCR value from 0 to 2 regardless of the fVIIC frequency Rewrite bits CCR4 to CCR0 when the ES0 bit in the S1D0 register is 0 disabled b7 b6 b5 b4 b1 b2 b3 I2C0 Clock C...

Page 575: ...Pulse ACKCLK ACK clock bit b7 When the ACKCLK bit is 1 ACK clock present an ACK clock is generated immediately after 1 byte data is transmitted or received 8 clocks When the ACKCLK bit is 0 no ACK clo...

Page 576: ...elected by the SIP bit for the pin signal selected by the SIS bit Refer to 25 4 Interrupts STSPSEL Start stop condition generation select bit b7 See Table 25 13 Setup Hold Time for Generating a Start...

Page 577: ...EC SDAM RW SCLM RW ICK0 ICK1 I2 C bus system clock select bit enabled when bits ICK4 to ICK2 in the S4D0 register are 000b RW 0 SCLMM I O pin 1 Port output pin Internal SDA output monitor bit 0 Logic...

Page 578: ...d Therefore read the internal WAIT flag status to determine whether the I2C bus interrupt request is generated at the eighth clock before the ACK clock or at the falling edge of the ACK clock When the...

Page 579: ...S10 register Internal WAIT flag IR bit in the IICIC register Write signal to the S00 register ACK clock Set to 0 by an interrupt acceptance or by a program 2 7 8 9 1 Write by a program When setting t...

Page 580: ...d SCL output signal levels are the same as the output level of the I2C interface before it has any effect from the external device output Bits SDAM and SCLM are read only bits If necessary set these b...

Page 581: ...the S10 register is set to 1 bus busy and the SCLMM high period is greater than the timeout detect period I2C0 Control Register 2 Symbol S4D0 Address 02B7h Bit Symbol Bit Name RW Reset Value 00b Funct...

Page 582: ...interface disabled fVIIC is selected by setting all the bits ICK4 to ICK2 bits ICK1 to ICK0 in the S3D0 register and the PCLK0 bit in the PCLKR register Refer to Table 25 8 I2C bus System Clock Selec...

Page 583: ...bit When read 0 Last bit 0 1 Last bit 1 RW ADR0 General call detect flag When read 0 Not detected 1 Detected RW AAS Slave address compare flag When read 0 Address not matched 1 Address matched RW AL...

Page 584: ...b1 The ADR0 bit function in read access is described below See Table 25 10 Functions Enabled by Writing to the S10 Register for the bit function in write access Conditions to become 0 Stop condition i...

Page 585: ...the ALS bit in the S1D0 register is 0 addressing format and the received slave address is 0000000b general call AL Arbitration lost detect flag b3 The AL bit function in read access is described belo...

Page 586: ...format and the received slaved address is 0000000b general call In slave receive mode the ALS bit in the S1D0 register is 1 free data format and the slave address reception is completed Conditions to...

Page 587: ...he S1D0 register is set to 1 I2C interface reset Conditions to become 1 The TRX bit is set to 1 by a program In slave mode the ALS bit in the S1D0 register is 0 addressing format the AAS bit in the S1...

Page 588: ...AAS0 bit is enabled when the MSLAD bit in the S4D0 register is 0 S0D0 register only Bits AAS2 to AAS0 are enabled when the MSLAD bit is 1 registers S0D0 to S0D2 Conditions to become 0 The ES0 bit in...

Page 589: ...en the ES0 bit in the S1D0 register is 0 I2C interface disabled See Table 25 8 I2C bus System Clock Select Bits for details f1 PCLKR register PCLK0 1 PCLK0 0 System clock select circuit Divide by m fI...

Page 590: ...ow period of the SCLMM clock I2C bus standard is allocated Table 25 12 lists the Bit Setting for Bits CCR4 to CCR0 and Bit Rate fVIIC 4 MHz Table 25 11 Bit Rate of Internal SCL Output and Duty Cycle I...

Page 591: ...1 does not stop in wait mode and transition is made to wait mode the I2C interface can receive the slave address even in wait mode When the CM02 bit in the CM0 register is set to 1 peripheral clock f1...

Page 592: ...clock signal is output for 1 byte and the slave address is transmitted After a stop condition is generated and the BB bit becomes 0 bus free a write to the S10 register is disabled for 1 5 fVIIC cycl...

Page 593: ...Time for Generating a Start Stop Condition Item STSPSEL Bit Standard Clock Mode Fast mode fVIIC cycles fVIIC 4 MHz fVIIC cycles fVIIC 4 MHz Setup time 0 short mode 20 5 0 s 10 2 5 s 1 long mode 52 13...

Page 594: ...hold time Figure 25 8 Stop Condition Generation Timing Do not write to the S10 register or S00 register until the BB bit in the S10 register becomes 0 bus free after the instructions to generate a sto...

Page 595: ...rt condition standby state The SDAMM pin released 2 Wait until the SDAMM pin level becomes high 3 Write a slave address to the S00 register a start condition trigger is generated Figure 25 9 shows the...

Page 596: ...egister is set to E0h If the I2C interface is in a start condition standby state exit the state A start condition trigger is not generated even if a data is written to the S00 register by program Bits...

Page 597: ...he completion of the slave address receive If data is written to registers S10 and S00 during that period the above operation is performed Figure 25 11 shows the Start Condition Overlap Protect Functi...

Page 598: ...or master receive mode Stop condition generated in master transmit mode or master receive mode b Internal SDA output High c SDAMM pin level Low sampling at the rising edge of the clock of SCLMM pin Fi...

Page 599: ...during slave address transmission the I2C interface automatically enters slave receive mode and receives the slave address sent from another master When the ALS bit in the S1D0 register is 0 addressi...

Page 600: ...BB bit in the S10 register becomes 1 when a start condition is detected and becomes 0 when a stop condition is detected The set timing and reset timing of the BB bit depends on whether the mode is st...

Page 601: ...alues of Bits SSC4 to SSC0 in Standard Clock Mode fVIIC SSC Value recommended Start Stop Condition Detect Parameter BB Bit Setting Resetting Time SCLMM open time Setup time Hold time 5 MHz 11110b 6 2...

Page 602: ...25 15 shows Operation When Transmitted Received a Slave Address or Data Figure 25 15 Operation When Transmitted Received a Slave Address or Data PIN bit in the S10 register SCLMM SDAMM ACK clock A A S...

Page 603: ...on Timing A timeout is detected when all of the following conditions are met The TOE bit in the S4D0 register is 1 timeout detection enabled The BB bit in the S10 register is 1 bus busy The SCLMM pin...

Page 604: ...enabling an I2C bus interrupt at the eighth clock just before ACK clock during data reception a receiver can determine whether to generate ACK or NACK after checking the received data each byte 25 3 1...

Page 605: ...ion generated then slave address transmitted B Data transmission in I2C bus interrupt routine 1 Write transmit data to the S00 register data transmission C Completion of Master transmission in I2C bus...

Page 606: ...he S10 register master receive mode 2 Set the ACKBIT bit in the S20 register to 0 ACK presents because the data is not the last one 3 Write dummy data to the S00 register C Data reception 2 data recep...

Page 607: ...r B Data reception 1 In I2C bus interrupt routine 1 Read the received data from the S00 register 2 Set the ACKBIT bit in the S20 register to 0 ACK presents because the data is not the last one 3 Write...

Page 608: ...ter and execute slave transmission Figure 25 20 Example of Slave Transmission A Start of slave transmission In I2C bus interrupt routine 1 Check the value of the S10 register When the TRX bit is 1 the...

Page 609: ...T bit in the S10 register ASL bit in the S1D0 register AAS bit in the S10 register ADR0 bit in the S10 register PIN TOE bit in the S4D0 register TOF bit in the S4D0 register I2C bus interrupt request...

Page 610: ...the falling edge of ACK clock through the SCLMM pin PIN S10 IICIC Data reception before ACK clock Detection of the falling edge of the last clock of transmit receive data through the SCLMM pin WIT S3...

Page 611: ...the SIP bit in the S2D0 register or the SIS bit in the S2D0 register is changed Therefore follow the procedure below to change these bits Refer to 14 13 Notes on Interrupts 1 Set bits ILVL2 to ILVL0...

Page 612: ...HR bit in the S1D0 register during transmission reception 25 5 2 3 S20 Register Do not change bits other than the ACKBIT bit in the S20 register during transmission reception 25 5 2 4 S3D0 Register Do...

Page 613: ...master devices drive the SCLMM line low no normal stop condition is generated This is because the SDAMM line is released while the SCLMM line is still driven low Figure 25 22 Abnormal Waveform Abnorm...

Page 614: ...ising edge of the SCLMM line Interrupts disabled P7_1 1 SCLMM line is high No Enable SCL SDA interrupt End wait for an interrupt Reset the MMI2C module P7_0 1 SDAMM line becomes high Yes Yes End SCL S...

Page 615: ...CC3 register 1 reception enabled Start bit detected Interrupt request generation timing A transmit interrupt is generated when 8 bits of data have been transmitted 10 bits of data have been transmitte...

Page 616: ...edges are detected ACK output in receiving process One of the following conditions can be selected Inserted by program Set by the CCRBAO bit of CCRB2 register Inserted by hardware ACK is output when m...

Page 617: ...atch or Broadcast CRD8FLG Detect reception of 8 10 bits of data CTNACKFLG Detect NACK in transmission CRERRFLG Receive signals outside tolerated range CRXDEN 0 1 0 1 CTXDEN fC Timer A underflow CCLK1...

Page 618: ...Function Control Register 1 CECC1 XXXX X000b 0351h CEC Function Control Register 2 CECC2 00h 0352h CEC Function Control Register 3 CECC3 XXXX 0000b 0353h CEC Function Control Register 4 CECC4 00h 0354...

Page 619: ...dware Transmit NACK ACK end select bit Symbol CECC2 Address 0351h Reset Value 00h CEC Function Control Register 2 Bit Symbol Bit Name Function RW CRRNG Receive edge detection select bit 0 Detects fall...

Page 620: ...n Lost Detection Table 26 5 ACK Output When Inserted by Hardware Destination Address ACK Output Received Destination address Address selected by the CRADRI1 or CRADRI2 register own address Direct 0000...

Page 621: ...set the CREGCLR bit to 0 then set it to 1 When setting the CREGCLR bit to 1 while CEC input is low the CREGFLG bit becomes 0 If the CREGCLR bit is set to 0 after that the CREGFLG bit becomes 1 Figure...

Page 622: ...data transmission continues even after the EOM bit is set to 1 and transmitted To stop transmitting set the CTXDEN bit in the CECC3 register to 0 transmission disabled Table 26 6 Operation When the EO...

Page 623: ...the CABTEN bit to 1 while not receiving a low pulse is output when writing to the CABTEN bit After setting the CRXDEN bit to 1 receive enabled and then setting the CABTEN bit to 1 if the receiving dat...

Page 624: ...TEN bit is 1 low pulse output enabled in reception error If a receive error occurs when the CABTWEN bit is set to 1 low pulse output at rising edge of the CEC signal and the CEC input is low a 3 6 ms...

Page 625: ...to become 0 Set the CTXDEN bit in the CECC3 register to 0 transmit disabled Symbol CECFLG Address 0354h Reset Value 00h CEC Flag Register Bit Symbol Bit Name Function RW b7 b6 b5 b4 b3 b2 b1 b0 CRFLG...

Page 626: ...t 0 Disabled 1 Enabled RW CRISEL2 Receive error interrupt enable bit 0 Disabled 1 Enabled RW CRISELM Receive interrupt mode select bit 0 No limitation of 8th 10th bit receive interrupt 1 8th 10th bit...

Page 627: ...in the CECFLG register is 1 while bits EOM and ACK are being transmitted after the eighth bit has been transmitted The information written to this bit is output after the next data transmission Do no...

Page 628: ...register is 0 receive disabled or the CRXDEN bit is 1 and the start bit to EOM bit are being received Do not rewrite the CCRBAO bit when the ACK bit is being transmitted CCRBAI Receive data ACK input...

Page 629: ...h in this chapter Symbol CRADRI2 Address 035Bh Reset Value 00h CEC Receive Follower Address Set Register 2 Bit Symbol Bit Name Function RW CRADRI20 1000b select bit 0 Not selected 1 Selected RW CRADRI...

Page 630: ...r bits If necessary set to 0 The read value is undefined b2 b1 PCR5 RW PCR6 RW PCR7 RW INT6 input enable bit INT7 input enable bit Key input enable bit 0 Enabled 1 Disabled 0 Enabled 1 Disabled 0 Enab...

Page 631: ...e To use fC set the PM25 bit in the PM2 register to 1 peripheral clock fC provided Refer to 8 Clock Generator for details When the timer A0 underflow is used as the count source each time timer A0 und...

Page 632: ...ut to the CEC pin twice in a row that level is transferred to the internal circuit when the CFIL bit in the CECC2 register is 1 digital filter enable Figure 26 4 shows Digital Filter Figure 26 4 Digit...

Page 633: ...in the CECC2 register Figure 26 5 shows Start Bit Acceptable Range When the start bit within the acceptable range is detected the CRSTFLG bit in the CECFLG register becomes 1 start bit detected Figure...

Page 634: ...ptable range the input data is determined as data 1 if the rising edge is detected before 1 05 ms and the input data is determined as data 0 if the rising edge is detected after 1 05 ms Figure 26 6 Da...

Page 635: ...s 1 low pulse output enabled in receive error However this pulse is not output if an error occurs in the start bit Low pulse output timing can be selected by setting the CABTWEN bit in the CECC4 regis...

Page 636: ...s 1 Low pulse is output at the rising edge of the CEC signal 3 6 ms 3 to 4 cycles of count source Receive error occurs CEC 3 6 ms Low pulse is output at the rising edge within 3 6 ms after the receive...

Page 637: ...is generated when the CABTEN bit becomes 1 Tolerated range error occurs IR bit CRERRFLG bit CABTEN bit Set to 0 by acceptance of an interrupt or by a program CRXDEN bit CEC While the CRXDEN bit is 0 r...

Page 638: ...1 inserted by hardware ACK is output when the received Destination address matches the address selected by the CRADRI1 or CRADRI2 register own address Table 26 8 lists ACK Output Table 26 8 ACK Outpu...

Page 639: ...er block Data block IR bit CRSTFLG bit CRFLG bit CRXDEN bit CEC ST H6 H1 H0 ACK D7 D6 D1 D0 H7 EOM EOM The above diagram applies under the following conditions y The CFIL bit in the CICC2 register is...

Page 640: ...0 filter disabled y The CRISEL2 bit in the CISEL register is 1 receive error interrupt enabled y The CRISELS bit in the CISEL register is 0 reception start bit interrupt disabled CRXDEN bit Bit in th...

Page 641: ...ransmit signal is selected by bits CFALL1 to CFALL0 in the CECC4 register Figure 26 13 shows Falling Timing of Transmit Signal Figure 26 13 Falling Timing of Transmit Signal CEC output CRISE2 to CRISE...

Page 642: ...rbitra tion lost detected Figure 26 14 Arbitration Lost Detectable Range 26 3 6 3 Transmission Example Figure 26 15 shows a Transmission Example Figure 26 16 shows a Transmission Example When NACK Rec...

Page 643: ...pt disabled y The CEOMI bit in the CECC3 register is set to 0 EOM enabled y The CFIL bit in the CECC2 register is set to 0 filter disabled y The CRISEL0 bit in the CISEL register is set to 0 8th bit r...

Page 644: ...bit in the CISEL register is set to 1 transmit error interrupt enabled y The CTNACK bit in the CECC2 register is set to 1 and the CTACKEN bit is 1 transmission stops with NACK CTXDEN bit Bit in the C...

Page 645: ...rupt disabled y The CRISEL1 bit in the CISEL register is set to 1 10th bit receive interrupt enabled y The CRISELS bit in the CISEL register is set to 1 reception start bit interrupt enabled Bits CTXD...

Page 646: ...m 0 to 1 CTISEL0 Tenth bit transmitted When the CTD8FLG bit changes from 1 to 0 CTISEL1 Transmit error interrupt Arbitration lost When the CTABTFLG bit changes from 0 to 1 CTISEL2 NACK received Direct...

Page 647: ...CEC2 interrupt set the IFSR34 bit in the IFSR3A register to 1 CEC2 Table 26 11 CEC Function Interrupt Associated Registers Address Register Symbol Reset Value 006Bh CEC1 Interrupt Control Register CEC...

Page 648: ...same bit successively 1 Change the bit to 0 2 Wait for one or more cycles of the count source 3 Change the same bit to 1 Example when reading the bit rewritten under the influence of another bit afte...

Page 649: ...12 Resolution 10 bits Integral nonlinearity error AVCC VREF 5 V AN0 to AN7 AN0_0 to AN0_7 or AN2_0 to AN2_7 input 3 LSB ANEX0 or ANEX1 input 3 LSB AVCC VREF 3 0 V AN0 to AN7 AN0_0 to AN0_7 or AN2_0 to...

Page 650: ...conversion register Analog circuit PM01 to PM00 00b PM01 to PM00 00b Comparator 0 1 ADSTBY ADEX1 to ADEX0 01b ADEX1 to ADEX0 10b ADEX1 to 0 00b 00b 00b 00b 00b 00b 00b 00b 00b 00b 00b 00b 00b 00b CH2...

Page 651: ...ue 0366h Port Control Register PCR 0000 0XX0b 03A2h Open Circuit Detection Assist Function Register AINRST XX00 XXXXb 03C0h A D Register 0 AD0 XXXX XXXXb 03C1h 0000 00XXb 03C2h A D Register 1 AD1 XXXX...

Page 652: ...ister Symbol PCR Address 0366h Bit Symbol RW Reset Value 0000 0XX0b b0 Bit Name Function PCR0 RW No register bits If necessary set to 0 The read value is undefined b2 b1 PCR5 RW PCR6 RW PCR7 RW INT6 i...

Page 653: ...register to 1 A D conversion after waiting for one cycle of AD b7 b6 b5 b4 b1 b2 b3 Symbol AINRST Address 03A2h Reset Value XX00 XXXXb b0 Function Bit Symbol Bit Name RW Open Circuit Detection Assist...

Page 654: ...D2 register AN3 AN0_3 AN2_3 AD3 register AN4 AN0_4 AN2_4 AD4 register AN5 AN0_5 AN2_5 AD5 register AN6 AN0_6 AN2_6 AD6 register AN7 AN0_7 AN2_7 AD7 register Symbol Address Reset Value RW A D Register...

Page 655: ...mode and bits PM05 to PM04 are 11b multiplexed bus is allocated to the entire CS space b7 0 0 b6 b5 b4 b1 b2 b3 Symbol ADCON2 Address 03D4h Reset Value 0000 X00Xb b0 Function Bit Symbol Bit Name RW A...

Page 656: ...e Table 27 5 A D Operation Mode Bit Setting A D Operation Mode ADCON1 register ADCON0 register MD2 MD1 MD0 0 0 0 One shot mode 0 0 1 Repeat mode 0 1 0 Single sweep mode 0 1 1 Repeat sweep mode 0 1 1 1...

Page 657: ...S0 bit in the ADCON0 register the CKS1 bit in the ADCON1 register and the CKS2 bit in the ADCON2 register Table 27 6 lists AD Frequency Table 27 6 AD Frequency CKS2 CKS1 CKS0 A D 0 0 0 fAD f1 divided...

Page 658: ...onverter is not used no current flows in the A D converter by setting the ADSTBY bit to 0 A D operation stopped standby This helps reduce power consumption b7 b6 b5 b4 b1 b2 b3 Symbol ADCON1 Address 0...

Page 659: ...the ADCON0 register CKS1 Bit in the ADCON1 register CKS2 Bit in the ADCON2 register Select A D conversion speed 1 CKS0 AD CKS1 CKS2 1 1 2 1 2 0 1 0 0 fAD fAD 1 3 f1 Sampling time First bit conversion...

Page 660: ...ing time and the last A D conversion result is stored in the ADi register One shot mode Start processing time A D conversion execution time end processing time Two pins are selected in single sweep mo...

Page 661: ...rnal trigger is enabled when the TRG bit in the ADCON0 register is 1 ADTRG trigger To use this trigger set the following The direction bit of the port which shares a pin with ADTRG is 0 input mode The...

Page 662: ...as analog input pins by setting bits ADEX1 to ADEX0 in the ADCON1 register The A D conversion result of pins ANEX0 and ANEX1 are stored in registers AD0 and AD1 respectively 27 3 5 Current Consumptio...

Page 663: ...i i 0 to 7 ANEXi AN0 i AN2 i AINRST0 Bit in the AINRST register FRQYHUVLRQ F FOH N 9ROWDJH RI RSHQ FLUFXLW SLQ P9 2SHQ FLUFXLW QRW GHWHFWHG 2SHQ FLUFXLW GHWHFWHG The horizontal axis indicates how many...

Page 664: ...Discharge AINRST1 1 On Sampling capacitor Charge control signal Discharge control signal C ANi ANi i 0 to 7 ANEXi AN0 i AN2 i AINRST1 Bit in the AINRST register FRQYHUVLRQ F FOH N 9ROWDJH RI RSHQ FLU...

Page 665: ...o a digital code once A D conversion start conditions When the TRG bit in the ADCON0 register is 0 software trigger the ADST bit in the ADCON0 register is set to 1 A D conversion starts When the TRG b...

Page 666: ...ADGSEL0 Select analog input pin group CKS2 Select AD frequency ADCON0 CH2 to CH0 Select analog input pin MD1 to MD0 Set to 00b TRG Select a trigger ADST Set to 1 to start A D conversion and set to 0 t...

Page 667: ...to the pin is repeatedly converted to a digital code A D conversion start conditions When the TRG bit in the ADCON0 register is 0 software trigger the ADST bit in the ADCON0 register is set to 1 A D c...

Page 668: ...onversion result can be read ADCON2 ADGSEL1 ADGSEL0 Select analog input pin group CKS2 Select AD frequency ADCON0 CH2 to CH0 Select analog input pin MD1 to MD0 Set to 01b TRG Select a trigger ADST Set...

Page 669: ...ADCON0 register is 0 software trigger the ADST bit in the ADCON0 register is set to 1 A D conversion start When the TRG bit is 1 ADTRG trigger the input level at the ADTRG pin changes from high to low...

Page 670: ...DCON2 ADGSEL1 ADGSEL0 Select analog input pin group CKS2 Select AD frequency ADCON0 CH2 to CH0 Disabled MD1 to MD0 Set to 10b TRG Select a trigger ADST Set to 1 to start A D conversion and set to 0 to...

Page 671: ...ion start conditions When the TRG bit in the ADCON0 register is 0 software trigger the ADST bit in the ADCON0 register is set to 1 A D conversion start When the TRG bit is 1 ADTRG trigger the input le...

Page 672: ...t AD0 to AD7 b9 to b0 A D conversion result can be read ADCON2 ADGSEL1 ADGSEL0 Select analog input pin group CKS2 Select AD frequency ADCON0 CH2 to CH0 Disabled MD1 to MD0 Set to 11b TRG Select a trig...

Page 673: ...is converted to a digital code in the following order AN0 AN1 AN0 AN2 AN0 AN3 A D conversion start conditions When the TRG bit in the ADCON0 register is 0 software trigger the ADST bit in the ADCON0 r...

Page 674: ...0 A D conversion result can be read ADCON2 ADGSEL1 ADGSEL0 Select analog input pin group CKS2 Select AD frequency ADCON0 CH2 to CH0 Disabled MD1 to MD0 Set to 11b TRG Select a trigger ADST Set to 1 to...

Page 675: ...ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7 ANi_0 ANi_1 ANi_2 ANi_3 ANi_4 ANi_5 ANi_6 ANi_7 When ANi_0 is prioritized single pin Time When ANi_0 and ANi_1 are prioritized 2 pins ANi_0 ANi_1 ANi_2 ANi_3 ANi_4...

Page 676: ...0 1 1024 VIN in time T when the difference between VIN and VC is 0 1LSB is obtained 0 1 1024 means that A D precision drop due to insufficient capacitor charge is kept to 0 1LSB in A D conversion Howe...

Page 677: ...ples for timing of generating interrupt requests Also refer to 14 7 Interrupt Control for details Table 27 18 lists Registers Associated with A D Converter Interrupt Table 27 18 Registers Associated w...

Page 678: ...27 17 Example of Pin Configuration 27 7 4 Register Access Write registers ADCON0 excluding the ADST bit ADCON1 and ADCON2 when A D conversion stops before a trigger is generated After A D conversion s...

Page 679: ...T register follow these steps 1 Change bits AINRST1 to AINRST0 in the AINRST register 2 Wait for one cycle of AD 3 Set the ADST bit in the ADCON0 register to 1 A D conversion started 27 7 9 Detecting...

Page 680: ...s one cycle of fAD Figure 27 19 Period When the ADi Register Value is Rewritten A D conversion AD0 register AD1 register AD7 register One cycle of fAD AN0 AN1 AN2 AN7 AN0 AN1 One cycle of fAD One cycl...

Page 681: ...er Block Diagram Table 28 1 D A Converter Specifications Item Specification D A conversion method R 2R Resolution 8 bits Table 28 2 I O Ports Pin Name I O Function DA0 Output 1 D A comparator output D...

Page 682: ...egister DACON 00h b7 b0 Function RW Output value of D A conversion 00h to FFh RW Setting Range D Ai Register i 0 1 Symbol Address Reset Value DA0 03D8h 00h DA1 03DAh 00h b7 b6 b5 b4 b1 b2 b3 D A Contr...

Page 683: ...n n decimal set in the DAi register V VREF n 0 to 255 VREF Reference voltage Figure 28 2 shows the D A Converter Equivalent Circuit Figure 28 2 D A Converter Equivalent Circuit n 256 VREF 2 AVSS 2R R...

Page 684: ...Notes on D A Converter 28 4 1 When Not Using the D A Converter When not using the D A converter set the DAiE bit i 0 1 in the DACON register to 0 output disabled and the DAi register to 00h in order...

Page 685: ...writes to a certain SFR address and perform CRC calculations automatically on the data read from and data written to the aforementioned SFR address Figure 29 1 CRC Calculator Block Diagram Table 29 1...

Page 686: ...ol Reset Value 03B4h SFR Snoop Address Register CRCSAR XXXX XXXXb 03B5h 00XX XXXXb 03B6h CRC Mode Register CRCMR 0XXX XXX0b 03BCh CRC Data Register CRCD XXh 03BDh XXh 03BEh CRC Input Register CRCIN XX...

Page 687: ...b7 b6 b5 b4 b1 b2 b3 Symbol CRCMR Address 03B6h Reset Value 0XXX XXX0b b0 CRC Mode Register CRC polynomial select bit No register bits If necessary set to 0 The read value is undefined CRC mode select...

Page 688: ...ress as a trigger to automatically perform CRC calculation there is no need to write data to the CRCIN register All SFR addresses from 0020h to 03FFh are subject to the CRC snoop The CRC snoop is usef...

Page 689: ...to the CRCIN register CRCD register CRCIN register After two cycles the result is stored in the CRCD register CRCD register 1189h 23h 0A41h b15 b0 b0 b0 b0 b0 b15 b15 b7 b7 Setting procedures 0000h Wh...

Page 690: ...word 4 byte units Erase method Block erase Program and erase control method Program and erase controlled by software commands Protect method A lock bit protects each block Number of commands 8 Progra...

Page 691: ...memory is rewritten using a dedicated serial programmer Standard serial I O mode 1 Clock synchronous serial I O Standard serial I O mode 2 2 wire clock asynchronous serial I O The flash memory is rewr...

Page 692: ...m ROM 2 can be used when the PRG2C0 bit in the PRG2C register is 0 program ROM 2 enabled Data flash can be used when the PM10 bit in the PM1 register is set to 1 0E000h to 0FFFFh data flash Data flash...

Page 693: ...h 0A0000h 0AFFFFh 0FFFFFh 090000h 09FFFFh 080000h 08FFFFh 00EFFFh 00E000h Program ROM 2 16 KB Block A 4 KB Block B 4 KB 00FFFFh 00F000h 013FFFh 010000h Data flash Program ROM 1 Block 0 64 KB Block 1 6...

Page 694: ...0 XX0Xb 0222h Flash Memory Control Register 2 FMR2 XXXX 0000b 0230h Flash Memory Control Register 6 FMR6 XX0X XX00b b7 0 b6 b5 b4 b1 b2 b3 Symbol FMR0 Address 0220h Reset Value 0000 0001b other than u...

Page 695: ...g or erasing FMSTP Flash memory stop bit b3 The FMSTP bit resets the flash memory control circuits and minimizes current consumption in the flash memory Access to the internal flash memory is disabled...

Page 696: ...6 1 Full Status Check Do not execute the following commands when the FMR06 bit is 1 Program block erase lock bit program and block blank check FMR07 Erase status flag b7 This bit indicates the auto e...

Page 697: ...or data flash When setting this bit to 0 one wait is inserted to the read cycle of the data flash The write cycle is not affected b7 0 b6 b5 b4 b1 b2 b3 Symbol FMR1 Address 0221h Reset Value 00X0 XX0X...

Page 698: ...efer to 9 4 Power Control in Flash Memory b7 0 0 b6 b5 b4 b1 b2 b3 Symbol FMR2 Address 0222h Reset Value XXXX 0000b b0 Function Bit Symbol Bit Name RW Flash Memory Control Register 2 b7 b4 No register...

Page 699: ...ister and FMR11 bit in the FMR1 register are 1 Change the FMR60 bit when the PM24 bit in the PM2 register is 0 NMI interrupt disabled or high is input to the NMI pin Also change this bit when the FMR0...

Page 700: ...n the block including the option function select area is erased In blank products the OFS1 address value is FFh when shipped After a value is written by the user this address takes on the written valu...

Page 701: ...e b0 Function WDTON Watchdog timer start select bit 0 Watchdog timer starts automatically after reset 1 Watchdog timer is stopped after reset b1 Reserved bit Set to 1 CSPROINI After reset count source...

Page 702: ...of program ROM 2 After starting the program the flash memory is rewritten according to the program in EW0 or EW1 mode 30 7 1 User Boot Function User boot mode can be selected by the status of a port...

Page 703: ...ndard serial I O mode Other than UserBoot in ASCII code Standard serial I O mode i 0 to 10 j 0 to 7 Notes 1 Only use the values listed in Table 30 7 2 See Table 30 8 UserBoot in ASCII Code 3 See Table...

Page 704: ...l of the port P1_5 is low Port Address 13FF9h 13FF8h P0 03h E0h P1 03h E1h P2 03h E4h P3 03h E5h P6 03h ECh P7 03h EDh P8 03h F0h P9 03h F1h P10 03h F4h Address Setting Value Meaning 13FF0h 55h Upper...

Page 705: ...0FFFFh 0FFFFFh 0F0000h 0EFFFFh 0E0000h Block 2 0DFFFFh 0D0000h Block N 0X0000h 0XFFFFh Reset vector Data flash When the RESET pin changes from low to high CNVSS VSS Single chip mode Boot mode User boo...

Page 706: ...ROM 1 Program ROM 2 Rewrite control program executable area The rewrite control program must be transferred to an area other than the flash memory e g RAM before being executed The rewrite control pro...

Page 707: ...on is forcibly stopped as soon as the interrupt occurs and then the interrupt process starts After the flash memory restart execute auto erase operation again and confirm that it is completed as expec...

Page 708: ...array mode Table 30 12 Modes after Executing Commands in EW0 Mode Command Mode after Executing Command Read array Read array mode Clear status register Read array mode Program Read status register mo...

Page 709: ...eted NMI watchdog timer oscillator stop restart detect voltage detect 1 and voltage detect 2 interrupts Auto erase operation or auto program operation forcibly stops as soon as the interrupt occurs an...

Page 710: ...12 M16C 64A Group 30 Flash Memory Table 30 13 Modes after Executing Commands in EW1 Mode Command Mode after Executing Command Read array Read array mode Clear status register Program Block erase Lock...

Page 711: ...vents data from being inadvertently written to or erased from the flash memory Table 30 14 lists Lock Bit and Block State Condition to become 0 Execute the lock bit program command Condition to become...

Page 712: ...mmand Table 30 15 Software Commands Command First Bus Cycle Second Bus Cycle Third Bus Cycle Mode Address Data D15 to D0 Mode Address Data D15 to D0 Mode Address Data D15 to D0 Read array Write x xxFF...

Page 713: ...in program ROM 1 program ROM 2 or the data flash Do not execute this command in EW1 mode Figure 30 8 Read Status Register Command 30 8 5 3 Clear Status Register Command The clear status register comma...

Page 714: ...he auto program operation is completed Do not execute other commands while the FMR00 bit is 0 After the auto program operation is completed the FMR06 bit in the FMR0 register indicates whether or not...

Page 715: ...n is completed Do not execute other commands while the FMR00 bit is 0 After the auto erase operation is completed the FMR07 bit in the FMR0 register indicates whether or not the auto erase operation h...

Page 716: ...ghest address of a block specified in the second bus cycle Figure 30 12 shows a flowchart of the Lock Bit Program Command Execute the read lock bit status command to read the lock bit state lock bit d...

Page 717: ...the second bus cycle the FMR16 bit in the FMR1 register stores information on the lock bit status of a specified block Read the FMR16 bit after the FMR00 bit in the FMR0 register becomes 1 ready Do n...

Page 718: ...ked the FMR07 bit SR5 is set to 1 not blank regardless of the FMR02 bit state Figure 30 14 shows a flowchart of the Block Blank Check Command Figure 30 14 Block Blank Check Command As a result of bloc...

Page 719: ...r Read any even address in program ROM 1 program ROM 2 or data flash after writing the read status register command Read any even address in program ROM 1 program ROM 2 or data flash after executing t...

Page 720: ...lock 2 The block erase command is executed on an unlocked block but the auto erase operation is not completed as expected The block blank check command is executed and the check result is not blank 0...

Page 721: ...do not use that block When handling an erase error of the block blank check command and erasing is not necessary execute 1 only Program error When a program operation is executed 1 Execute the clear...

Page 722: ...is mounted on a board Standard serial I O mode has following modes Standard serial I O mode 1 The MCU is connected to the serial programmer by using clock synchronous serial I O Standard serial I O m...

Page 723: ...d of ID Code All ID code storage addresses and data must match the combinations listed in Table 30 19 When the forced erase function or standard serial I O mode disable function is not used use anothe...

Page 724: ...erated 30 9 3 Standard Serial I O Mode Disable Function Use the standard serial I O mode disable function in standard serial I O mode When the ID codes in the ID code stored addresses are set to Prote...

Page 725: ...input pin for A D converter When using standard serial I O mode 1 and power supply to VREF is not supplied connect with VSS P0_0 to P0_7 Input port P0 I VCC2 Input a high or low level signal or leave...

Page 726: ...input Notes 1 Control pins and external circuitry will vary depending on the programmer For more information refer to the programmer manual 2 In this example modes are switched between single chip mo...

Page 727: ...power supply to VREF is not supplied connect with VSS P0_0 to P0_7 Input port P0 I VCC2 Input a high or low level signal or leave open P1_0 to P1_7 Input port P1 I VCC2 Input a high or low level signa...

Page 728: ...ect Address 1 OFS1 The OFS1 address is located in block 0 of program ROM 1 When the ROMCR bit in the OFS1 address is 1 ROMCP1 bit enabled and the ROMCP1 bit is set to 0 the ROM code protect function i...

Page 729: ...rrupt vector The ID code check function cannot be disabled Even if the protect using the ID code check function is unnecessary input the appropriate ID code when using a serial programmer or debugger...

Page 730: ...t during command execution because the address match interrupt vector is located in ROM Do not use a non maskable interrupt during block 0 erase because fixed vector is located in block 0 30 11 3 5 Re...

Page 731: ...s 1 CPU rewrite mode enabled The PM13 bit returns to the former value by setting the FMR01 bit to 0 CPU rewrite mode disabled When the PM13 bit is changed during CPU rewrite mode the value of the PM13...

Page 732: ...rocesses in user boot mode then restart the MCU in single chip mode before the input level changes To use user boot mode after standard serial I O mode turn off the power when exiting standard serial...

Page 733: ...I Input voltage RESET CNVSS BYTE P6_0 to P6_7 P7_2 to P7_7 P8_0 to P8_4 P8_6 P8_7 P9_0 to P9_7 P10_0 to P10_7 XIN 0 3 to VCC1 0 3 1 V P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P...

Page 734: ...SS BYTE 0 8VCC1 VCC1 V P7_0 P7_1 P8_5 0 8VCC1 6 5 V CEC 0 7VCC1 V VIL Low input voltage P3_1 to P3_7 P4_0 to P4_7 P5_0 to P5_7 0 0 2VCC2 V P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 in single chip mo...

Page 735: ...P10_0 to P10_7 10 0 mA IOL avg Low average output current 1 P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_7 P9_0 to P9_7 P10_0 to P...

Page 736: ...solution AVCC VCC1 VCC2 VREF 10 Bits INL Integral non linearity error 10 bits VCC1 5 0 V AN0 to AN7 input AN0_0 to AN0_7 input AN2_0 to AN2_7 input ANEX0 ANEX1 input Note 2 3 LSB VCC1 3 3 V AN0 to AN7...

Page 737: ...Characteristics 2 2 1 VCC1 AVCC 3 0 to 5 5 V VCC2 VREF VSS AVSS 0 V at Topr 20 C to 85 C 40 C to 85 C unless otherwise specified Symbol Parameter Measuring Condition Standard Unit Min Typ Max AD A D...

Page 738: ...retain data on the erasure cycles of each block and limit the number of erase operations to a certain number 4 If an error occurs during block erase attempt to execute the clear status register comman...

Page 739: ...peration In addition averaging the erasure cycles between blocks A and B can further reduce the actual erasure cycles It is also advisable to retain data on the erasure cycles of each block and limit...

Page 740: ...d Symbol Parameter Condition Standard Unit Min Typ Max Vdet0 Voltage detection level Vdet0_0 1 When VCC1 is falling 1 60 1 90 2 20 V Voltage detection level Vdet0_2 1 When VCC1 is falling 2 55 2 85 3...

Page 741: ...in Typ Max Vdet2 Voltage detection level Vdet2_0 When VCC1 is falling 3 50 4 00 4 50 V Hysteresis width at the rising of VCC1 in voltage detector 2 0 15 V Voltage detector 2 response time 2 When VCC1...

Page 742: ...ified Symbol Parameter Condition Standard Unit Min Typ Max td P R Internal power supply stability time when power is on 1 5 ms td R S STOP release time 150 s td W S Low power mode wait mode release ti...

Page 743: ...16 125 kHz On Chip Oscillator Electrical Characteristics VCC1 2 7 to 5 5 V Topr 20 C to 85 C 40 C to 85 C unless otherwise specified Symbol Parameter Condition Standard Unit Min Typ Max fOCO S 125 kHz...

Page 744: ...P7_7 P8_0 to P8_4 P8_6 P8_7 P9_0 to P9_7 P10_0 to P10_7 IOH 200 A VCC1 0 3 VCC1 V P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 IOH 200 A VCC2 0 3 VCC2 VOH High output...

Page 745: ...N3 SIN4 SD PMC0 PMC1 SCLMM SDAMM CEC ZP IDU IDV IDW 0 5 2 0 V VT VT Hysteresis RESET 0 5 2 5 V IIH High input current P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0...

Page 746: ...Hz on chip oscillator stopped 20 7 mA f BCLK 20 MHz XIN 20 MHz square wave 125 kHz on chip oscillator stopped 16 0 mA 125 kHz on chip oscillator mode Main clock stopped 125 kHz on chip oscillator on n...

Page 747: ...25 kHz on chip oscillator stopped 22 7 mA f BCLK 20 MHz XIN 20 MHz square wave 125 kHz on chip oscillator stopped 17 0 mA 125 kHz on chip oscillator mode Main clock stopped 125 kHz on chip oscillator...

Page 748: ...nput Note 1 The condition is VCC1 VCC2 3 0 to 5 0 V Figure 31 6 External Clock Input XIN Input Table 31 21 Reset Input RESET Input Symbol Parameter Standard Unit Min Max tw RSTL RESET input low pulse...

Page 749: ...g Input in Timer Mode Symbol Parameter Standard Unit Min Max tc TA TAiIN input cycle time 400 ns tw TAH TAiIN input high pulse width 200 ns tw TAL TAiIN input low pulse width 200 ns Table 31 25 Timer...

Page 750: ...imer A Input Two Phase Pulse Input in Event Counter Mode Table 31 27 Timer A Input Two Phase Pulse Input in Event Counter Mode Symbol Parameter Standard Unit Min Max tc TA TAiIN input cycle time 800 n...

Page 751: ...input low pulse width counted on one edge 40 ns tc TB TBiIN input cycle time counted on both edges 200 ns tw TBH TBiIN input high pulse width counted on both edges 80 ns tw TBL TBiIN input low pulse w...

Page 752: ...Serial Interface Symbol Parameter Standard Unit Min Max tc CK CLKi input cycle time 200 ns tw CKH CLKi input high pulse width 100 ns tw CKL CLKi input low pulse width 100 ns td C Q TXDi output delay...

Page 753: ...Unit Min Max Min Max tBUF Bus free time 4 7 1 3 s tHD STA Hold time in start condition 4 0 0 6 s tLOW Hold time in SCL clock 0 status 4 7 1 3 s tR SCL SDA signals rising time 1000 20 0 1 Cb 300 ns tH...

Page 754: ...3 waits setting 3 Calculated according to the BCLK frequency as follows n is 2 for 2 waits setting and 3 for 3 waits setting Table 31 34 Memory Expansion Mode and Microprocessor Mode Symbol Parameter...

Page 755: ...sion Mode and Microprocessor Mode Effective in wait state setting RDY input RD BCLK Separate bus Multiplexed bus RD Separate bus Multiplexed bus tsu RDY BCLK th BCLK RDY Measuring conditions y V V 5 V...

Page 756: ...le 31 35 Memory Expansion Mode and Microprocessor Mode in No Wait State Setting Symbol Parameter Measuring Condition Standard Unit Min Max td BCLK AD Address output delay time See Figure 31 14 25 ns t...

Page 757: ...R01UH0136EJ0210 Rev 2 10 Page 724 of 800 Jul 31 2012 M16C 64A Group 31 Electrical Characteristics Figure 31 14 Ports P0 to P10 Measurement Circuit P6 P7 P8 P10 P9 P0 P1 P2 P3 P4 P5 30 pF...

Page 758: ...D 0ns min td BCLK AD td BCLK ALE 4ns min th RD AD 0ns min td BCLK RD th BCLK RD 0ns min tac1 RD DB tsu DB RD th RD DB th BCLK ALE 25ns max td BCLK CS 25ns max td BCLK CS 25ns max 0ns min th BCLK CS tc...

Page 759: ...g External Area Symbol Parameter Measuring Condition Standard Unit Min Max td BCLK AD Address output delay time See Figure 31 14 25 ns th BCLK AD Address output hold time in relation to BCLK 0 ns th R...

Page 760: ...S 4ns min th BCLK ALE 0ns min th RD AD td BCLK RD 25ns max 0ns min th BCLK RD n 0 5 t 45 ns max cyc tsu DB RD 0ns min th RD DB td BCLK CS 25ns max 0ns min th BCLK CS tcyc td BCLK AD 25ns max 0ns min t...

Page 761: ...ess output hold time in relation to WR Note 1 ns td BCLK CS Chip select output delay time 25 ns th BCLK CS Chip select output hold time in relation to BCLK 0 ns th RD CS Chip select output hold time i...

Page 762: ...t 45 ns max cyc tac3 RD DB tsu DB RD th RD DB 0ns min 0ns min td AD RD th BCLK AD 0ns min 15ns max td BCLK ALE th BCLK ALE 4ns min td BCLK AD 25ns max th RD AD 0 5 t 10 ns min cyc 25ns max td BCLK RD...

Page 763: ...A 0 5 CEC IOL 1 mA 0 0 5 V VOL Low output voltage XOUT HIGH POWER IOL 0 1 mA 0 5 V LOW POWER IOL 50 A 0 5 Low output voltage XCOUT HIGH POWER With no load applied 0 V LOW POWER With no load applied 0...

Page 764: ...25 kHz on chip oscillator stopped 20 7 mA f BCLK 20 MHz XIN 20 MHz square wave 125 kHz on chip oscillator stopped 16 0 mA 125 kHz on chip oscillator mode Main clock stopped 125 kHz on chip oscillator...

Page 765: ...z on chip oscillator stopped 22 7 mA f BCLK 20 MHz XIN 20 MHz square wave 125 kHz on chip oscillator stopped 17 0 mA 125 kHz on chip oscillator mode Main clock stopped 125 kHz on chip oscillator on no...

Page 766: ...nput Note 1 The condition is VCC1 VCC2 2 7 to 3 0 V Figure 31 19 External Clock Input XIN Input Table 31 41 Reset Input RESET Input Symbol Parameter Standard Unit Min Max tw RSTL RESET input low pulse...

Page 767: ...g Input in Timer Mode Symbol Parameter Standard Unit Min Max tc TA TAiIN input cycle time 600 ns tw TAH TAiIN input high pulse width 300 ns tw TAL TAiIN input low pulse width 300 ns Table 31 45 Timer...

Page 768: ...Timer A Input Two Phase Pulse Input in Event Counter Mode Table 31 47 Timer A Input Two Phase Pulse Input in Event Counter Mode Symbol Parameter Standard Unit Min Max tc TA TAiIN input cycle time 2 s...

Page 769: ...nput low pulse width counted on one edge 60 ns tc TB TBiIN input cycle time counted on both edges 300 ns tw TBH TBiIN input high pulse width counted on both edges 120 ns tw TBL TBiIN input low pulse w...

Page 770: ...Serial Interface Symbol Parameter Standard Unit Min Max tc CK CLKi input cycle time 300 ns tw CKH CLKi input high pulse width 150 ns tw CKL CLKi input low pulse width 150 ns td C Q TXDi output delay t...

Page 771: ...Unit Min Max Min Max tBUF Bus free time 4 7 1 3 s tHD STA Hold time in start condition 4 0 0 6 s tLOW Hold time in SCL clock 0 status 4 7 1 3 s tR SCL SDA signals rising time 1000 20 0 1 Cb 300 ns tH...

Page 772: ...3 for 3 waits setting 3 Calculated according to the BCLK frequency as follows n is 2 for 2 waits setting 3 for 3 waits setting Table 31 54 Memory Expansion Mode and Microprocessor Mode Symbol Paramet...

Page 773: ...sion Mode and Microprocessor Mode Effective in wait state setting RDY input RD BCLK Separate bus Multiplexed bus RD Separate bus Multiplexed bus tsu RDY BCLK th BCLK RDY Measuring conditions y V V 3 V...

Page 774: ...able 31 55 Memory Expansion and Microprocessor Modes in No Wait State Setting Symbol Parameter Measuring Condition Standard Unit Min Max td BCLK AD Address output delay time See Figure 31 27 30 ns th...

Page 775: ...R01UH0136EJ0210 Rev 2 10 Page 742 of 800 Jul 31 2012 M16C 64A Group 31 Electrical Characteristics Figure 31 27 Ports P0 to P10 Measurement Circuit P6 P7 P8 P10 P9 P0 P1 P2 P3 P4 P5 30 pF...

Page 776: ...0ns min td BCLK AD td BCLK ALE 4ns min th RD AD 0ns min td BCLK RD th BCLK RD 0ns min tac1 RD DB 0 5 t 60 ns max cyc tsu DB RD th RD DB th BCLK ALE 30ns max td BCLK CS 30ns max td BCLK CS 30ns max 0ns...

Page 777: ...g External Area Symbol Parameter Measuring Condition Standard Unit Min Max td BCLK AD Address output delay time See Figure 31 27 30 ns th BCLK AD Address output hold time in relation to BCLK 0 ns th R...

Page 778: ...S 4ns min th BCLK ALE 0ns min th RD AD td BCLK RD 30ns max 0ns min th BCLK RD tsu DB RD 0ns min th RD DB td BCLK CS 30ns max 0ns min th BCLK CS tcyc td BCLK AD 30ns max 0ns min th BCLK AD td BCLK ALE...

Page 779: ...dress output hold time in relation to WR Note 1 ns td BCLK CS Chip select output delay time 50 ns th BCLK CS Chip select output hold time in relation to BCLK 0 ns th RD CS Chip select output hold time...

Page 780: ...max cyc tac3 RD DB tsu DB RD th RD DB 0ns min 0ns min td AD RD th BCLK AD 0ns min 25ns max td BCLK ALE th BCLK ALE 4ns min td BCLK AD 50ns max th RD AD 0 5 t 10 ns min cyc 40ns max td BCLK RD 0ns min...

Page 781: ...pproximately 0 1 F across pins VCC1 and VSS and pins VCC2 and VSS using the shortest and thickest possible wiring Figure 32 1 shows the Bypass Capacitor Connection Figure 32 1 Bypass Capacitor Connect...

Page 782: ...2 Bit Rate Register U2BRG 026Bh to 026Ah UART2 Transmit Buffer Register U2TB 0273h SI O3 Bit Rate Register S3BRG 0277h SI O4 Bit Rate Register S4BRG 0289h UART5 Bit Rate Register U5BRG 028Bh to 028Ah...

Page 783: ...ructions Function Mnemonic Transfer MOVDir Bit processing BCLR BMCnd BNOT BSET BTSTC and BTSTS Shifting ROLC RORC ROT SHA and SHL Arithmetic operation ABS ADC ADCF ADD DEC DIV DIVU DIVX EXTS INC MUL M...

Page 784: ...e PRC2 bit to 1 write enabled by writing to a given SFR the PRC2 bit becomes 0 write disabled Change the registers protected by the PRC2 bit in the next instruction after setting the PRC2 bit to 1 Mak...

Page 785: ...address to 0 voltage monitor 0 reset enabled after hardware reset and the VDSEL1 bit to 0 Vdet0_2 In this case the voltage monitor 0 reset is enabled the VW0C0 bit and bit 6 in the VW0C register are...

Page 786: ...d by a hardware reset but becomes 0 not detected from a voltage monitor 0 reset 32 4 4 Hardware Reset when VCC1 Vdet0 When a hardware reset is executed while VCC1 Vdet0 the voltage monitor 0 reset is...

Page 787: ...om the CLKOUT pin is listed below Outputting the main clock 1 Set the PRC0 bit in the PRCR register to 1 write enabled 2 Set the CM11 bit in the CM1 register the CM07 bit in the CM0 register and the C...

Page 788: ...Also if a potential difference attributed to the noise occurs between the VSS level of the MCU and the VSS level of the crystal ceramic resonator an accurate clock is not input to the MCU 32 5 2 2 Lar...

Page 789: ...in operation or a program runaway Figure 32 8 Wiring of Signal Line Whose Level Changes at High Speed 32 5 3 CPU Clock Technical update number TN M16C 109 0309 When an external clock is input from th...

Page 790: ...Table 32 4 Acceptable Range of Power Supply Ripple Symbol Parameter Standard Unit Min Typ Max f ripple Power supply ripple allowable frequency VCC1 10 kHz VP P ripple Power supply ripple allowable amp...

Page 791: ...from 0 to 1 3 Wait for 1 ms 4 Change the bit from VC25 to VC27 that was originally 1 back to 1 voltage detector on 32 5 6 2 When Using 125 kHz On chip Oscillator Mode or 125 kHz On chip Oscil lator L...

Page 792: ...d mode To enter wait mode from low cur rent consumption read mode set the FMR23 bit in the FMR2 register to 0 low current consump tion read mode disabled Do not enter wait mode from CPU rewrite mode T...

Page 793: ...op mode when the oscillator stop restart detect function is enabled To enter stop mode set the CM20 bit in the CM2 register to 0 oscillator stop restart detect function disabled Do not enter stop mode...

Page 794: ...32 7 2 External Bus When a hardware reset power on reset or voltage monitor 0 reset is performed with a high level input on the CNVSS pin the internal ROM cannot be read 32 7 3 External Access Immedi...

Page 795: ...C register is 1 three phase output forcible cutoff by input on SD pin enabled the following pins become high impedance P7_2 CLK2 TA1OUT V P7_3 CTS2 RTS2 TA1IN V P7_4 TA2OUT W P7_5 TA2IN W P8_0 TA4OUT...

Page 796: ...the first instruction after reset only all interrupts are disabled 32 9 3 NMI Interrupt When not using the NMI interrupt set the PM24 bit in the PM2 register to 0 NMI interrupt dis abled The NMI inte...

Page 797: ...0 Procedure for Changing the Interrupt Generate Source Use the MOV instruction to set the IR bit to 0 interrupt not requested 3 Disable interrupts 2 3 Change the interrupt source including a mode chan...

Page 798: ...he internal bus and the instruction queue buffer Example 1 Using the NOP instruction to pause the program until the interrupt control register is modified INT_SWITCH1 FCLR I Disable interrupts AND B 0...

Page 799: ...cessary for the signal input to pins INT0 through INT7 regardless of the CPU operation clock If the POL bit in registers INT0IC to INT7IC bits IFSR7 to IFSR0 in the IFSR register or bits IFSR31 to IFS...

Page 800: ...210 Rev 2 10 Page 767 of 800 Jul 31 2012 M16C 64A Group 32 Usage Notes 32 10 Notes on the Watchdog Timer After the watchdog timer interrupt is generated use the WDTR register to refresh the watchdog t...

Page 801: ...o 1 set the value to be written to the DMAS bit to 1 to retain its state immediately before writing Similarly when writing to the DMAE bit with a read modify write instruction set the DMAS bit to 1 to...

Page 802: ...r occurs when an interrupt request of the selected timer is generated An event or trigger occurs while an interrupt is disabled because an interrupt request signal is generated regardless of the I fla...

Page 803: ...t puts a high level signal when it is 1 After one cycle of the CPU clock the IR bit in the TAiIC register becomes 1 interrupt requested 32 12 4 2 Delay between the Trigger Input and Timer Output As th...

Page 804: ...e the timer Ai interrupt IR bit set the IR bit to 0 by a program after the changes listed above are made 32 12 5 2 Stop While Counting When setting the TAiS bit to 0 count stopped during PWM pulse out...

Page 805: ...output mode To use the timer Ai interrupt IR bit set the IR bit to 0 by a program after the changes listed above are made 32 12 6 2 Stop While Counting When setting the TAiS bit to 0 count stopped du...

Page 806: ...ead before it starts counting and after a value is set in the TBi register while not counting the set value is read 32 13 3 Timer B Event Counter Mode 32 13 3 1 Reading the Timer While counting the co...

Page 807: ...rations between Count Start and the First Measurement When a count is started and the first active edge is input an undefined value is transferred to the reload register At this time a timer Bi interr...

Page 808: ...otes on Timer A and 18 5 Notes on Timer B 32 14 2 Influence of SD When a low level signal is applied to the SD pin while the IVPCR1 bit in the TB2SC register is 1 three phase output forcible cutoff by...

Page 809: ...fter setting the TSTART bit to 0 During this time do not access registers associated with the real time clock other than the TCSTF bit Note 1 Registers associated with the real time clock RTCSEC RTCMI...

Page 810: ...ng to Figure 32 11 Time Data Reading Figure 32 11 Time Data Reading Using read results if they are the same value twice 1 Read the values necessary from time data bits 2 Read the same bit as 1 and com...

Page 811: ...mode Using an interrupt Set the DRINT bit in the PMCiINT register to 1 data reception complete interrupt enabled and read the registers within the PMCi interrupt routine Monitoring by a program 1 Set...

Page 812: ...Page 779 of 800 Jul 31 2012 M16C 64A Group 32 Usage Notes 32 16 4 Combined Operation When using combined operation set same value to bits TYP1 to TYP0 in the PMC0CON1 register and bits TYP1 to TYP0 i...

Page 813: ...hen the RTS function is used with an external clock the RTSi pin i 0 to 2 5 to 7 outputs a low level signal which informs the transmitting side that the MCU is ready for a receive operation The RTSi p...

Page 814: ...e UiTB register for each receive operation If the reception is started while an external clock is selected and the TXEPT bit in the UiC0 register is 1 no data present in transmit register meet the las...

Page 815: ...ample of hold and setup times when generating a start stop condition Calculation example when setting 100 kbps UiBRG count source f1 20 MHz UiBRG register setting value n 100 1 SDA digital delay setti...

Page 816: ...slave mode and the TXEPT bit in the UiC0 register is 1 no data present in transmit register meet the last requirement when the external clock is high Requirements to start transmission in no particula...

Page 817: ...on reception is stopped Read receive data from the SiTRR register while transmission reception is stopped The IR bit in the SiIC register becomes 1 interrupt requested during output of the eighth bit...

Page 818: ...the S1D0 register during transmission reception 32 19 2 3 S20 Register Do not change bits other than the ACKBIT bit in the S20 register during transmission reception 32 19 2 4 S3D0 Register Do not use...

Page 819: ...evices drive the SCLMM line low no normal stop condition is generated This is because the SDAMM line is released while the SCLMM line is still driven low Figure 32 13 Abnormal Waveform Abnormal state...

Page 820: ...e of the SCLMM line Interrupts disabled P7_1 1 SCLMM line is high No Enable SCL SDA interrupt End wait for an interrupt Reset the MMI2C module P7_0 1 SDAMM line becomes high Yes Yes End SCL SDA interr...

Page 821: ...essively 1 Change the bit to 0 2 Wait for one or more cycles of the count source 3 Change the same bit to 1 Example when reading the bit rewritten under the influence of another bit after reception is...

Page 822: ...32 16 Example of Pin Configuration 32 21 4 Register Access Write registers ADCON0 excluding the ADST bit ADCON1 and ADCON2 when A D conversion stops before a trigger is generated After A D conversion...

Page 823: ...T register follow these steps 1 Change bits AINRST1 to AINRST0 in the AINRST register 2 Wait for one cycle of AD 3 Set the ADST bit in the ADCON0 register to 1 A D conversion started 32 21 9 Detecting...

Page 824: ...one cycle of fAD Figure 32 18 Period When the ADi Register Value is Rewritten A D conversion AD0 register AD1 register AD7 register One cycle of fAD AN0 AN1 AN2 AN7 AN0 AN1 One cycle of fAD One cycle...

Page 825: ...Notes on D A Converter 32 22 1 When Not Using the D A Converter When not using the D A converter set the DAiE bit i 0 1 in the DACON register to 0 output disabled and the DAi register to 00h in order...

Page 826: ...rrupt vector The ID code check function cannot be disabled Even if the protect using the ID code check function is unnecessary input the appropriate ID code when using a serial programmer or debugger...

Page 827: ...t during command execution because the address match interrupt vector is located in ROM Do not use a non maskable interrupt during block 0 erase because fixed vector is located in block 0 32 23 3 5 Re...

Page 828: ...1 CPU rewrite mode enabled The PM13 bit returns to the former value by setting the FMR01 bit to 0 CPU rewrite mode disabled When the PM13 bit is changed during CPU rewrite mode the value of the PM13...

Page 829: ...rocesses in user boot mode then restart the MCU in single chip mode before the input level changes To use user boot mode after standard serial I O mode turn off the power when exiting standard serial...

Page 830: ...1 DIMENSIONS 1 AND 2 DO NOT INCLUDE MOLD FLASH NOTE DIMENSION 3 DOES NOT INCLUDE TRIM OFFSET Detail F L A 2 A 1 3 1 2 F 1 30 31 50 51 80 81 100 Index mark y x c H E E D HD A bp ZD Z E e Terminal cross...

Page 831: ...L 240 DM2CON 239 DM2SL 240 DM3CON 239 DM3SL 240 DTT 336 F FMR0 111 661 FMR1 664 FMR2 112 665 FMR6 666 I ICTB2 337 IDB0 IDB1 336 IFSR 199 IFSR2A 198 IFSR3A 197 IICIC 195 INT0IC to INT2IC 196 INT3IC 196...

Page 832: ...195 S5TIC 195 S6TIC 195 S7TIC 195 SAR0 to SAR3 237 SCLDAIC 195 T TA0IC to TA4IC 195 TA0MR to TA4MR 266 TA0 to TA4 261 TA1 TA2 TA4 331 TA11 TA21 TA41 262 331 TABSR 262 309 TACS0 to TACS2 257 TAOW 260 T...

Page 833: ...M16C 64A Group REGISTER INDEX R01UH0136EJ0210 Rev 2 10 Page 800 of 800 Jul 31 2012 VD1LS 66 VW0C 67 VW1C 68 VW2C 70 225 VWCE 65 W WDC 228 WDTR 227 WDTS 227...

Page 834: ...Motor Control Timer Function 327 347 352 Table 19 2 Three Phase Motor Control Timer Function Specifications 2 2 Table 19 9 Three Phase Mode 0 Specifications and Table 19 12 Three Phase Mode 1 Specific...

Page 835: ...ous versions for the items revised or added in previous versions 2 10 Jul 31 2012 785 32 19 3 Low High level Input Voltage and Low level Output Voltage Added REVISION HISTORY M16C 64A Group User s Man...

Page 836: ...e Monitor 2 Control Register VW2C partially modified 67 7 3 Optional Function Select Area partially added 67 7 3 1 Optional Function Select Address 1 OFS1 partially modified 73 76 Figure 7 6 and Figur...

Page 837: ...m 2 3 PMCi Input partially modified 402 Table 22 3 Registers PMC0 Circuit partially modified 421 22 3 1 1 Count Source partially modified 422 22 3 1 2 PMCi Input partially added 428 22 3 2 4 Compare F...

Page 838: ...ally modified 677 Table 30 13 Difference in Reading of Status Register added 677 30 8 4 1 to 30 8 4 3 Sequencer Status Bits SR7 and FMR00 Erase Status Bits SR5 and FMR07 Program Status Bits SR4 and FM...

Page 839: ...ister Changed reset value from 000X 0000b Overall 002Ah Voltage Monitor 0 Control Register Changed reset value from 1100 XX10b Overall 002Bh Voltage Monitor 1 Control Register Changed reset value from...

Page 840: ...reset other than hardware reset Deleted notes 1 to 8 63 7 2 2 Voltage Detector Operation Enable Register VCR2 Changed b4 64 7 2 3 Voltage Monitor Function Select Register VWCE Changed name and functi...

Page 841: ...ted g and h from 125 kHz on chip oscillator mode 120 9 3 3 Wait Mode Changed the last 2 lines 120 9 3 3 2 Entering Wait Mode Added line 5 and below 121 9 3 3 4 Exiting Wait Mode Deleted the 2 paragrap...

Page 842: ...13 5 Rewriting the Interrupt Control Register and 14 13 6 Instruction to Rewrite the Interrupt Control Register Rewritten from 14 13 5 Rewriting the Interrupt Control Register in the previous version...

Page 843: ...SEL0 and PSEL1 411 22 2 5 PMCi Status Register PMCiSTS i 0 1 Added the explanations below the register diagram Added the condition to become 0 of the CPFLG bit Changed the explanation and condition to...

Page 844: ...I O Mode Deleted 454 23 2 2 UARTi Transmit Receive Mode Register UiMR i 0 to 2 5 to 7 Added the explanation of bits SMD2 to SMD0 455 23 2 3 UARTi Bit Rate Register UiBRG i 0 to 2 5 to 7 Added the sett...

Page 845: ...s 499 Table 23 20 Special Mode 2 Specifications Deleted the description of slave mode in the Transmit receive clock row Deleted note 1 500 Figure 23 32 Serial Bus Communication Control Example in Spec...

Page 846: ...explanations for bits CRISE2 to CRISE0 CFALL1 CFALL0 and CABTWEN Changed the CABTEN bit explanation Changed the CREGFLG bit explanation 591 26 2 6 CEC Interrupt Source Select Register CISEL Deleted th...

Page 847: ...is input in the FMR01 bit explanation Added the last line in the FMR02 explanation Added the description for the FMR22 bit to the last paragraph of the FMSTP bit explanation 663 30 3 2 Flash Memory C...

Page 848: ...ode 697 30 11 3 10 Software Command Changed b Added or same command more than once to c Added e 697 30 11 3 14 Suspending the Auto Erase and Auto Program Operations Added the details on reset to the f...

Page 849: ...h bullets 758 32 6 3 Stop Mode Changed until main clock oscillation is stabilized in first bullet to for 20 fOCO S cycles or more Added lines 6 and 7 to the third bullet Deleted fourth bullet in the p...

Page 850: ...Partially changed the discription 791 32 23 1 OFS1 Address and ID Code Storage Address Added 792 32 23 3 2 CPU Rewrite Mode Select Added the description for the FMR60 bit 792 32 23 3 7 DMA transfer Ad...

Page 851: ...M16C 64A Group User s Manual Hardware Publication Date Rev 1 01 Feb 03 2009 Rev 2 10 Jul 31 2012 Published by Renesas Electronics Corporation...

Page 852: ...204 205 AZIA Center No 1233 Lujiazui Ring Rd Pudong District Shanghai 200120 China Tel 86 21 5877 1818 Fax 86 21 6887 7858 7898 Renesas Electronics Hong Kong Limited Unit 1601 1613 16 F Tower 2 Grand...

Page 853: ...M16C 64A Group R01UH0136EJ0210...

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