469
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
A.
Serial RapidIO Protocol Overview
The
RapidIO Physical Layer 1x/4x LP-Serial Specification
addresses the physical layer requirements
for devices utilizing an electrical serial connection medium. This specification defines a full duplex
serial physical layer interface (link) between devices using unidirectional differential signals in each
direction. Further, it allows ganging of four serial links for applications requiring higher link
performance. It also defines a protocol for link management and packet transport over a link.
RapidIO systems are comprised of end point processing elements and switch processing elements. The
RapidIO interconnect architecture is partitioned into a layered hierarchy of specifications which
includes the
Logical
,
Common
Transport
, and
Physical
layers. The Logical layer specifications define
the operations and associated transactions by which end point processing elements communicate with
each other. The Common Transport layer defines how transactions are routed from one end point
processing element to another through switch processing elements. The Physical Layer defines how
adjacent processing elements electrically connect to each other. RapidIO packets are formed through
the combination of bit fields defined in the Logical, Common Transport, and Physical Layer
specifications. TheTsi574 fully manages the end to end link on each port.
A.1
Protocol
The RapidIO Physical Layer 1x/4x LP-Serial specification
defines the protocol for packet delivery
between serial RapidIO devices including packet and control symbol transmission, flow control, error
management, and other device to device functions. A particular device may not implement all of the
mode selectable features presented in the RapidIO specification.
The 1x/4x LP-Serial physical layer specification has the following properties:
•
Embeds the transmission clock with data using an 8B/10B encoding scheme.
•
Supports one serial differential pair, referred to as one lane, or four ganged serial differential pairs,
referred to as four lanes, in each direction.
•
Allows switching packets between RapidIO 1x/4x LP-Serial Ports and RapidIO Physical Layer
8/16 LP-LVDS ports without requiring packet manipulation.
•
Employs similar retry and error recovery protocols as the RapidIO Physical Layer 8/16 LP-LVDS
specification.
•
Supports transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbit/s)
per lane.
A.2
Packets
A RapidIO 1x/4x LP-Serial packet is formed by prefixing a 10-bit physical layer header to the
combined RapidIO transport and logical layer bit fields followed by an appended 16-bit CRC field.
The sum of all of the bit fields adds 20 bytes to the encapsulated data packet size. The maximum data
field size is 256 bytes resulting in a maximum packet size of 276 bytes.
