Renesas IDT Tsi574, User Manual

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13. I2C Registers > Register Descriptions 440
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
13.2.19 Externally Visible I
2
C Status Register
This register provides a summary view of status of the Tsi574. It can be polled by an external system
management device. Any bit masked by its related enable, changing from 0 to 1, will cause
ALERT_FLAG to be set in the
“Externally Visible I
2
C Slave Access Status Register” , and the Tsi574
to respond to the Alert Response Address if the ALRT_EN bit is set in the “I
2
C Slave Configuration
Register” . The related enables are present in the “Externally Visible I
2
C Enable Register” . If all
masked status bits are 0, then the ALERT_FLAG clears. The ALERT_FLAG also clears when the
slave responds to the Alert Response Address, and not set again until there is a change in the status.
Bits [0] are read only from the register bus, but R/W1C from the I
2
C bus through the slave interface.
They are set when the corresponding event occurs within the Tsi574, and held asserted until an external
I
2
C master writes a 1 to that position to clear the event. If an event is still asserting at the time the W1C
occurs, the bit remains set.
The software status bits [1:3] are R/W from the register bus. They can be set or cleared by software,
and thereby used for any system purpose. An external I
2
C master can write 1 to those bits to clear them.
If the W1C occurs at the same time as software is writing the bit, the software written value will take
precedence.
This register corresponds to the I
2
C peripheral addresses 0x80 through 0x83. This register is affected
by a reset controlled by the “I
2
C Reset Register” . All status will be cleared, including the software
status bits. Chip status will re-assert after a SRESET is released in the “I
2
C Reset Register” only if that
chip event occurs again.
Register name: EXI2C_STAT
Reset value: 0xFFFF_FFFF
Register offset: 0x1D280
Bits 0 1 2 3 4 5 6 7
00:07 RESET SW_
STAT2
SW_
STAT1
SW_
STAT0
OMBW IMBR I2C TEA
08:15 RCS MCS Reserved LOGICAL MC_LAT MCE
16:23 Reserved
24:31 PORT7 PORT6 PORT5 PORT4 PORT3 PORT2 PORT1 PORT0
Bits Name Description Type
Reset
Value
0 RESET Enable RESET Alert Response
0 = Status asserted will not enable setting ALERT_FLAG
1 = Status asserted will enable setting ALERT_FLAG
R/W 1
1 SW_STAT2 Enable SW_STAT2 Alert Response
0 = Status asserted will not enable setting ALERT_FLAG
1 = Status asserted will enable setting ALERT_FLAG
R/W 1