Renesas IDT Tsi574, User Manual

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12. Serial RapidIO Registers > IDT-Specific RapidIO Registers 306
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.8.5 RapidIO Port x Route Config DestID CSR
This register and SPx_ROUTE_CFG_PORT operate together to provide indirect read and write access
to the LUTs. The registers are identical to RIO_ROUTE_CFG_DESTID and
RIO_ROUTE_CFG_PORT, except the
“RapidIO Port x Route Config Output Port CSR” on page 307
are per-port registers and they include an auto-increment bit to increment the contents of the
destination ID register after a read or write operation.
Register name: SP{BC,0..7}_ROUTE_CFG_DESTID
Reset value: 0x0000_0000
Register offset: 10070, 11070, 11170, 11270, 11370,
11470, 11570, 11670, 11770
Bits 0 1 2 3 4 5 6 7
00:07 AUTO_INC PAR_INVE
RT
Reserved
08:15 Reserved
16:23 LRG_CFG_DEST_ID[0:7]
24:31 CFG_DEST_ID[8:15]
Bits Name Description Type
Reset
Value
0 AUTO_INC Automatically post-increment the destination ID when the destination ID
is used to perform either a read or a write, through the
“RapidIO Port x
Route Config Output Port CSR” on page 307 .
R/W 0
1 PAR_INVERT Parity Invert
This bit is for testing of interrupt and/or demerit software systems.
0 = Normal operation
1 = Invert the parity bit for each LUT entry written (but not read). This
causes a parity error when the LUT entry is used to route a packet.
R/W 0
2:15 Reserved N/A R 0
16:23 LRG_CFG_D
EST_ID
This field specifies the most significant byte of the destination ID used to
select an entry in the LUT, when the
“RapidIO Port x Route Config
Output Port CSR” on page 307 is read or written.
R/W 0x00
24:31 CFG_DEST_
ID
Specifies the destination ID used to select an entry in the LUT when the
RIO_ROUTE_CFG_PORT register is read or written.
This value increments by one for every write to the “RapidIO Port x
Route Config Output Port CSR” on page 307 when the AUTO_INC bit is
set
R/W 0x00