CHAPTER 4 DESCRIPTION OF FUNCTIONS
User’s Manual S19262EJ3V0UM
44
4.6.4 Cautions on using IR encoder/decoder
(1) Cautions on changing the IR control register settings
Be sure to set bit 4 (IR_RXEN) of the IRCR0 register to 0 (to stop reception) before changing the register
settings that specify the reception by the IR decoder. If this bit is not set to 0, invalid data might be received
due to a sudden signal variation.
The following registers are affected:
Bit 6 (IR_MASK_OFF) and bit 5 (IR_RXPSEL) of IRCR0 register
IRCR1 to IRCR4 registers
(2) Restriction on the XIN clock frequency minimum
The IR decoder uses the XIN clock to sample reception pulses. Therefore, the minimum valid reception pulse
width depends on the XIN clock frequency.
(3) Supported IrDA specifications
The interface protocol prescribed by IrDA concerns the infrared (IR) interface, and the electrical interface (<1>
and <2> in Figure 4-4) is not prescribed. When using the IR encoder/decoder, thoroughly evaluate the
connectivity with the connected devices (such as IR transceivers).
Figure 4-4. IrPHY Ver. 1.4 Block Configuration Example
16550-
compatible
UART
IR encoder
Output driver
and LED
IR transceiver
module
Detector and
receiver
IR decoder
Encoder/
decoder
<2>
<1>
<3>
IR output
IR input
Table 4-4. IrPHY Ver. 1.4 SIR Ratings Related to Data Transfer Speed and Pulse Width
Transfer
Speed
(kbps)
Modulation
Mode
Allowable
Transfer Speed
Error (% of Rate)
Minimum
Pulse Width
(
s)
Pulse Width
x3/16 Nominal
Value (
s)
Maximum
Pulse Width
(
s)
2.4 RZI
0.87
1.41
78.13
88.55
9.6 RZI
0.87
1.41
19.53
22.13
19.2 RZI
0.87
1.41 9.77 11.07
38.4 RZI
0.87
1.41 4.88 5.96
57.6 RZI
0.87
1.41 3.26 4.34
115.2 RZI
0.87
1.41 1.63 2.23
Remark
The pulse widths are defined for the IR output (<3> in Figure 4-4).
