CHAPTER 3 REGISTERS
User’s Manual S19262EJ3V0UM
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* If a register value is changed during operation, normal operation is not guaranteed. In this case, initialize
the register.
Table 3-3. Reception Trigger Level Settings (Bits 7 and 6 of FCR)
Bits 7 to 6 of
IIR
16-byte FIFO Mode
(Bit 5 of FCR Register = 0)
Trigger Level (Bytes)
64-byte FIFO Mode
(Bit 5 of FCR Register = 1)
Trigger Level (Bytes)
00 01
01
01 04
16
10 08
32
11 14
56
Table 3-4. DMA Mode Settings (Bit 3 of FCR and Bits 3 and 2 of HCR0)
Bit 3 of FCR
register
Bits 3 and 2
of HCR0
Receive DMA Request
Transmit DMA Request
0 00
Mode
0
1 00
Mode
1
0
01
Mode 0
Mode 1
1
10
Mode 1
Mode 0
Others (Setting prohibited)
Table 3-5. DMA Modes and DMA Request Generation Conditions
Mode
DMA Request Generation Condition
DMA Request Release Condition
When the DMA access data width is one byte (bit 5 of HCR0 = 0)
Mode 0
The receive FIFO stores 1 or more bytes of data.
The receive FIFO is empty.
Receive DMA
request
Mode 1
The amount of data in the receive FIFO
reached the trigger level or a timeout event
occurred
Note 1
.
The receive FIFO is empty.
Mode 0
The transmit FIFO is empty.
The transmit FIFO stores 1 or more bytes of
data.
Transmit DMA
request
Mode 1
The transmit FIFO is empty.
The transmit FIFO is full.
When the DMA access data width is two bytes (bit 5 of HCR0 = 1).
Mode 0
The receive FIFO stores 2 or more bytes of data.
The receive FIFO stores 1 or fewer bytes of
data
Note 2
.
Receive DMA
request
Mode 1
The trigger level is reached or a timeout event
occurs
Note 1
when the receive FIFO stores 2 or
more bytes of data.
The receive FIFO stores 1 or fewer bytes of
data
Note 2
.
Mode 0
The transmit FIFO is empty.
The transmit FIFO stores 2 or more bytes of
data.
Transmit DMA
request
Mode 1
The transmit FIFO is empty.
The transmit FIFO full
