CHAPTER 3 REGISTERS
User’s Manual S19262EJ3V0UM
15
3.2.2 Interrupt enable register
This register (IER: 5000_0004H (UART0), 5001_0004H (UART1), 5002_0004H (UART2)) enables the issuance of
interrupt requests. Each interrupt can be set up individually for each interrupt source.
The interrupt sources corresponding to bits to which 1 is written are enabled.
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved EDSSI
ELSI
ETBEI
ERBI
Name R/W
Bit
After
Reset
Function
Reserved
R
15:8
0
Reserved. When these bits are read, 0 is returned for each bit.
Reserved
R/W
7:4
0
Reserved. Written data is ignored.
EDSSI
R/W
3
0
Specifies whether to enable the modem status interrupt.
0: Disables the modem status interrupt.
1: Enables the modem status interrupt.
ELSI
R/W
2
0
Specifies whether to enable the reception error (receiver line status)
interrupt.
0: Disables the reception error interrupt.
1: Enables the reception error interrupt.
ETBEI
R/W
1
0
Specifies whether to enable the transmit buffer empty (transmit hold
register (THR) empty) interrupt.
0: Disables the transmit buffer empty interrupt.
1: Enables the transmit buffer empty interrupt.
ERBI
R/W
0
0
Specifies whether to enable the reception completion (received data
available) and timeout interrupts.
0: Disables the reception completion and timeout interrupts.
1: Enables the reception completion and timeout interrupts.
Caution By setting bit 0 to “0”, reception completion and timeouts can be excluded from the interrupt
sources. However, when bit 4 of the HCR0 register is set to 1 (receiver timeout DMA REQ
disable), a timeout error is added to the interrupt sources, regardless of the setting of bit 0.
Remark
A timeout error is detected when either of the following conditions is satisfied while the FIFO stores at
least one character:
<1> The most recent serial character is received before at least the four continuous character times.
<2> The host read the FIFO most recently before four continuous character times.
Four continuous character times is equivalent to four characters of a 12-bit received character (start: 1
bit, data: 8 bits, parity: 1 bit, stop: 2 bits), that is, 768 cycles (for a 16
clock) (12
4
16 = 768 cycles
(for a 16
clock)).
