8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 7
Figure 6. 8V19N850 Reference Clock Input CLK/nCLK AC Coupling Term ination – Exam ple 1
Figure 7. 8V19N850 Reference Clock Input CLK/nCLK AC Coupling Term ination – Exam ple 2
2.2
OX_DPLL Input (OCXO/TCXO)
The XO_DPLL input receives a stable frequency source from OCXO/TCXO mainly for SysAPLL and SysDPLL.
This input can also be used for APLL0, APLL1, and APLL2 phase frequency detector input. The limitation of
frequency range is provided in the 8V19N850 datasheet. When the XO_DPLL input is only used for SysAPLL or
SysDPLL, a stable frequency TCXO/OCXO is required. Low frequency (e.g., 10MHz to 20MHz) is fine. Phase
noise performance is not critical. When the TCXO/OCXO is used for both SysAPLL/SysDPLL and APLL0,
APLL1, both stable frequency and good phase noise performance are required. Higher frequency (e.g., ~ 38MHz
to 54MHz) is recommended for better phase noise performance.
XO_DPLL/nXO_DPLL is a differential high-impedance input with built-in weak pull-up and pull-down resistors.
The input termination is dictated by the signal source driver type. If the driver is a differential driver, see the
examples provided in “Input Termination for Reference Clock Input”. Since most OCXO/TCXO drivers are single-
ended drivers, Figure 8 provides an example of single-ended to XO_DPLL input layout. Not all components in
the footprint are required to be populated because of the varying strength of the driver and trace length in the
layout.
VCC=3.3V
Clock Input
CLK
nCLK
R4
10K
R2
10K
R3
5.1K
R1
5.1K
VCC=3.3V
C1
C2
Differential Signal
Zo
Zo
R5
2 x Zo
VCC=3.3V
Clock Input
CLK
nCLK
C1
C2
Differential Signal
Zo
Zo
R5
Zo
R4
10K
R3
5.1K
R5
Zo
VCC=3.3V
