Renesas 8V19N850 Manual Download Page 15

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8V19N850 Hardware Design Guide

X0120307 Rev.1.0
Mar 25, 2021

Page 15

3. Schematic Example

A reference demonstration board schematic and the board layout are available upon request:

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8V19N850 EVB schematic

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8V19N850 EVB board layout

4. Revision History

Revision

Date

Description

1.0

Mar 25, 2021

Initial release.

Summary of Contents for 8V19N850

Page 1: ...OCXO TCXO 8 2 4 Output Terminations for QCLK and QREF Drivers 9 2 4 1 LVPECL Type Driver Terminations 9 2 4 2 LVDS Type Driver Terminations 14 3 Schematic Example 15 4 Revision History 15 The simplifi...

Page 2: ...PLL 16 VDD_APLL 17 CP_APLL 18 GPIO_0 19 GPIO_1 20 GPIO_2 21 GPIO_3 22 VDD_GPIO 23 QCLK_D0 24 SPI_SEL 36 VDDO_D3 35 nQCLK_D3 34 QCLK_D3 33 VDDO_D2 32 nQCLK_D2 31 QCLK_D2 30 VDDO_D1 29 nQCLK_D1 28 QCLK_...

Page 3: ...further reduce the cutoff frequency and clean up lower frequency noise For the output supplies VDDO_x to reduce output frequency interference the power rails between the output banks that operate at d...

Page 4: ...in N is effective feedback divider Fpd Fvco N Fvco is vco frequency Fpd is the phase detector input frequency 3 Calculate Cs 2 Where is ratio between loop bandwidth and the zero frequency at zero fc f...

Page 5: ...s greater than 10 For example the actual chosen value can be 100 nF from a standard capacitor value to allow room for charge pump current adjustment Cp can be calculated from the equation Cs For 3 Cp...

Page 6: ...ce without AC coupling Figure 6 and Figure 7 provide examples of input driven by a differential driver with AC coupling This section provides only few examples Other termination topologies can also be...

Page 7: ...L SysDPLL and APLL0 APLL1 both stable frequency and good phase noiseperformance are required Higher frequency e g 38MHz to 54MHz is recommended for better phase noise performance XO_DPLL nXO_DPLL is a...

Page 8: ...onjunctionwith an OCXO at the XO_DPLL input the XO is used for APLL0 APLL1 or APLL2 This OCSI input must be a good phase noise performance and higher frequency 38MHz to 54MHz The OCXO to the XO_DPLL t...

Page 9: ...kon U7842 or different frequency in the same product family TXC OG48070001 or different frequency in the same product family CTS17 or different frequency in the same product family 2 4 Output Terminat...

Page 10: ...on in Figure 11 Output Supply Voltage Output Amplitude VTT VDDO_V 1 8V 350mV VDDO_v 1 50V 500mV VDDO_v 1 75V VDDO_V 2 5V 350mV VDDO_v 1 50V 500mV VDDO_v 1 75V VDDO_V 3 3V 350mV VDDO_v 1 50V 500mV VDDO...

Page 11: ...ues for Output Termination in Figure 12 Output Supply Voltage Output Amplitude R1 R3 R2 R4 VDDO_V 1 8V 350mV 350 60 500mV No pop 50 VDDO_V 2 5V 350mV 125 83 500mV 166 71 VDDO_V 3 3V 350mV 92 110 500mV...

Page 12: ...ble 5 Resistor Values for Output Termination in Figure 13 Output Supply Voltage Amplitude R3 VDDO_V 1 8V 350mV 21 4 500mV 0 VDDO_V 2 5V 350mV 71 4 500mV 41 VDDO_V 3 3V 350mV 128 500mV 86 750mV 57 1000...

Page 13: ...tion Table 6 Resistor Values for Output Termination in Figure 14 Output Supply Voltage Amplitude R1 R2 VDDO_V 1 8V 350mV 93 500mV 55 VDDO_V 2 5V 350mV 192 500mV 133 VDDO_V 3 3V 350mV 300 500mV 222 750...

Page 14: ...see the note below Figure 17 Figure 15 LVDS Style Driver Termination DC Coupled Figure 16 LVDS Style Alternative Driver Termination DC Coupled Figure 17 LVDS Style Alternative Driver Termination AC Co...

Page 15: ...25 2021 Page 15 3 Schematic Example A reference demonstration board schematic and the board layout are available upon request 8V19N850 EVB schematic 8V19N850 EVB board layout 4 Revision History Revisi...

Page 16: ...e intended for developers skilled in the art designing with Renesas products You are solely responsible for 1 selecting the appropriate products for your application 2 designing validating and testing...