Renesas 89HPES24T3G2ZBAL, User Manual

Page: 84 / 165

IDT Configuration Registers
PES24T3G2 User Manual 8 - 2 February 22, 2012
Notes
Figure 8.1 Port Configuration Space Organization
Upstream Port (Port 0)
Cfg.
Offset
Size
Register
Mnemonic
Register Definition
0x000 Word P0_VID VID - Vendor Identification Register (0x000) on page 8-10
0x002 Word P0_DID DID - Device Identification Register (0x002) on page 8-10
0x004 Word P0_PCICMD PCICMD - PCI Command Register (0x004) on page 8-10
0x006 Word P0_PCISTS PCISTS - PCI Status Register (0x006) on page 8-11
0x008 Byte P0_RID RID - Revision Identification Register (0x008) on page 8-12
0x009 3 Bytes P0_CCODE CCODE - Class Code Register (0x009) on page 8-12
0x00C Byte P0_CLS CLS - Cache Line Size Register (0x00C) on page 8-13
0x00D Byte P0_PLTIMER PLTIMER - Primary Latency Timer (0x00D) on page 8-13
Table 8.2 Upstream Port 0 Configuration Space Registers (Part 1 of 5)
PCI
Configuration Space
(64 DWords)
Phy Layer Control
& Status Registers
Switch Control
& Status Registers
Power Budgeting
Enhanced Capability
PCIe Virtual Channel
Enhanced Capability
Device Serial Number
Enhanced Capability
Advanced Error Reporting
Enhanced Capability
0x000
0x040
0x0D0
0x0F0
Type 1
Configuration Header
PCI Express
Capability Structure
Extended Config Access
MSI
Capability Structure
0x0FF
0x100
0x000
0x180
0x200
0x280
0x400
0x4E0
0x500
0xFFF
0x0C0
PCI Power Management
Capability Structure
Reserved
0x560
SSID/SSVID
Reserved