Renesas 89HPES24T3G2ZBAL, User Manual

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IDT Link Operation
PES24T3G2 User Manual 3 - 9 February 22, 2012
Notes
• A transitional link down pseudo-state prior to L0. This pseudo-state is associated with the
LTSSM Detect, Polling, Configuration, Disabled, Loopback and Hot-Reset states.
Figure 3.2 PES24T3G2 ASPM Link Sate Transitions
Active State Power Management
The operation of Active State Power Management (ASPM) is orthogonal to power management. Once
enabled by the ASPM field in the PCI Express Link Control (PCIELCTL) register, ASPM link state transi-
tions are initiated by hardware without software involvement. The PES24T3G2 ASPM supports the required
L0s state as well as the optional L1 state. The L0s Entry Timer (L0ET) field in the PCI Power Management
Proprietary Control (PMPC) register controls the amount of time L0s entry conditions must be met before
the hardware transitions the link to the L0s state.
The upstream switch port has the following L0s entry conditions.
– The receive lanes of all of the switch downstream ports which are not in a low power state (i.e.,
D3) and whose link is not down are in the L0s state.
– The switch has no TLPs to transmit on the upstream port or there are no available flow control
credits to transmit a TLP.
– There are no DLLPs pending for transmission on the upstream port.
The downstream switch ports have the following L0s entry conditions.
– The receive lanes of the switch upstream port are in the L0s state.
– The switch has no TLPs to transmit on the downstream port or there are no available flow control
credits to transmit a TLP.
– There are no DLLPs pending for transmission on the downstream port.
The L1 Entry Timer (L1ET) field in the PCI Power Management Proprietary Control (PMPC) register
controls the amount of time L1 entry conditions must be met before the hardware transitions the link to the
L1 state. If these conditions are met and the link is in the L0 or L0s state, the hardware will request a transi-
tion to the L1 state from its link partner. Note that L1 entry requests are only made by the PES24T3G2
upstream port. If the link partner acknowledges the transition, the L1 state is entered. Otherwise, the L0s
state is entered. Note that the upstream switch port will only request entry into the L1 state when all of the
downstream ports which are not in a low power state (i.e., D3) and whose link is not down are in the L1
state.
L0
L0s L1
L2/L3 Ready
L3
Link Down
Fundamental Reset
Hot Reset
Etc.