Renesas 89HPES24T3G2ZBAL, User Manual

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IDT Configuration Registers
PES24T3G2 User Manual 8 - 41 February 22, 2012
Notes
AERUEM - AER Uncorrectable Error Mask (0x108)
14 COMPTO RO 0x0 Completion Time-out Status. A switch port does not initiate
non-posted requests on its own behalf. Therefore, this field is
hardwired to zero.
15 CABORT RO 0x0 Completer Abort Status. The PES24T3G2 never responds to a
non-posted request with a completer abort.
16 UECOMP RW1C 0x0
Sticky
Unexpected Completion Status. This bit is set when an unex-
pected completion is detected.
17 RCVOVR RW1C 0x0
Sticky
Receiver Overflow Status. This bit is set when a receiver over-
flow is detected.
18 MAL-
FORMED
RW1C 0x0
Sticky
Malformed TLP Status. This bit is set when a malformed TLP is
detected.
19 ECRC RW1C 0x0
Sticky
ECRC Status. This bit is set when an ECRC error is detected.
20 UR RW1C 0x0
Sticky
UR Status. This bit is set when an unsupported request is
detected.
21 ACSV RW1C 0x0
Sticky
ACS Violation Status. This bit is set when an ACS violation is
detected on the port. The PES24T3G2 does not support ACS
and therefore this bit is hardwired to 0x0.
30:22 Reserved RO 0x0 Reserved field.
31 DBE RW1C 0x0
Sticky
Double Bit Error Status. When the Double Bit Error AER Report-
ing Enable (DBEAEREN) bit is set in the Memory Error Control
(MECTL) register, this bit is set whenever a double bit error is
detected in any memory associated with the port.
When the DBEAEREN bit is cleared, this field is read-only zero.
Bit
Field
Field
Name
Type
Default
Value
Description
0 UDEF RW 0x0
Sticky
Undefined. This bit is no longer used in this version of the speci-
ficiation.
3:1 Reserved RO 0x0 Reserved field.
4 DLPERR RW 0x0
Sticky
Data Link Protocol Error Mask. When this bit is set, the corre-
sponding bit in the AERUES register is masked. When a bit is
masked in the AERUES register, the corresponding event is not
logged in the advanced capability structure, the First Error
Pointer field (FEPTR) in the AERCTL register is not updated, and
an error is not reported to the root complex.
This bit does not affect the state of the corresponding bit in the
AERUES register.
Bit
Field
Field
Name
Type
Default
Value
Description