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uREG User Manual
60
9.2.
PROJECT COMPILATION
Once edited using the graphic editor, the application project has to be compiled. The
compilation process is called from the toolbar in the editor by clicking the gear icon /
Narzędzia
→ Kompilacja projek
tu
/. Compilation includes a syntactic analysis of the project to check its
correctness and feasibility of relations between functors. The project whose syntax is correct
undergoes optimization. This process may or may not result in renaming identifiers (numbers)
relating to functors.
Compilation of a correct application project yields:
output HEX files with the application code for direct upload to the controller
(also *.APP packed file for external uPROG programmer),
output files with the settings code for direct upload to the controller,
application signature which unambiguously identifies the application,
output CFG files generated for
Monitor3
so that the program can be used to handle the
application,
compilation status providing information about the number of applied functors, settings,
reports, texts and the project signature.
The output files with the code and settings can be immediately reloaded to the controller (in
on-line mode if the device is interfaced with the editing computer), or later with the use of a
external uPROG programmer. For the immediate mode, the programmer is called by clicking
the integrated circuit upload icon /
Narzędzia → Programowanie uREG
/.
9.3.
STATIC DEBUGGER
Successfully completed compilation automatically activates the environment for a local or
remote
static debugger
of the project. Irrespectively of the access mode, the debugger is called
by the black triangle icon on the tool bar in the editor /
Debugger →
Krok elementarny
/.
The debugger is used to test and monitor complete operation of the finished application
project under conditions which will be identical for controller computers (except the real-time
conditions). Thus, application evaluation and tracking computation progress is performed in a
model electrical environment in virtual time, with steps simulating the lapse of elementary time
units or their conventionally agreed multiple values.
Emulation of an actual electrical environment in the switchboard uses a dedicated analogue
input window in the
LogCZIP
system. Rows in the window can be used to impose at any
moment the desired substitute values of currents, voltages, phase current phases relative to
voltages and zero sequence phase relative to voltage and frequency and its derivative. For
debugging double-section equipment (like ATS), voltages across busbars can be set
independently for each section.
Logic levels of substitute digital signals across device terminals and computer signals are
determined in windows presenting attributes of functors associated with relevant inputs. Such
Summary of Contents for uREG
Page 2: ...uREG User Manual 2 LogCZIP and uREG are registered trademarks of REGULUS Zygmunt Liszy ski...
Page 4: ...uREG User Manual 4...
Page 8: ...uREG User Manual 8 21 GUIDELINES FOR THE PURCHASER 107 22 WARRANTY 107...
Page 21: ...uREG User Manual 21 Drilling diagram for 10 slot enclosure installation...
Page 22: ...uREG User Manual 22 Drilling diagram for 14 slot enclosure installation...