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Realtek Confidential

RTL8762C Evaluation Board User Manual 

11 
Copyright 2018 Realtek Semiconductor Corporation. 
All Rights Reserved. 

specified IO port with jump wire. 

3)

 

Mark 18:

 RESET key and 5 independent keys, as shown in Figure 1-9. 

Note:    Debouncing capacitors and internal pull-up resistor make up a filter circuit to reduce ripples when 

buttons  are  pressed.  However,  it  can  also  affect  the  result  of  keyboard  array  scan.  Capacitors  are  not 

mounted on board by default. User can solder 0.1uF capacitor on pads when necessary. 

 

 

Figure 1-9    Schematic of Keys 

 

4)

 

Mark 11: 

FT232 chip. 

 

1.2.7 Pin Allocation on Motherboard of Evaluation Board   

When edges of daughter board are flush with the white lines and PCB antenna on daughter board is aligned with 

silkscreen mark on motherboard, the pins on daughter board are properly inserted; otherwise it is necessary to be 

cautious about improper connection.   

Pin allocation of motherboard is listed as follows:   

 

Table 1.1 IO Pin Allocation on Motherboard & Daughterboard 

RTL8762CJ 
RTL8752CJ 

RTL8762CJF 
RTL8752CJF 

RTL8762CK 

RTL8762CKF 

EVB   

FunctIOn 

EVB    socket 

P0_0 

P0_0 

P0_0 

P0_0 

 

M0_0 

P0_1 

P0_1 

P0_1 

P0_1 

LED0 

M0_1 

P0_2 

P0_2 

P0_2 

P0_2 

LED1 

M0_2 

P0_3 

P0_3 

P0_3 

P0_3 

LOG 

M0_3 

P0_4 

P0_4 

P0_4 

P0_4 

 

M0_4 

P0_5 

P0_5 

P0_5 

P0_5 

 

M0_5 

P0_6 

P0_6 

P0_6 

P0_6 

 

M0_6 

P0_7 

P0_7 

P0_7 

P0_7 

 

M0_7 

Summary of Contents for RTL8762C

Page 1: ...R e a l t e k C o n f i d e n t i a l RTL8762C Evaluation Board User Manual V1 0 2018 09 17...

Page 2: ...l RTL8762C Evaluation Board User Manual 2 Copyright 2018 Realtek Semiconductor Corporation All Rights Reserved Revision History Date Version Amendment Author 2018 07 07 V1 0 First Draft Jason_Xue 201...

Page 3: ...valuation Board Introduction 6 1 1 RTL8762C EVB introduction 6 1 2 Evaluation Board Interface 6 1 2 1 Interface Description 6 1 2 2 Main Chip Module 7 1 2 3 Power supply 8 1 2 4 IO Port 9 1 2 5 Interf...

Page 4: ...l t e k C o n f i d e n t i a l RTL8762C Evaluation Board User Manual 4 Copyright 2018 Realtek Semiconductor Corporation All Rights Reserved Contents of Tables Table 1 1 IO Pin Allocation on Motherboa...

Page 5: ...nterface Block Diagram 6 Figure 1 2 EVB Interface Distribution 7 Figure 1 3 Daughter Board 7 Figure 1 4 Power jumper 8 Figure 1 5 Connection of HCI UART Jumper 9 Figure 1 6 Connection of LOG 9 Figure...

Page 6: ...C Bluetooth Evaluation Board EVB Hardware 8762C EVB provides hardware environment for customer to develop their own application which includes 1 Voltage converter 2 6 axis motion sensor 3 4 LEDs and 6...

Page 7: ...IO GND RST SWO MICBIAS GND MIC_P MIC_N LOG UART Interface FT232_RX FT232_TX TX RX GND VCC GND GND GND KEY1 M4_1 KEY0 M4_0 RST KEY4 M2_5 KEY3 2_3 KEY2 2_4 LED3 M1_4 LED2 M1_3 LED1 M0_2 LED0 M0_1 LED3_...

Page 8: ...mark 10 4 Mark 13 14 AMS1117 3 3V output and AMS1117 2 5V output LDP chip that provide 5V to 3 3V and 5V to 2 5V voltage conversion circuit when EVB is powered by Li ion battery 5 Mark 9 Power G sens...

Page 9: ...C Test Jumper for external MIC 2 Mark 3 UART LOG Test Jumper a Connection of Jumper for HCI UART Test is shown in figure 1 5 Figure 1 5 Connection of HCI UART Jumper b Connection of Jumper for Log Tes...

Page 10: ...8 and J19 with jumper Figure 1 7 G sensor I2C connection 5 Mark 12 Micro USB interface It can be used as UART communication port when connected to PC 6 Mark 20 SWD interface used for SWD debug 1 2 6 O...

Page 11: ...ic of Keys 4 Mark 11 FT232 chip 1 2 7 Pin Allocation on Motherboard of Evaluation Board When edges of daughter board are flush with the white lines and PCB antenna on daughter board is aligned with si...

Page 12: ...32k_XO 32k_XO 32k_XO M_32k_XO P2_0 P2_0 P2_0 P2_0 M2_0 P2_1 P2_1 P2_1 P2_1 M2_1 P2_2 P2_2 P2_2 P2_2 ICM20618_INT CUT M2_2 P2_3 P2_3 P2_3 P2_3 KEY3 M2_3 P2_4 P2_4 P2_4 P2_4 KEY2 M2_4 P2_5 P2_5 P2_5 P2...

Page 13: ...re connected Connection of Jumper for Log Test is shown in Figure 2 1 Figure 2 1 LOG out connection 2 2 Current test The following current test points are reserved on evaluation board VDD_DEV is perip...

Page 14: ...avoid additional impacts from debug device 2 3 6 axis Motion Sensor 6 axis motion sensor is powered by VDD_DEV so J6 needs to be connected before using G sensor If I2C interface is applied J18 and J19...

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