Ameba-D User Manual
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Receive FIFO Full Interrupt (ssi_rxf_intr) – Set when the receive FIFO is equal to or above its threshold value plus 1 and requires service to
prevent an overflow. The threshold value, set through a software-programmable register, determines the level of receive FIFO entries at
which an interrupt is generated. This interrupt is cleared by hardware when data are read from the receive FIFO buffer, bringing it below
the threshold level.
Receive FIFO Overflow Interrupt (ssi_rxo_intr) – Set when the receive logic attempts to place data into the receive FIFO after it has been
completely filled. When set, newly received data are discarded. This interrupt remains set until you read the receive FIFO overflow
interrupt clear register (RXOICR).
Receive FIFO Underflow Interrupt (ssi_rxu_intr) – Set when an APB access attempts to read from the receive FIFO when it is empty. When
set, zeros are read back from the receive FIFO. This interrupt remains set until you read the receive FIFO underflow interrupt clear
register (RXUICR).
Multi-Master Contention Interrupt (ssi_mst_intr) – Present only when the SPI component is configured as a serial-master device. The
interrupt is set when another serial master on the serial bus selects the SPI master as a serial-slave device and is actively transferring
data. This informs the processor of possible contention on the serial bus. This interrupt remains set until you read the multi-master
interrupt clear register (MSTICR).
Combined Interrupt Request (ssi_intr) – OR'ed result of all the above interrupt requests after masking. To mask this interrupt signal, you
must mask all other SPI interrupt requests.
19.2.2
Transfer Modes
When transferring data on the serial bus, the SPI master can operate in transmit and receive mode, transmit only mode or receive only mode
as following. The transfer mode (TMOD) is set by writing to control register 0 (CTRLR0)
.
When transferring data on the serial bus, the SPI slave can only operate in transmit and receive mode. That is, TMOD field in CTRLR0 register is
invalid for SPI slave. If you do not want this device to respond with data, slave output can be disabled through SLV_OE bit in CTRLR0.
19.2.2.1
Transmit and Receive
When TMOD = 2‘b00, both transmit and receive logic are valid. Transmit data are popped from the transmit FIFO and sent through the txd line
to the target device, which replies with data on the rxd line. The receive data from the target device is moved from the receive shift register
into the receive FIFO at the end of each data frame.
19.2.2.2
Transmit Only
When TMOD = 2‘b01, the receive data are invalid and should not be stored in the receive FIFO. Transmit data are popped from the transmit
FIFO and sent through the txd line to the target device, which replies with data on the rxd line. At the end of the data frame, the receive shift
register does not load its newly received data into the receive FIFO. The data in the receive shift register is overwritten by the next transfer.
You should mask interrupts originating from the receive logic when this mode is entered.
19.2.2.3
Receive Only
When TMOD = 2‘b10, the transmit data are invalid. The txd output remains at a constant logic level during the transmission. The receive data
from the target device is moved from the receive shift register into the receive FIFO at the end of each data frame. You should mask interrupts
originating from the transmit logic when this mode is entered.
19.2.3
Operation Modes
The SPI can be configured in the fundamental modes of operation discussed in this section.
19.2.3.1
Serial-Master Mode
This mode enables serial communication with serial-slave peripheral devices. When configured as a serial-master device, the SPI initiates and
controls all serial transfers. Fig 19-8 shows an example of the SPI configured as a serial master with all other devices on the serial bus
configured as serial slaves.
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