RCA COSMAC Operator'S Manual Download

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Summary of Contents for COSMAC

Page 2: ...I I I I I I I I I I I I I I I I I I 1 nell LSI Systems Design 2nd Draft February 1975 Copyright 1974 1975 RCA Corporation I Operator s Manual Solid State Technology Center Somerville N J ...

Page 3: ...ule 37 5l2 Byte RAM Module 38 5l2 Byte PROM Module 39 I O Decoder Module 40 Bus Separator Module 41 Byte I O Module 42 Terminal Module 43 Card Nest and Signal Naming Conventions 44 Memory Module Addressing Details 47 RCA 1odules 47 Example A 47 Example B 48 Custom Memory Modules 49 Input Output Interfaces Sl Introduction 51 The Module Enable Philosophy and Two Level I O Sl Interfacing Signals 53 D...

Page 4: ...A TELETYPE HALF TO FULL DUPLEX CONVERSION INSTRUCTIONS 66 B UTZ ASSEMBLY LISTING 69 C TTY MODEM MICROKIT SWITCHBOX 77 D BACKPLANE WIRING SCHEDULE 79 E MODULE LOGIC AND CIRCUIT DIAGRAMS 80 97 F COSMAC INSTRUCTION SUMMARy 98 G ASCII HEX TABLE 99 ...

Page 5: ...18 19 20 21 22 Block Diagram Address Latch Module Block Diagram 5l2 Byte RAM Module Block Diagram 5l2 Byte PROM Module Block Diagram I O Decoder Module Block Diagram Bus Separator Module Block Diagram Byte I O Module Block Diagram Terminal Module Custom 4K RAM Functional Diagram DMA Input Example DMA Output Example Sample Program Interface Sample Character Waveform Model 33 Teletype Terminal Strip...

Page 6: ...BER TITLE PAGE 1 VT2 Register Initialization 29 2 VT2 Calling Sequences 30 3 Card Nest Hodule Assingments 44 APPENDIX D Backplane Wiring Schedule 79 APPENDIX F COSMAC Instruction Summary 96 APPENDIX G ASCII Hex Table 97 ...

Page 7: ...ternal devices These interfaces may be custom designed by the user or for common peripheral devices they may be available from RCA as standard optional modules The COSMAC Software Development Package or CSDP provides a fundamental set of programming aids to facilitate the coding and debugging of application programs The Microkit includes means to transfer program material from the CSDP sys tem to ...

Page 8: ...mmable read only memory containing the prewritten UTILITY PROGRAM henceforth called UT2 The crystal controlled system clock and the control pinel interface reside on a card Two cards are used to provide appropriate data routing within the system An additional module is used for memory address latching Finally three cards provide a fundamental I O input out put interface including I O device select...

Page 9: ...plex operation Two I O typewriter cables are supplied with the Microkit one for a Teletype the other for an Execuport They are labeled appropriately To connect the terminal select the proper cable and plug its receptacle labeled PI into the appropriate connector mounted directly on the accessible end of the Terminal board in card position 20 see Figure 1 below The two connectors on the Terminal bo...

Page 10: ...hat the system is functioning properly Depressing RESET causes the RUN light to go off and the CPU to idle Following this by a depression of RUN UTILITY will cause the RUN indicator to light The system is now running with UT2 the utility program in control This program begins by reading the first keyboard input character to define for itself the terminal character rate and whether or not it should...

Page 11: ...y entering MltlA CR The system will print the characters just entered after the memory location addressed 0001 in this case and will return the prompt characxer again The time out program can then be run either by entering PI CR or by depressing RESET followed by RUN PROGRAM In either case the RUN indicator should go off after an elapsed time of approximately 2 6 seconds This establishes that the ...

Page 12: ...eader already has a detailed familiarity with the COS C CPU For completeness the Appendix includes a COSMAC INSTRUCTION SUMMARY and a table relating ASCII characters to their hexadecimal representations MEMORY ORGANIZATION To write elementary programs the user must be aware of which portions of the total memory address space in the Microkit are available for his use We cover only the basic princip...

Page 13: ...S O the most significant address bit and one Sl2 byte PROM bank position 4 enabled when AlS l The two RAM banks are pre wired to give a composite lK RAM whose bank number is zero The PROM in position 4 is also wired to give it a bank number of zero Thus the RAM will respond to addresses XOOO to X3FF where X is 0 to 7 most signif icant bit 0 while the PROM will respond to addresses YOOO to YlFF whe...

Page 14: ... parameters necessary to run the terminal thus allowing a single program to operate with wide vari ations in clock speed or terminal speed When UT2 is ready to accept a command it types out a prompt character To interrogate memory the user types a command such as M2FS 3 terminating with the CR carriage return UT2 will respond by printing out the contents of memory beginning at location 02FS printi...

Page 15: ... while data is being entered any non hex character except the comma and semicolon as will be discussed is ignored This permits arbitrary LF s spaces for readability nulls generated by the utility or by a time share system to give the carriage time to return etc As a second optional form of data entry a string of input data can be terminated by a semicolon and a CR The utility program then expects ...

Page 16: ...summary the user has the following options after the prompt character He may type M address 6 count M non hex address 6 data optional or where data may have imbedded non hex digits between each hex pair or P address CR UTZ ignores initial characters until it detects or Then inputs which are not compatible with the above for mats will result in an error message P always begins with RO as program co...

Page 17: ...er of hex dIgIts IS required Before each hex pair ar bitrary garbage is allowed except for a CR comma or semicolon CR terminates the command unless immediately preceded by comma or generally preceded by a semicolon i In case of comma CR the user should insert his own LF and uTz continues to accept data This is a form of line continuation ii In case of a semicolon all following characters are ignor...

Page 18: ...rection of an error without retyping the whole command For example a mistaken 234 can be corrected by continuing 2340235 0235 A bad command can be aborted by typing any illegal character except following M or M or between input hex digit data pairs in these cases type any hex digit and then for example a period 8 To punch reloadable paper tape type M addr 6 count then a header of nulls control shi...

Page 19: ... and also in D The memory location pointed at by R2 as well as registers RE RF X and DF will have been changed in value not preserved over the call The READ routine normally uses R3 as its program counter so it is most convenient to branch to READ via a D3 instruction R3 0 will also return with a modified value All other register contents will not be changed by the call Since the READ routine uses...

Page 20: ...t rate and which use arguments passed via registers are discussed in the section cited above Given the ability to execute simple typewriter I O functions the user is now able to code elementary test programs to further exercise the Microkit As a simple example consider the routine described in the COS C Microprocessor Manual p 40 to read two bytes compare them and output the larger of the two The ...

Page 21: ... TYPE entry 9C saved in R7 l R6 now points to 0026 the immediate TYPE byte RS now initialized to 0016 is ready to be the new local program counter Switch P from 0 to 5 Call READ Input character to D and to RF l Save first char in immediate byte location READ second character to D and to RF l X now points to first character D M R X D Subtract first from second Exit to print the first character if i...

Page 22: ...ust be restored to the value 6 see instruction at location lD since UTZ changes X As an example of loading and running a program via the keyboard we present below an example of a Microkit session using the elementary program just discussed above In what follows text enclosed in square brackets represents UT2 typeout text enclosed in round brackets represents user input and other text represents ru...

Page 23: ...ont d The reader is invited to code an elementary hexadecimal test program to verify his knOWledge of the COSMAC instruction set and the elementary I O typewriter inter face described above and to further exercise the Microkit 17 ...

Page 24: ...run the program during which time program bugs are isolated and removed via further editing and reassembly of the source file Eventually the object code is ready for loading and running in the real hardware the Microkit for further testing It is this part of the process that we are concerned with here We have already discussed the use of the M UT2 feature to load the Microkit RAM from the keyboard...

Page 25: ...haring service to assemble and debug his program and that he is presently connected so that his terminal is operating in the norm time sharing mode Execuport in LINE mode or switchbox in TTY MODEM position with CSDP LOAD switch off Assume further that he is speaking to the CSDP control pro gram and that an object code file previously assembled by CSDP is ready for transmission The steps required t...

Page 26: ...hat UT2 must be properly initialized just prior to the final CR This M form is more compact and relocatable 2 Y File Name Start RAM Loc End RAM Loc where the same comments above apply to File Name For example Y TTY 20 lSO will result in the transmission of the semicolon con tinuation form of the M file more readable since each line begins with an address value If the Microkit has been initialized ...

Page 27: ...R the user calls for an assembly of this file with listIng and diagnostics printed to the terminal The output he receives is indicated in Figure 4 below The COS C CODE listed there the same as that in the hex program generated earlier has now been loaded into the CSDP simulator s memory After generating the listing CSDP again returns with the DBG prompt Refer to the COSr C Software Manual for deta...

Page 28: ... I L_f PCE F P2 POINTS AI FPEE L OC ERO CHI F O PHI P2 PLO F e PHI FC PHI l iPC L 1 1 PHI 10 LD I P tPTF PLO IOPTF L JI HPPTF PH I I FTR L I I I APe 1 FL O rlpCi LD I r 1 I LOOP F LO FC LOCI L F F OCF1 lt 1 COUHTEP PEt I r EP PC I ITCH F POCPI i1 1 COUI HErS ift I n PF OCipm 1 LOOP EC I n HEFT LOOP CL O lOPTI PL O 1 PO I 1 iT TO F E1 j SEP 10 CALL PEAD FIPST CHAR TO srp APe SAUE IT CL O lOPTF FL O...

Page 29: ... 0 CL O I CiF Tr 31 FL O 10 2 EF ICJ 3 E AF C LJ lI iCi OUF CE L I I F F IE __ L Ciiil F l iF LF FEfD Et iTF i i F F TI IC I L Cn E F J I LF l F 5 i EJ ITF j ICi F IJT F E fr j T FIE F F CIC F f 111 C CIIJt ITEI F C F _ CfiL L I l iC F POCF i 1 COUITfCF i n c M r II 1 C j iTE F Tef It 1I tC It ll T FIE lTE t I OF TP P7 HOL Y IFF TF FiI F W F 1 lrILUC CIF C 1 Ff7 0CF I TI iF T FfT L CC 1 8 Iw a Ili...

Page 30: ...transmit command For this case 30 16 bytes will be transmi ted While the object file is being transmitted to the Microkit it is also printed on the typewriter For the example given the CSDP command X TTY 0 30 will result in MOOOO FF90B2A2BSB6F88lB3F83EA7F89CB7F826A6F816A5DS87A3D35687A3D3E6F73B 239F5697A3D3FF30l6FFFFFFFFFFFFFFFF DBG printed on the terminal during the loading of RAM On the other han...

Page 31: ...s clearly the Microkit must be appropriately interfaced to a card reader to effect a program load If the object file can be transmitted from the batch system to a remote terminal a process similar to that discussed above CSDP load can be used to effect a program load Further details can be found in the COSMAC BATCH ASSEMBLER CBA Manual As a final note on loading one should not overlook the special...

Page 32: ...o be available in one specific register called AUX This constant occupies the upper half of AUX AUX l and has two parts One bit the least significant specifies echo or not 0 denotes echo 1 de notes no echo For Teletypes connected in Full Duplex the bit should be O For Execuports the bit should be 0 if Full Duplex operation is employed and 1 for Half Duplex The remainder of AUX l constitutes a timi...

Page 33: ...for the DELAY routine The user of TYPE and READ has the option of calling TIMALC or setting up AUX l and the pointer to the DELAY routine himself TIMALC READ and TYPE use SUB R3 as their ram counter and return to the caller with SEPS They can e called directly from a program in state RS or may be called through the standard linkage procedure DELAY uses RC as its program counter AUX l RE I is reser...

Page 34: ...S and TYPE6 types from M R6 and increments R6 TYPESD is an entry which provides a I S bit delay be fore going to TYPES The purpose of this is to let an immediately preceding READ process completely before TYPEing TYPE2 is an entry which results in CHAR I being typed out in hex form as two hex digits Each 4 bit half is con verted to a ASCII hex digit O 9 A F and separately typed out Notice that the...

Page 35: ...s Program counter for VTZ which calls the routines above Program counter for the DELAY routine Points to DELAYI in memory Assembled into by READAH input hex digits AUX l holds time constant and echo bit AUX O used by all READ TYPE routines and hy TIMALC CHAR I holds input output ASCII character CHAR O used by all READ TYPE routines and by TIMALC REGISTER REGISTER NAME NUMBER PTER RO CL RI ST R2 SU...

Page 36: ...CHAR l Output hex digit pair in CHAR 1 Read input char and set up control byte in AUX l Initialize RC to point to DELAYI Delay as function of M R3 see text Then R3 l NOTES ON ABOVE 1 All routines except DELAY use R3 as program counter exit with SEPS and alter registers X D DF AUX CHAR and location M R2 2 DELAY routine uses RC as program counter exits with SEP3 after incrementing R3 and alters regi...

Page 37: ...ard covering the range from 8200 821F then UT2 will detect this fact and store registers RO RF there although RO Rl and R4 1 are clobbered in the process The user can later use the command M8200 20 to see their contents before UT2 took over If he wants later to continue operation he should take into account the fact that UT2 has clobbered registers RO through RS and RC through RF 31 ...

Page 38: ...PU data bus into two unidirectional busses memory data IN and OUT Similarly the BUS SEPARATOR on the I O side performs the same function for the in dividual unidirectional I O data busses IN and OUT The BYTE I O module is a generalized 8 bit parallel data I O interface for optional user devices The TERMINAL I O module is specifically designed for a bit serial T eletype like I O device Simplified f...

Page 39: ...r II uC l l DATA II TO DEV BYTE TT f AL I USER I DATA 1 0 tI FACE I A DE VICES I FROM DEV V 1 L BUS SEPAc RATDR STATE CODE I O N L IN E S IDECOOER TPB COSMAC CPU MWR H ADDRS MEM WRITE 1A 7 1 MEM AODRS L ADDRS TPA r i 1 L kE I I I USER I RAM M yl ROM MEMORY DATA 0 1 t v I TO MEM FR T E I I L J _ FIG 5 MICROKIT BLOCK DIAGRAM 33 ...

Page 40: ...ignals interrupt DMA input r quest DMA output request and four external flags It transmits wo timing pulses or syncs and an encoded CPU state When executing an input output instruction 1 6 it transmits the four bit N field of the instruction See the COS C Microprocessor Manual for details of i s functIonal operation CLOCK CLEAR LOAD 3 N 4 MEMORY ADDRESS STATE CODE 2J 8 CPU SYNC 2 MEMORY COSMAC _ D...

Page 41: ... starting execution at 8001 if previously reset Also on this card is a free running Pierce crystal oscillator with a crystal tuned to 1 95 MHz This internal clock can be gated off by an external clock inhibit as well as by CLEAR If a user wishes to run at some other frequency there is provision for an external clock Depression of RUN UTILITY or AIS true deselects the low half of memory Otherwise t...

Page 42: ...K PERMIT CLOCK BUS DMA au RUN 8 START FLI P FLOPS CPU STAT RUN l UTIUTY 0 RUNJ ROGRAM 0 O t l ESET o o EXTERNAL CL nt CLEAR LOAD LOAQLSWITCH 0 o I LA1CHJ RUN UTILITY A 15 I LOW DESELECT HIGH DESEL EC RUN LIGHT Fig 7 Block Diagram Clock and Control Module 36 ...

Page 43: ... the memory address bus carries the lower order byte A7 AO A special timing signal which is true only when all sixteen memory address bits are stable may be required by certain types of memory for exampl the COS MaS 512 byte RAM This signal is derived using two CPU syncs and the clock SYNC CPUMEMORY ADDRESS 8 8 BIT LATCH 8 ADDRESS TO 8 MEMORY LOW ORDER BYTE A7 AO Fig a Block Diagram Address Latch ...

Page 44: ...ry low This card is selected for access when address bits All AID and A9 match the constant bank number signals hard wired on appropriate connector pins in this card s position provided that the overriding DESELECT signal is not asserted DATA IN ADDRESS AO TO A8 9 MEMORY WRITE 8 DATA OU 8 SELECT WIRED BANK SELECTION 3 MEMORY ADDRESS STABLE MEMORY DESELECT Fig 9 Block Diagram S12 Byte RAM Module 38...

Page 45: ...match the constant bank number signals hard wired on appropriate connector pins in this card s position provided that the overriding DESELECT signal is not asserted Additional PROM modules are available from RCA with PROM chips inserted in the sockets They may be removed from the card for user programming ADDRESS AO A8_ It K DATA OUT 9 2 8 PROM SELECT WIRED BAN K SELECTION 3 ADDRESS A9 AlI 3 PROM ...

Page 46: ... 1 defines an I O Read I O bus memory N3 0 defines an I O Write memory I O bus The sixteen I O Sync signals have approxima ely the durition of a full machine cycle The eight I O Strobe signals occur for I O Write only and are timed to indicate that the data is ready i e that the memory access is complete STATE CODE 2 DECODER CPU STATES _ 4 DECODER N3 u 1 6 N 3 I I O SYNC 8 NO N2 3 1 6 o N3 0 _ DEC...

Page 47: ...by an appropriate logic condition In the Microkit two such modules are used one to interface to the memory system the other to interface to the I O system Wiring of the two connector pins carrying the function select signals distinguishes the memory bus separator from the I O bus separator FUNCTION SELECT 2 MEMORY CONTROL 2 ENABLE TRANS MISSION CAIE 8 DATA OUT 8 DATA BUS 8 DATA IN 8 Fig 12 Block D...

Page 48: ...or external use or gating an input byte to RAM Both ports are available for user devices I O STROB OUTPUT DEVICE SELECT DATA OUT 8 GATE 8 BYTE BIT OUT 8 LATCH USER DEVICE ATA TRANS B TE _D_ I_N_ NISS ION Y_ 8 GATE IN 8 I O SYNC INPUT DEVICE SELECT USER DEVICE Fig 13 Block Diagram Byte I O Module 42 ...

Page 49: ...ther standard 20 rnA current loop or TTL levels The serial ASCII characters which are output to the terminal are formed by strobing Data Bus bit 0 into a latch under program control Data is transmitted to memory by driving External Flag 4 The Utility Program samples EF4 at appropriate intervals and builds an ASCII character one bit at a time I O STROBE DATA BIT 0 c TTL DATA 20MA DATA TO TTY EXTERN...

Page 50: ...the back of the Microkit which interconnects the pins of 21 of the 34 available connectors Eleven of the 21 wired connectors are occupied by the basic Microkit card set The card positions viewed from the back and numbered left to right are CONNECTOR POSITION NUMBER WIRED FOR MODULE IDENTIFYING CODE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 34 Memory Bus Memory Bus Memory Bus PROM Me...

Page 51: ...onnected on the backplane but which have meaning defined by the plugged in module A blank entry defines an unused pin Unbracketed names indicate signals interconnected by printed wiring Bracketed names indicate wire wrap inter connected signals Names bracketed by asterisks indicate signals not interconnected on the backplane defined only by the plugged in module Ground GND is wirewrapped as well a...

Page 52: ...side of the system is on the left On the rear of the front panel is a pocket with a small PLUG IN LOCATIONS drawing which maps the supplied modules into backplane slots Unoccupied locations have space on this drawing for the user to note modules that are added to the system Some precaution should be exercised in removing and inserting modules into the Hicrokit nest The module cards are keyed so th...

Page 53: ...9 la and 11 to perform bank selection Memory deselect MDS P pin X may be a function of the remaining high order address bits 12 15 In the microkit the slot occupied by memory module GMC 4 has pin X connected to PMDS P which is derived from the Clock and Control module GGB Similarly the RAM slots 11 and 12 use RMDS P These two signals have been alluded to earlier in connection with high and low mem...

Page 54: ...in that space to the 8200 83FF address range Obtain an additional GMC module and program the PROM chips Remove GMA from slot 12 Insert the new GMC in slot 12 This completes the first step Choose an unused Memory Bus slot Suppose you select 5 Add wires to slot 5 as follows pin 1 to GND pin X to PMDS P pin X of slot 4 Insert G in slot 5 48 ...

Page 55: ...ps at 9V Power beyond this must be provided by the user The COSMAC CPU ar hitecture does not require memory cycles to be contiguous i e to immediately follow each other in time See Appendix D of the COSMAC 1ICROPROCESSOR MANUAL for memory timing Thus the cycle times of added memory modules are not critical Clearly they must be less than the machine cycle of approximately four microseconds What are...

Page 56: ...expense of generality A second 4K RAM identical to the above could not be added to the system as it stands A more general sD1ution requires central block selection logic decoding of address bits 12 15 Then it would be possible to design larger capacity memory modules which can be moved in address space by backplane wiring changes in a manner similar to that discussed for the S12 byte banks supplie...

Page 57: ...t alone the module will be perm anently enabled This input can also be driven by a signal possibly derived from a manual switch so that the module can be selectivel enabled Notice that a memory module also includes suc a feature in which case the overall ENABLE is derived either directly from an address bit or from some decoded combination of several address bits as was just discussed under Memory...

Page 58: ...at matter if only one I O device exists the 1 SCO code itself can be useo to activate it Now consider a more complex system containing more possible I O data paths than can be handled in the one level arrangement All I O modules in the COSHAC system are designed to easily accommodate a two level I O ystem Each has an ENABLE signal input which can be derived from the output of a decoder whose input...

Page 59: ...lines TDO N to TD7 N which may be connected to user devices Data here is valid at TPB of the I O execution cycle When an OUT N instruction machine code 6N O N 7 is executed the I O decoder sends out a decoded signaT SI N P at TPB of the I O execution cycle This SI P signal may be used directly to strobe a latch which will hold the data appearing at TDO N to TD7 N There are eight input data lines I...

Page 60: ...ne e TrA This is equivalent to the TPA N notation in this manual Similarly MWR there is equivalent to MWR P here Timing for DMA requests and INTERRUPTS are shown in the COSMAC Microprocessor Manual As explained there any DMA request or INTERRUPT will cause the COSMAC CPU to make a transition out of the IDLE state repetitive Sl s and cause program execution to commence The COSMAC CPU is sensitive t...

Page 61: ...shown can be eliminated Note that this arrangement will work as shown even if a DMA Output port is also im plemented because the Bus Separator on the I O side prevents the IND bus from connecting to the two way system data Bus even though an S2 Pl in response to an Output request enables the Input gates shown above Expansion of DMA Input to serve more devices will require aduitional transmission g...

Page 62: ...rom the device electronics is needed only if another DMA interface is present in the system INTERRUPT A straightforward Interrupt implementation is shown in Fig 17 p 58 of the Microprocessor Manual To trans late to the Microkit interface replace the two state code inputs to the NOR by Systems which require multiple Interrupt conditions can be handled in a variety of ways If the Interrupts are sync...

Page 63: ...s 60 to 64 of the COSHAC Microprocessor Manual describe the implementation of a pro grammed sequencer hased on the COSMAC micro processor The description there outlines the required external logic and the associated control program The program uses an I O Read instruction to read data from switches and an I O Write instruction to send data to an output register External flag 1 is coupled to the en...

Page 64: ... new plug in contains the following F P ENTER CD4011 L CD4013 EFI N I S Q C I R C 0 0 S VOO VOO 8 TOGGLE SWITCHES 1 VOO IN 0 P TO IN 7 P PI 3 TO PI IO 0 8 SLOTI9 r Fig 18 Sample Program Interface Since slot 19 is wired to IOF P and SI06 P two bytes in the Sample Program listing on page 64 Microprocessor Manual must be changed as follows Address DODD change 68 to 6F Address ODIC change 60 to 66 Now...

Page 65: ...alse before it looked for EFI true All of the switch debounce hardware can now be eliminated The program becomes longer by two bytes as follows Old EFI test address OOOA 3COA New EFI test address OOOA 330A3COC The new code causes the program to loop at address OOOA until EFI becomes false then it loops at OOOC until it becomes true again The switch logic can be replaced by ENTER Ir e CJ lTj Recall...

Page 66: ...i i i i i iOO AI 0 0 0 i 0 vL V1 en J i BIT SERIAL OPTIONAL ON SOME DEVICES ASCII CHARACTER c 41 Fig 19 SAMPLE CHARACTER WAVEFORM Each character is framed by a START bit and one or two STOP bits On input this signal is tied to EF4 N which is sensed by a program at the midpoints of each of the bits Software assembles the resultant ASCII character On output the character is transmitted one bit at a ...

Page 67: ...e frequency at which this occurs will be a function of the terminal character rate External Flags EFI to EF4 The external flags offer a simple yet powerful input interface to the COS C CPU We have already discussed means by which a program may test an external flag and branch conditionally on its value The use of a flag as a bit serial data input port was also described Note that with the Terminal...

Page 68: ...O side The module logic shown in the Appendix includes signal names valid for slot 18 Microkit Dynamic Characteristics COS C CPU timing and dynamic specifications are to be foun4 in the COSMAC Microprocessor Manual and in the COS 4AC Data Sheet COSMAC based products should be designed to those specs The Microklt lnterface is designed to facilitate functional experiments The interface supply voltag...

Page 69: ... the RUN indicator to light If it doesn t you may have a failure in the Clock and Control module no CLOCK signal a burned out indicator or a failed CPU If CLOCK and d c power VDD and CPU PWR are present at the CPU moJule then TPA and TPB should also be present Hitting LF or CR after RUN UTILITY should cause VT2 to calibrate itseTr and type out a prompting asterisk If the Microkit does not respond ...

Page 70: ...wer supply from C C connector Line cord and socket at back of cage POWER SUPPLY Mounted to slotted rear of nest uses space of 6 connectors 5 volts at 2 5 amps 5 regulation 9 volts at 0 4 amps 12 volts at 01 amps Short circuit and thermal protection One fuse for AC on front panel no overvoltage protection These connectors have unusual sized pins 015 x 04l Use for example OK Machine electric powered...

Page 71: ... each for RESET and RUN UTILITY one for RUN PROGRAM one for LO D grounded chassis Terminal card to customer furnsihed TTY 4 wire cable 9 ft terminated with MOLEX connectors for TTY Cable from console card to Execuport or terminal using T2 L interface Amphenol male connector through 9 ft of 4 wire cable to 25 pin Cinch plug 65 ...

Page 72: ... AP P END ICE S ...

Page 73: ...ed for 60 rnA operation the following modifications can be made 1 Move the VIOLET wire from pin 8 to pin 9 2 Move the BLUE wire connected to the current source resistor a flat green resistor with 4 tabs located to the right of the keyboard from the 7S0n tab to the l4S0n tab Figure 21 below is also included for the reader s inform ation It illustrates all of the interface circuitry between Microkit...

Page 74: ...DU I TAPE PUNCH L 7EL ET IPE 00 cL 3 3 SEND TERMINAL ST 1 P RECEI liE CONNECTION FoR J 20 1vfA LooP I Z 5 1 5 f7 8 9 r 0 I l Z 2 0 2 I fl 0 J j e 0 l 10 Q f I 10 WHTj BRW vIoLeT BLU YEl TERMINAL STRIP cONNECTIONS Fig 20 Model 33 Teletype Terminal Strip Location and Connections 67 ...

Page 75: ...PUT NOTE 2 NOTE 3 U4B 0 00 I SI9 7 TDO CLEAR I OUTPUT DECODER 7 NOTE I 8 l AfM TTV TTYIB 22 PRINTER TTYI p _ S I 9V 3 7 I T T L I 9V TTL INTERFACE 0 OUTPUT NOTE 2 NOTE I CABLE 3902531 501 NOTE 2 CABLE 3902531 502 NOTE 3 REF DWG 3901809 FOR DETAILS Fig 21 Detailed Circuits for CPU Terminal Interface Full Duplex Io le ...

Page 76: ...Fnr CR 17 SEl lICOI orJ Arlf1 COIV1A In TilE UAun RATE OF UT2 IS DlOErn lJPorJ TilE 19 TERI llr AL OEltlG USEO A cn Ol I F IS ErJTERED 20 AT TIlE OEGII IJIIIG TO SPECIFY TilE APPHOPIATE 21 OELAY UEnlEE UITS lJT2 III LL ECIIO 22 CHAnACTER IF A eR IS CIIOQS 1 A i TilE 23 TII HUG CHARACTER ECIIOlf lG IIILL 1I0T TAI 21 PLACE Ir A LF IS IIJpUT fl S TlIE T11 1 tlG 2 CHARACTER 2G UT2 AT Jr ITI fl T I or ...

Page 77: ...TillER 8G GO STATE SUI3 37 88 8 90 START A OCTyrE jD IJ l 0 91 GO STATE Slm IIOD CR CAmU AGE nF Tlmrr 92 5T2 GO STATE SUI3 OA Lr L HIE FEEn 3 GO STATE GU13 2A X AS PRorlPT CIIAft6 r n H 4 IG IOHE ST 1 ASL 0 AS L 1 rHE PARr TO I JPLJT II 95 O GITS CLEAR ASL 9G A 0 READAIl SUB 0 97 GO STATE sun IrlPUT C JrY AflD 98 XOR 21 IS IT qg nz DOLLAR 100 XOR liDS IS IT I CTC T IITI1 Of 101 S ITCII O flll Sl v...

Page 78: ... 130 H02 GO STATE sun 131 nDF R02 rH AO IfJ r rorlD AI G 132 rllJl tilER or lYTES 133 XOR 00 IF XT r K FOn cn 134 UUZ SYtlEnR 135 A O TYPE50 SUrl O TyrE 13G L1IJE GO STATE SUr1 f OA I F 137 PTER l CIIAn 1 PREr o Hr L11lE IIEf OlrJG 138 A 0 TYPE2 SlJlJ O 13g GO STATE sun TYPE 2 111 IJ IG1ri 140 PTER O CIlAR l 11 1 A O TYPE2 SlJn 142 GO STATE SUB TYPE OTIlEn 2 1 3 GO STATE sun 2rJ SP1 r r 11 11 5 Tl...

Page 79: ... IERR 1 O TYr SD lm GEnERAL m SlJLT r r 198 S ITI CTI C mnOR 199 200 201 202 20 2 4 TlH FOLLO JItHl OOE p IlIlI 1 205 20G OOI LAR GO STATE SlJn llnn Slm O HEl nA 1 207 xon SIIOlJl fl BE I 208 m lZ SYrJERR 209 D1 GO STATE sun 210 nor rn ASSO 1nLE IIEX STI lrIG IIITO NJI 211 XOR fOn FI nST r mtlIIC rlUST nr cn 212 ur z SYIJERR 2lJ I SL l RO 1 ASI O Ro n r T UP I IEn PC 214 A O TYPESO SUD O 215 GO ST...

Page 80: ...O REXIT 3GO 361 TYPE ROUT I1 lE TYPES 1 BYTE FRon R5 RG 362 OR CIIAr 1 OR rr PE 1 rrrTE A i 2 IIEX DI ITS 3G3 FRon CI1A 1 FOLLO lS A L1W FEED B SIX 1IJLLS 364 USES 2 AUXILLARY REGS AUX AI JD CllAR PLlJS 3G5 RAt1 LOC ATIOi4 ST r XITS REi lW TO r pi 1 3 rrr 3GG Ra RSI EXITS TO R5 3G7 1ErJ r rHERED AT TYPE5D PAUSES TO ALLOI 1 4 3G3 i ARL I r R READ TO COlolPLETE 3G9 370 A JX O IIOLD3 OUTPUT CI1AR AT ...

Page 81: ... Cl 408 P EI3IT 3T 1109 nITs Gr STi TE or uw 11 07 nEL r IE BIT T 1i 410 DEC CIIAR OECRD1E1H TALLY 1111 ST I IJ O Alm n01 ST 412 OUT 7 fJUTPIJT D iT i nITH 413 DEC 3T 414 CIIM 001 1m II 0F 1 15 3Z q 11AR AUX O AIJ LO TO STRnCli lELA 415 AUX 0 2 0r 30 I9ST SIIIH TO nF n nIT 417 GO TO PI EI3IT 418 419 IXCIl r Cli R f FI3 C lI R 0 SET UP r 0H LIen ell in 420 I3tlF TEXIT I3UT r XIT IF r 0 r 1 Jn 1121 ...

Page 82: ...trip position 3 4 and 6 7 as shown in Figure 20 Appendix A Others may connect through a MOLEX jack to 32 the same receptacle needed for the Microkit In either case isolate the two current loops one to the keyboard SEND and one to the printer RECEIVE and bring out as four wires The TTY cable supplied with the Microkit see Note 1 Fig 21 can be cut to produce two 4 wire cables The three way routing o...

Page 83: ...YBOARD J 1 4 SEND TO MODEM RECEIVE 6 POLE DOUBLE THROW SWITCHES SHOWN IN TTY MO OEM POSITrON OTHER POSrTlO IS TTY KIT PRINTER DPOT SWITCH RIGHT TO ACTIVATE CSOP LOAD 5 4 MCA 255 OR EQUIVALENT KEYBD TO J2 OF TTY Fig 22 TTY MODEM KIT Switchbox 78 ...

Page 84: ... DESEPARATOR DWG 3901810 ADDRESS LATCH DWG 3901808 CLOCK CONTROL DWG 3901804 BUS SEPARATOR DWG 3901805 I O DECODER DWG 3901806 BYTE I O DWG 3901807 TERMINAL INTERFACE DWG 3901809 NMOS 1K X 8 RAM DWG 3901801 PROM UTILITIES 512B DWG 3901803 CPU DWG 3901822 POWER SUPPLY BOARD ASSY DWG 3900537 1 2 4 5 6 7 8 9 10 11 12 13 GZAOI GMA01 EXTENDER 14 15 CMOS 512B RAM 16 17 ...

Page 85: ... N PI D tbT02 N 1 3 1 PI I 8U5 2 N INDZ N 1 10 TD3 N 1 1 4 oJ PI R BUS 3 N IND3 N PI F T04 N PJ I r 1 5 SUS 4 N IN04 N PI H TDS N p oJ PI T SUS 5 N INDS N 1 J TDG N 1 1 7 oJ PI lJ SUS N IND N PI K 00 I 0 TD7 N 1 1 18 J P V SlJ 5 7 N IND7 N PI L 0 GBA01 BUS DESEPARATOR I 01 lITIITIIJ 1 ...

Page 86: ...D1 o r 1 Co CLfc 01 T I t 00 3 D L GTY 1 3 2 1 2 2 1 2 1 1 1 1 1 DWG NO 198622 63 198653 51 198622 54 198636 51 198631 51 8412778 10 8510655 114 198775 1 99206 207 993025 461 8542728 413 3554095 1 3410354 19 PARTS LIST DESCRIPTION ICP CD4069BE HEX INV ICP CD4049A HEX INV ICP CD4001A GO 2 NOR ICP CD4013A 0 FLIP FLOP ICP CD4042A GO LATCH CAPACITOR 15uf 20 20V DIODE ZENER 12V 400W DIODE RESISTOR 100 ...

Page 87: ...ell3 12V VDD 1c5 I G4 13 CR1 CR2 CtpUl R VOO I ctV PI A 00 N GFA01 CON T bIIIIIJj 3 ...

Page 88: ...CURRENT DRAIN P C RUNL T N fi I oiL lad T I II pi a I pill PI M R lDS P Il JI CtEAR P P 7 DI1AouT H 10 Il 0 9V 6 8MA 5V 14 MA 00 VI PART S LIST ON PAGE 4A GGB01 GGB02 CLOCK CONTROL bIIIIIIJ 4 ...

Page 89: ... CD 4007A DUAL COMP PRo U7A 2 2 198653 51 ICP CD 4049A HEX INV U3A U4A 1 1 198655 52 ICP CD 4066A QD SW U1B 9 9 198775 1 DIODE CR1 CR6 CR9 CAll 1 1 3900975 1 CRYSTAL 1 95 MHZ Yl 2 198861 1 LED CR7 CR8 1 1 99206 163 RESISTOR 1 5KJ l 5 1 4 W R22 2 2 99206 135 RESISTOR 100 J1 5 1 4 W R14 R20 1 1 99206 140 RESISTOR 160J1 5 1 4 W R16 6 6 99206 183 RESISTOR 10K 5 1 4 W R2 4 6 8 10 12 9 9 99206 191 RESIS...

Page 90: ...i 00 Z 2 Z oJ V J tn I 2 2 l 1I1 OIl l l II G II l II II II l 11 II III 0 0 r UNUS O eL e I NT5 t PI V PI l P I 21 PI tt o _ PARTS LIST oWG NO I Of SCRIPTION I REFERENCf 198622 54 ICP Co4001A Qo 2 NOR U5B 198622 51 ICP C04011 A Qo 2 NAND U4B 5 I 198653 52 ICP Co4050A HEX BUFF U2A U4A U5A U7A U6B 2 I 198655 52 I ICP CD 4066A QD SW I U3A LJ6A 8 9206 183 RESISTOR 10K 5 1 4W R1 THRU R8 1 8412778 10 CA...

Page 91: ...A PI I Il All A d t5 1 I PNl 13 SCI N PI j IZ SOoN f PI Z I I I TPfj N 9V 5V 8 MA 00 0 PARTS LIST OTY OWG NO Of SCRIPTION REFERENCE 3 198653 51 ICP CD4049A HEX INV U2A U3A U2B 1 198653 52 ICP CD4050A HEX BUFF U7B 3 198635 51 ICP CD402BA BCD DEC U4A U6A U6B 2 198622 51 ICP CD4011A 00 2 NAND U3B U4B 1 198622 53 ICP CD4012A DUAL 4 NAND U7A 1 8412778 10 CAPACITOR 15uf _L 20 20V C1 1 99206 191 RESISTOR...

Page 92: ...O II It II II II S III l il II a Il l II Il l IQ PARTS LIST QTY DWG NO DESCRIPTION REFERENCE 3 198653 51 ICP CD4049A HEX INV U2A U4A U7A 2 198655 52 ICP CD4066A 00 SW U1A U3A 1 198622 51 ICP CD4011A QD 2 NAND USB 2 198631 61 ICP CD4042A QD LATCH U6A U8A 1 3541950 3 RESISTOR MODULE 22K R2B 1 8412778 10 CAPACITOR 15uf 20 20W C1 ___ I 0 J rnLJ J GGE01 tm J a m Jl BYTE I O bTISSSIJ LEM J e J C 0 7 ...

Page 93: ... SW U6B tl al 1 198636 61 ICP CD4013A D FLIP FLOP U4B c a 1 198023 1 TRANSISTOR N P N Ql ogO GHA01 1 1980242 TRANSISTOR P N P Q2 g 2 1987751 DIODE CR1 CR2 c I 2 8412778 10 CAPACITOR 15uf t20 20V Cl C3 g JI TERMINAL INTERFACE c eXI I 1 3554095 1 CAPACITOR 0 1 uf 80 C2 0I 1 3 82283 149 RESISTOR 390fl i 5 1 2W R2 R6 Rl1 1 99206 159 RESISTOR 1K t5 1 4W R4 lITIII 3 99206 169 RESISTOR 2 7K t5 1 4W R3 R7...

Page 94: ... W v J l z 1 1 alL z_ r an z lI all all z J all z In 1L z It G DlL z r J DIl z cO t DlL 00 1 0 PARTS LIST DWG NO L DESCRIPTION FERENCE 198622 52 ICP C04023A TR3 NAND U4A 1 I 198638 51 ICP CD4030A aD EX OR U3A 8 198640 1 ICP NMOS 1K STATIC RAM U1B THRU U8B 2 198653 52 ICP CD4050A HEX BUFFER U5A U6A 1 I 8412778 10 CAPACITOR 15ul 120 20V C3 2 35540951 CAPACITOR 0 1ul 180 Cl C2 20 50V 2 I 99206 191 I ...

Page 95: ...O P E PI F PI Pf PI K PH O HI N Z N l N OI 4 N D S N N 1N f t rltr oJ _ l I r PARTS LIST D QTY DWG NO DESCRIPTION REFERENCE 1 198622 52 ICP CD4023A TR3 NAND U68 1 198638 51 ICP CD4030A QD EX OR U6A 1 198653 51 ICP CD4049A HEX INV U58 1 198653 52 ICP CD4050A HEX 8UFF U5A 9 198775 1 DIODE CRl THRU CR9 2 8412778 10 CAPACITOR 15vf 20 20V Cl C2 3 99206 191 RESISTOR 22K 5 1 4W Rl R2 R3 2 3900538 0 ICP 2...

Page 96: ... I 1 I I j r I I I I tl tl t jl f I 1 8 MA OF 12V 11 I 1 n t u 2 5 a 1 I OS I I 78 COSM C cpv 1 S 41 1 JIB s I R To N M Tllll e IILe N lie l 7 2 11 COSM C CPLI 1 0 ADII TO eU5 17 APPllol eTL 10 I AOPlll eT I AOOR2 cT P 1 1 1 0 OOR ICTL p I lle I ToIlS Ill 22 v ess OTMl jEW e CI I O OTY 1 1 2 1 2 1 DWG NO 198641 1 198641 2 8412778 10 3541950 3 82283135 198775 1 PARTS LIST D SCRIPTION ICP CPU 1 ICP ...

Page 97: ...2 1 1 1 1 1 1 1 3900923 84 8412178 5 3900924 227 3900923 99 198356 2 198783 2 3900021 1 993022 206 82283 135 993022 211 82283 159 82283 164 82283 146 82283 123 82283 152 198175 1 198658 2 198658 3 CAPACITOR 5300ul 15 10 25V CAPACITOR 10ul 20V CAPACITOR 500ul 16V CAPACITOR 1800ul 35V DIODE DIODE SPADE TERMINAL RESISTOR 39il 110 2W RESISTOR 100il 5 1 2W RESISTOR 621 1 10 2W RESISTOR 1000il 15 1I2W R...

Page 98: ...MER AND BOARD ASSEMBLY WITH IIEAT SINKS ARE HELD TOGETIIER BY A MOUNTING BRACKET TO MAKE AN INTEGRAL UNIT PERFORJ IANCE CIIARACTERISTICS ARE SPECIFIED FOP THE ASSHIBLY AS A WHOLE 1IIE DC OUTPUTS ARE NON ADJUSTABLE AND ARE CURRENT LIMITED TIllS ASSHIBLY DOES NOT PROVIDE OYER VOLTAGE PROTECTION 2 0 ELECTRICAL PERFORJ NCE 2 1 INPUT VOLTAGE a 115 VAC NOMINAL b 104 YAC MINIMUM c 127 YAC MAXIMUM 2 2 INP...

Page 99: ...ARK THE APPROPRIATE PLUG IN GROUP At O ASSEMBLY REVISION LEVEL IN THE LOCATION SHOWN USING ITE 14 3 MARK THE FACTORY DATE CODE IN THE LOCATION SHO US ING ITEM 14 4 h A illQ u D D 50c O l I J R I XW i Ql U 9 JR JH S AS S lL PRINTED BOARD lO 10 3903823 1 Iv USABLE REVLEVE I ASSy 800KLET 1 1 I I I THIS DWG DWG REV LEVELl 10 1 I I OSR r 5 I C c t o SEf DETAIL A 4 PLACES o 26 RIVET OVER FAR SIDE to fB ...

Page 100: ...r YEO L yEE 1EF ym Y EJ rEI r EL Y EM YEN YEP XER r ET r yEU YEV YEW Y EX PI U PI V PI W PI X PI l J PI P PI R PI S PI T P A PI B PI C PI 0 PI E PI F P 1 H PI J PI K PI L PI Wl J I I J I Z JI 3 J 4 J 1 5 JI f J 1 7 J 1 B J I 9 JI IO J I II J 1 2 J 1 3 JI I l JI 15 J I I J 17 J 1 16 1 I J I LO 11 2 1 Y JI 21 J l P I PI I P 2 PI 3 PI 4 PI 5 PI PI 7 PI B PI 9 0 I U1 OU rs EXTENDER Gi ADl Lh d JtCA P ...

Page 101: ...i U2C I I JU3C U 13U4Ci U5C I 1U6C I u7cl I uecl 1 UYCI i i I Ai P 11r 12 I IlL 1C 1 ul lc i2 Ie j 2 LJ 21 U 12 1 2 I 11 i I U L 11j 7 I I I I I LJ 1 J I I PHv1 I I I V j V J i 1 I _ 0 I 1m N pr2 N D13 N DI4 N its N T l j n 1 1 to J 8 P u l 1 PH2 lP1 13 1 4 1 14 tC 1 15 l P1 1 vl tn I II II Pl 10 __ l VDTI D00 N D J1 N 2 N 3 N 1 04 N W D0 N Del N IJ _ 1 PI C Pl D PH PH P1 H Pl Jj l K PH I II A l p...

Page 102: ...F U3A U4A 1 198622 ICP CD402SA TR 3 NOR UIB 16 198664 ICP CD 4061A 256Xl RAM U2B THRU U9B U2C THRU U9C 1 8412778 CAPACITOR IS UF 20 20V Cl 3 99206 RESISTOR 22K S 1 4 1 Rl R2 R3 ULM J rueD AI LJ I U98 luge I e 0 s c J rn b ula I RD O I U28 I I U2e I 8 IU3e I nr4 L I U4e Ir1 I I fV5B I U5e t LJ I U6 B It r U 6 fUlB IlIle I GMA CONT n 17 ...

Page 103: ... IF EF4 SKIP BRANCH IF 0 NOT ZERO BRANCH IF NO OF B ANCH IF NO EFl BRANC H IF NU EF2 BRANCH IF NO EF3 BRANCH IF NO EF4 LOAD ADvANCE STORE OuTPUT INPUT RETURN DISABLE SAVE GET LC GET HI PUT LO PUT HI SET P SET LOAD BY X OR AND EXCLUSIVE OR Auo uaTRACT 0 SrlIFT RIGHT SLJdTRACT MEMORY LOAD IMMEDIATE OR IMMEDIATE AND IMMEDIATE EXCLUSIVE OR IMMEDIATE ADD IMMEDIATE SUBTRACT 0 IMMEDIATE SUBTRACT MEM IMME...

Page 104: ...6 F V f v UJ I 7 BEL ETB 7 G W g W I Z t 8 BS CAN 8 H X h x u LI 9 HT EM 9 Y i y z A LF SUB I J Z j z Vl I B VT ESC K k Vl t UJ C FF FS J L 1 D CR GS M m E SO RS N t n F SI US 0 0 0 DEl NOTES 1 PARITY BIT IN MOST SIGNIFICANT HEX DIGIT NOT INCLUDED 2 CHARACTERS IN COLUMNS o AND 1 AS WELL AS SP AND DEL ARE NON PRINTING 3 MODEL 33 TELETYPE PRINTS CODES IN COLUMNS 6 AND 7 AS IF THEY WERE COLUMN 4 AND ...

Page 105: ...PUT 2 BUS M R X N A B IN INPUT BUS R X N tl C IN INPUT 4 BUS R X N D IN INPUT 5 B E IN I INPUT I BUS M R X N E F IN INPUT 7 BUS M R X NO F COSMAC REGISTER SUI t1ARY HEXIDEC IMAL CODE D a BITS DATA REGISTER l Tf lI DF 1 BIT DATA FLAG ALU ARRY R 116 BITS 1 OF 16 SCRATCHPAD REGISTERS P 1 BITS DES If NATFS WH H R IS PR IGM CTR IX BITS DESIGNATES R X N 4 BITS LOtI RDFR INSTRUCTION DIGIT I BITS HTI H RI...

Page 106: ...3 ralr IUhJPT c l UE OMA r 1 CL A R SO F ETC H C YC L OMA DNA LOAD 5 MA 10l DNA INr OMA COS MAC STATE TRANSITION DIAGRAM STI Rr uP NORMAL rN TRUc TION S QvCNC E ExrERN L CLEAR C LO ON IOMA ourl t hr INHR n TC H ntoH M ooo p INTERNAL 51 SI SI SI S I 51 52 so SI SO S I SO 1 STArE tooe HH HH I fH HtJ HH I iH LH HH HI HH HL HH H E lC C UTlON oF 1 0 BtT TRANSFER pgTRvc nON j S2 SO SI L H HH HH so SI Ht...

Page 107: ...2 1 IS S 1 it Jb S 10 17 37 f II 18 38 3 12 I 19 1 1 3 10 0 2 8 lif 2 3 CosMAC S iST M Hlre f FAC it X y TNTER C HI ONN c TION oNL l tJOT AVAILA 3L WITH S tJGoL C Hl c o t1AC NOTE Vc c Svoc F Of TTL IN rcR FAc c oM PATA I1 1 rY 100 2 Vc O P NOltJC ON R UIAED C L TIMe NOT ro E l r 15 Voe Vee 1 2 5 Vo BuSIf 2 2 7 BUr1 Bus 3 2 BU 2 3uH Ii 6USI Bon s MAO 23 A ATE TP8 HAl 7 2 2 H Al 8 2 1 f ENABLE NA3 ...

Page 108: ... r I _ ol _ _ W lffIlkIVALIO 13r f oFF o WI IiIl2IVAllD6 Tt J Ll 1 _ I I I 1 MCMORY t C c ESS riME Nor 3 P J JI 1 027i u u u o s T I I I I I I I f I I MAC H I IE C l C L TINt I 104 1ST I I I I I I I I AO 11 W 1m A O wa AO I I I I Z7 iI I M READ M WR NOTE 2 t1fMORY OVTPO r TPA rp8 M Al E SS PERIOD AOORess MAO 7 NOTE 1 NOTE 2 NOTE 3 NOTE MINIMUM T DETERMINED BY COSMAC V DD MAX VDD lSVDC NO MAXIMUM T...

Page 109: ...1 llii J Iml INPUT I3tn rz2 tNPIJT lyrE 2 IVTI IIZ I I I _________ 11 1 r1 _ I I I I I o I I T O F BUS MWR HATE C ODE AStNC DNA IN ASYNC OM our 7 l T ll 7 T I llatfE I Til I AIUYTE1 1 1 I TAT OO eu5 2 rPB u u ItJrERRUPT TIMIN TPA TP8 u LJ u L Jr L l u nnrRRUPT OFF SrATE c O 11 1 11 2 71 11 11 S3 l jj j Z 0 I k MAX Rr PONS TIME 1 z LE5 ...

Page 110: ...ogrammer should maintain a register utilization list and initialize eadh register before use Program interrupt routines can cause very hard to find bugs For example if the interrupt routine uses an F6 instruction DF mayor may not be changed during the interrupt routine If DF is not saved and restored by the interrupt routine programs will run properly most of the time Once in a great while however...

Page 111: ...ments a variety of support programs is available These include assemblers simulators and interactive debuggers These programs can be used with standard commercial time sharing or batch services and facilitate COSMAC program development ...

Page 112: ...7 P DIO N A7 P OIO N A7 P DIO N BUSO N DIO N A7 P BUSO N SCO N N lZ A6 P DIl N M P DIl N A6 P DIl N BUSl N DIl N M P BUSl N SCl N P 13 AS P UIZ N AS P OIZ N AS P DIZ II BUSZ N DIZ N AS P BUSZ N SCZ N R 14 A4 P DI3 N A4 P DI3 N M P DI3 N BUS3 N DI3 N A4 P BUS3 N S IS A3 P DI4 N A3 P DI4 N A3 P UI4 N BUS4 N DI4 N A3 P BUS4 N N3 N T 16 AZ P DIS N AZ P DI SoN AZ P DIS N BUSS N DIS N AZ P BliSS II NZ N...

Page 113: ... N IN6 P IN06 N IN06 N O IN N CLEAR N I l7 P SIf lO P IN07 N VOO IN07 N IN7 P IN07 N SI l7 P IN07 N CLEAR N CLEAR P EXTCLK P IfIIB P SCO N BUSO N lTOO N BO P lTOO N CLEAR P lTOO N 6TOO N I l9 P SCI N BUSI N fIITOl N ItDI P lTOl N lTOI N lTOI N SCZ N IfIIA P SC2 N BUS2 N 9JTOZ N B2 Pft lT02 N lT02 N lTOZ N XCLR N I lB P 51 I6 P BUS3 N lT03 N B3 P lT03 N 0T03 N lT03 N I lC P N3 N BlJS4 N fIIT04 N B4...

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