Raymond Jimenez DSP56k User Manual Download Page 1

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The DSP56k MP3 Player User’s Manual

Raymond Jimenez

June 8, 2011

Summary of Contents for DSP56k

Page 1: ...The DSP56k MP3 Player User s Manual Raymond Jimenez June 8 2011...

Page 2: ...ii...

Page 3: ...internals Notable features of this system include An emphasis on data bandwidth all processes that could benefit from DMA interrupts do so We can successfully play 320kBps MP3 files and raw WAV files...

Page 4: ...iv INTRODUCTION...

Page 5: ...e Display 9 2 2 Playing Songs 10 2 3 Volume Control 10 3 Advanced Features 11 3 1 Adding Songs 11 3 2 Playing non MP3 files 12 III Developer Documentation 13 4 System Overview 15 4 1 Introduction to A...

Page 6: ...1 Prototyping Board CPU 59 7 2 CPLD 61 7 3 MP3 Decoder Daughterboard 63 7 4 DAC Analog Out 65 7 5 Display Keypad 67 7 6 IDE Interface 69 7 7 DRAM Address Multiplexing 71 8 Annotated Code 73 8 1 CPLD C...

Page 7: ...CONTENTS vii 9 Release Notes Errata 241 9 1 Known Bugs 241 9 2 Known Limitations 242...

Page 8: ...viii CONTENTS...

Page 9: ...1 1 Main MP3 Playback Unit 4 1 2 MP3 Player s Keypad 5 1 3 LCD Display Unit 6 2 1 Typical Appearance of the LCD Display 9 4 1 Overall System Block Diagram 16 4 2 Main Board Components 17 4 3 DRAM Bloc...

Page 10: ...x LIST OF FIGURES...

Page 11: ...List of Tables 4 1 DAC Startup Mode 18 xi...

Page 12: ...xii LIST OF TABLES...

Page 13: ...Part I Quick Start Guide 1...

Page 14: ......

Page 15: ...y In order to play MP3s from the hard drive connect the main playback unit to the keypad display and hard drive and power up the hard drive using its own power supply Then plug in the main unit s powe...

Page 16: ...4 CHAPTER 1 QUICK START GUIDE Figure 1 1 Main MP3 Playback Unit...

Page 17: ...5 Figure 1 2 MP3 Player s Keypad...

Page 18: ...6 CHAPTER 1 QUICK START GUIDE Figure 1 3 LCD Display Unit...

Page 19: ...Part II User Guide 7...

Page 20: ......

Page 21: ...nd song Fig 2 1 1 Song title The currently playing song or folder name is displayed here Please note that if the song folder name is too long only the first n characters will display consistently the...

Page 22: ...y line level standard 2 2 Playing Songs In order to play songs simply navigate to the song desired and press play If there is an entry with a preceeding it is likely a folder To navigate into a folder...

Page 23: ...ere H is the drive letter of the newly attached drive Move the music file that you would like to add to the drive and then go back to the command prompt and type mksong MP3 File mp3 Song Title Song Ar...

Page 24: ...P3 files In order to add a non MP3 file follow the steps above and the song should appear normally available for play When adding the non MP3 files keep in mind If a file s bitrate is too high it may...

Page 25: ...Part III Developer Documentation 13...

Page 26: ......

Page 27: ...nd controlling the DAC MP3 decoder e g volume play stop The select nature of the system makes this relatively easy to implement We first look at a detailed example of an MP3 s data flow 4 2 MP3 data f...

Page 28: ...es the file and outputs the audio data via I2 S protocol to the DAC The DAC s outputs then go through a finishing analog stage then out to the headphone jack Please note that the CPU is format agnosti...

Page 29: ...4 3 MP3 DECODER 17 Figure 4 2 Main Board Components...

Page 30: ...processor control 4 4 1 Power The DAC and analog stage have separate voltage regulators in order to pro vide cleaner power The 5V rail is regulated by two separate low dropout linear regulators to 3 3...

Page 31: ...fact that we do not have an external interrupt controller and that our main application is not multithreaded However we do achieve decent transfer rates due to the fact that our code is single threade...

Page 32: ...20 CHAPTER 4 SYSTEM OVERVIEW Figure 4 3 DRAM Block Diagram...

Page 33: ...4 6 DRAM 21 8 deassert CAS RAS both latch OE s Due to the fact that we use TA the DRAM timings are specified not in the CPU but by the CPLD For more details please see the CPLD DRAM code on page 73...

Page 34: ...22 CHAPTER 4 SYSTEM OVERVIEW...

Page 35: ...Chapter 5 Memory Map and Registers 23...

Page 36: ...x 8 bits forced by Mode 9 0xD00000 0xA0FFFF 0xA0FFFF SRAM 64k 0xA00000 SRAM 64k 0xA00000 0x2FFFFF 0x2FFFFF DRAM 1M 0x200000 DRAM 1M 0x200000 0x103fff 0x103fff IDE controller 8k 0x102000 IDE controller...

Page 37: ...0 0x100431 general periph AA1 0xD00609 ROM AA2 0x200431 DRAM AA3 0xA00831 SRAM BCR DSP is bus master 1 wait state on SRAM except for area 0 2 wait states and 1 7 wait states to compensate for SRAM and...

Page 38: ...26 CHAPTER 5 MEMORY MAP AND REGISTERS...

Page 39: ...have worked on in order to make sure our circuit works However these timing diagrams may not reflect reality due to parasitic effects that we haven t taken into account the wait states presented here...

Page 40: ...10ns 0ps 10ns 20ns 30ns 40ns 50ns 60ns 70ns 80ns clk O 80MHz address O 18 0 CS O RD O data O 15 0 data sampled O 15 0 Tcquart tRC tACSDel tACSDel Tcquart tRDW tRDNA tAA t OE tACS tOH tRDtoVAL tOHZ...

Page 41: ...s tRC ENG NOM Ws 1 NOM Tc 4000 address valid width 21ns 21ns t RDA ENG NOM tRDDE N OM tRDNA NOM tRD W NOM tRC from deassertion of RD to address valid 2 875ns 2 875ns 2 875ns t RDDE ENG 0 NOM Tc 3 NOM...

Page 42: ...4 SRAM Read SRAM SYMBOL DEFINITION DESCRIPTION MIN MAX NOM t AA Address Access Time 15ns tACS Chip Select Access Time 15ns tOE Output Enable Low to Output Valid 7ns tOH Output Hold from Address Change...

Page 43: ...40ns 20ns 0ps 20ns 40ns 60ns clk O 80MHz address O 15 0 CS O WR O data out O 15 0 Tcquart tRC tACSDel tACSDel tAS tWP tWR tDS tDH tWC t AW tCW tWP tDW...

Page 44: ...5ns 33 5ns Ws wait states 2 t ACSDel Address to chip select delay 0ps 0 tAS ENG 3 NOM Tc 4 2000 Address and AA valid to WR assertion 7 375ns 7 375ns t WR ENG 1 NOM Tc 4 2 000 WR deassertion to address...

Page 45: ...ite SRAM SYMBOL DEFINITION DESCRIPTION MIN MAX NOM t WC write cycle time 15ns tAW address valid to end of write 10ns tCW chip select low to end of 10ns tWP write pulse width 10ns t DW data valid to en...

Page 46: ...34 CHAPTER 6 TIMING 6 1 2 ROM...

Page 47: ...ps 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns 200ns220ns clk O 80MHz address O 18 0 CS O RD O data O 15 0 data sampled O 15 0 Tcquart tRC tACSDel tACSDel Tcquart tRDW tRDNA tCE tOE t ACC tOH tR...

Page 48: ...s 0ns t RC ENG NOM Ws 3 address valid width 146ns 146ns tRDA ENG NOM tRDD E NOM tRDNA NOM tRDW NO M tRC from deassertion of RD to address 14 125ns 14 125ns 14 125ns tRDDE ENG 1 NOM Tc 3 NOM Tc 4 4000...

Page 49: ...OM Read ROM SYMBOL DEFINITION DESCRIPTION MIN MAX NOM t ACC Address to Output Delay 120ns tCE Chip Select Access Time 120ns tOE Output Enable Low to Output Valid 50ns t OH Output Hold from Address Cha...

Page 50: ...38 CHAPTER 6 TIMING 6 1 3 DRAM...

Page 51: ...5 0 BRD O RAS O CAS O DRAM addr O 15 0 DRAM data O 15 0 DB 0 24 to CPU O 15 0 t RC tBDELAY tBDELAY tRDNA tRDW tBDELAY tBDELAY tCPLD DELAY tCPLD DELAY t BDELAY t CPLD ROW t RAH t ASR tRAS t CPLD RC INT...

Page 52: ...time between row 12 5ns Inter cycles CPU cycles between row and column addr 1 tCPLD CAS time from BRD assertion to CAS assertion CPLD synth 50ns CAS cycles CPU cycles to lag between BRD and CAS 4 tRD...

Page 53: ...N DESCRIPTION MIN MAX NOM t RAS RAS pulse width 70ns 10000ns tASR row address setup 0 tOFF data hold time 0ns tRAH row address hold 10ns t RAC RAS to data 70ns tCAS CAS pulse width 15ns 10000ns tAA co...

Page 54: ...BWR O RAS O CAS O DRAM addr O 15 0 D 0 23 O 15 0 DB 0 23 O 15 0 tWC tBDELAY tBDELAY t WRNA tWRW t BDELAY t BDELAY tCPLD DELAY tCPLD DELAY t BDELAY tCPLD ROW t RAH tASR tRAS t CPLD RC INTER tCPLD COLUM...

Page 55: ...CPLD RC INTER intervening time between row 12 5ns Inter cycles CPU cycles between row and column addr 1 tCPLD CAS time from BRD assertion to CAS assertion CPLD synth 50ns CAS cycles CPU cycles to lag...

Page 56: ...SYMBOL DEFINITION DESCRIPTION MIN MAX NOM t RAS RAS pulse width 50ns 10000ns tASR row address setup 0 tRAH row address hold 9ns tCAS CAS pulse width 8ns 10000ns t DS data setup 0ps tCAH column address...

Page 57: ...6 1 TIMING TARGETS 45 6 1 4 IDE...

Page 58: ...40ns 20ns 0ps 20ns 40ns 60ns 80ns 100ns 120ns 140ns 160ns 180ns A 0 2 O 15 0 AB 0 2 O 15 0 AAR0 O CS O RD O BRD O DIOR O tdelay tAD AAR t AAR CS tRC t1 0 tAAR CS tAD AAR tRDANV tRDW t delay t delay t...

Page 59: ...lay address buffer 4 5ns tAD AAR delay between address bus and AAR 0 0 t AAR CS delay between AAR and CS CPLD 15ns Tc CPU clock period 12 5ns Ws Wait states 9 t RDANV RD deassertion to address not val...

Page 60: ...Page 3 IDE timings SYMBOL DEFINITION DESCRIPTION MIN MAX NOM t 1 address valid to DIOR DIOW setup 25ns t0 cycle time 120ns t 1 0 minimum address assertion 145ns...

Page 61: ...S 49 6 1 5 DAC via SCI Please note that these timings are not actually in effect we decided to in terface via ESSI instead which is adjustable enough that we were able to directly tune DSP parametrs t...

Page 62: ...1us 800ns 600ns 400ns 200ns 0ps 200ns 400ns 600ns 800ns 1us 1 2us 1 4us 1 6us sclk O 1MHz txd O 15 0 tsiclk tsetup tSIIDS thold tSIIDS...

Page 63: ...CPU output SYMBOL DEFINITION DESCRIPTION MIN MAX NOM Tc internal clock 12 5ns 12 5ns thold hold time after rising edge 243 75ns tscc serial clock period 1us 1us tsetup setup time before falling edge 2...

Page 64: ...Page 3 decoder requirements SYMBOL DEFINITION DESCRIPTION MIN MAX NOM t siclk clock requirement 960ns tSIIDS data setup time 50ns tSIIDH data hold time 50ns...

Page 65: ...these timings are not actually in effect we decided to in terface via ESSI instead which is adjustable enough that we were able to directly tune DSP parametrs to fit MP3 decoder timing Additionally S...

Page 66: ...1us 800ns 600ns 400ns 200ns 0ps 200ns 400ns 600ns 800ns 1us 1 2us 1 4us 1 6us sclk O 1MHz txd O 15 0 tsiclk tsetup tSIIDS thold tSIIDS...

Page 67: ...CPU output SYMBOL DEFINITION DESCRIPTION MIN MAX NOM Tc internal clock 12 5ns 12 5ns thold hold time after rising edge 243 75ns tscc serial clock period 1us 1us tsetup setup time before falling edge 2...

Page 68: ...Page 3 decoder requirements SYMBOL DEFINITION DESCRIPTION MIN MAX NOM t siclk clock requirement 960ns tSIIDS data setup time 50ns tSIIDH data hold time 50ns...

Page 69: ...ign uses latches and the CPLD to interface between the LCD and the rest of the system 6 2 Timing Simulation CPLD For insurance that our CPLD design would work we simulated several sce narios In the fo...

Page 70: ...0 0 ns 200 0 ns 200 0 ns 400 0 ns 400 0 ns 600 0 ns 600 0 ns 800 0 ns 800 0 ns 1 000 0 ns 1 000 0 ns 1 200 0 ns 1 200 0 ns 1 400 0 ns 1 400 0 ns CLOCK AA0 DISPCS AA2 BWR BRD DWE DREFRESH BG DRAS DCAS...

Page 71: ...Chapter 7 Schematics 7 1 Prototyping Board CPU 59...

Page 72: ...2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A...

Page 73: ...7 2 CPLD 61 7 2 CPLD...

Page 74: ...27 I O11 28 I O12 29 I O13 30 I O14 31 I O15 32 I O16 37 I O17 38 I O18 39 I O19 40 I O20 41 I O21 42 I O22 43 I O23 44 I O24 3 I O25 4 I O26 5 I O27 6 I O28 7 I O29 8 I O30 9 I O31 10 IN1 SDO 24 IN2...

Page 75: ...7 3 MP3 DECODER DAUGHTERBOARD 63 7 3 MP3 Decoder Daughterboard...

Page 76: ...23 CVDD2 24 I2S MCLK GPIO5 25 RX 26 TX 27 SCLK 28 SI 29 SO 30 CVDD3 31 XTEST 32 GPIO 0 33 GPIO 1 34 GND 35 I2S LROUT GPIO 4 36 AGND0 37 AVDD0 38 RIGHT 39 AGND1 40 AGND2 41 GBUF 42 AVDD1 43 RCAP 44 AVD...

Page 77: ...7 4 DAC ANALOG OUT 65 7 4 DAC Analog Out...

Page 78: ...Res1 68 R7 Res1 Vcc5 Vcc475 GND 100nF C22 Cap 100nF C24 Cap 100pF C20 Cap Pol1 IN 1 GND 2 EN 3 BYPASS 4 OUT 5 U3 TPS97333 Vcc5 VccAud33 GND 100nF C23 Cap 100nF C25 Cap 100pF C21 Cap Pol1 Vcc475 GND 1...

Page 79: ...7 5 DISPLAY KEYPAD 67 7 5 Display Keypad...

Page 80: ...11 DB2 5 DB3 10 DB4 6 DB5 9 DB6 7 DB7 8 RS 13 R W 3 E 12 VSS 1 VCC 14 VEE 2 1 LCD DIP MTC S40200XRGHS w o backlight GND Vcc5 0 1u Cap 1u Cap GND OC 1 C 11 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 1Q 1...

Page 81: ...7 6 IDE INTERFACE 69 7 6 IDE Interface...

Page 82: ...DD1 15 DD14 16 DD0 17 DD15 18 Ground 19 keypin 20 DMARQ 21 Ground 22 DIOW 23 Ground 24 DIOR 25 Ground 26 IORDY 27 CSEL 28 DMACK 29 Ground 30 INTRQ 31 obsolete 32 DA1 33 PDIAG CBLID 34 DA0 35 DA2 36 CS...

Page 83: ...7 7 DRAM ADDRESS MULTIPLEXING 71 7 7 DRAM Address Multiplexing...

Page 84: ...PRD1 67 PRD2 68 PRD3 69 PRD4 70 SIMM1 DRAM4MX32 OC 1 C 11 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D 8 8D 9 1Q 19 2Q 18 3Q 17 4Q 16 5Q 15 6Q 14 7Q 13 8Q 12 U2 74HCT573 OC 1 C 11 1D 2 2D 3 3D 4 4D 5 5D 6 6D 7 7D...

Page 85: ...s we decided to use a hierarchial approach to CPLD design because it made pin routing much easier reset abl contains the reset logic which OR s together the JTAG reset and man ual reset functions allo...

Page 86: ...reset manreset pin 15 I O pin 0 jtagreset pin 42 I O pin 21 resetcpu pin 17 I O pin 2 s1 FUNCTIONAL_BLOCK chipsel Clock pin 11 clock input Y0 AA0 pin 18 I O pin 3 AA2 pin 19 I O pin 4 AB14 pin 20 I O...

Page 87: ...r1 Reset s1 Clock Clock s1 AA0 AA0 s1 AA2 AA2 s1 AB14 AB14 s1 AB13 AB13 s1 AB12 AB12 s1 BRD BRD s1 BWR BWR DispCS s1 DispCS KeypadCS s1 KeypadCS IDERD s1 IDERD IDEWR s1 IDEWR DataDir s1 DataDir DispE...

Page 88: ...3 datasheet DRAM takes up a lot of stuff d1 CS AA2 d1 Reset r1 Reset d1 BWR BWR d1 BRD BRD d1 RefreshEn DRefresh d1 Clock Clock DRowL d1 RowLatch DColL d1 ColLatch DRAS d1 RAS DCAS d1 CAS DLatchEn d1...

Page 89: ...ect actual logic This version inputs two active low reset signals on pin 16 and 17 and outputs a combined active low reset signal on pin 15 MODULE reset TITLE Reset Logic two active low reset inputs J...

Page 90: ...ut a chip select signal for the display I O 7 pin 22 keypad encoder chip I O 8 pin 23 and IDE controller I O 9 pin 24 MODULE chipsel TITLE Chip Select Logic chip select block input from CPU AA0 pin AA...

Page 91: ...aDir as active low to match the buffer wiring direction requirement when DataDir is asserted the data bus goes from peripherals to CPU DataDir BRD AA0 AA2 we take care of general peripheral chip selec...

Page 92: ...EnablePulse into 1 2 in order to minimize the clock bits we need seems to make everything run faster state_diagram DispState State EnableSetup DispEnable 0 IF DispCS BWR THEN EnableSetup ELSE IF Enabl...

Page 93: ...y 27 2011 Modified to use as template February 12 2011 changed from template to interrupt logic MODULE interrupt TITLE Interrupt Logic IRQ0 IRQ1 IRQ2 IRQ3 pin ISTYPE com InIRQ0 InIRQ1 InIRQ2 InIRQ3 pi...

Page 94: ...interrpt abl 2011 02 13 END interrupt 2...

Page 95: ...ruary 27 2011 changed from interrupt logic to dram logic MODULE dram TITLE DRAM Logic QS2 QS0 node ISTYPE reg setup time counter QH2 QH0 node ISTYPE reg hold time counter S3 S0 node ISTYPE reg our sta...

Page 96: ...e remain in the ready state until one of two things happen 1 refresh input we begin to refresh 2 chip select signal we begin a read or write cycle data takes priority over refresh delaying a ref cycle...

Page 97: ..._RAS with scount scount 1 STATE rw_colsetup RAS 1 CAS 0 RowLatch 0 TA 0 WE 0 GOTO rw_CAS with scount 0 STATE rw_CAS RAS 1 CAS 1 RowLatch 0 WE BWR TA 0 IF scount 4 then rw_TA with scount 0 ELSE rw_CAS...

Page 98: ...BR_RAS_LOW with scount 0 ELSE CBR_CAS_LOW with scount scount 1 STATE CBR_RAS_LOW TA 1 RAS 1 CAS 1 WE 0 RowLatch 1 IF scount 1 then CBR_RAS_HOLD with scount 0 ELSE CBR_RAS_LOW with scount scount 1 STAT...

Page 99: ...s bootloader this code is executed first and copies all of the system code from RAM into ROM in order to match the compiler s expectations Please note that when booting via this code program space is...

Page 100: ...t will 26 cause a jump to main 27 28 The reset section is located at p 0 in the mapfile This section is 29 intended to hold system reset code This code should jump to start 30 when it is done 31 32 se...

Page 101: ...9 F__break dc TOP_OF_MEMORY 80 81 __y_size the base of dynamic memory 82 83 global F__y_size 84 F__y_size dc BOTTOM_OF_MEMORY 85 86 errno error type set by some libraries 87 88 global Ferrno 89 Ferrno...

Page 102: ...136 nop pipeline delay 137 _LOOP10 and go get another 24 bit word 138 x space load from EPROM done 139 end_xload 140 141 now set bus control register to set wait states 142 movep 01d27f x fffffb see m...

Page 103: ...ion being 212 returned This negative of this size is then patched into the 213 second move N n6 instruction so that we can clean up after the 214 function call If no structure is returned 0 is patched...

Page 104: ...call 240 241 org p 242 243 global dummy_call 244 dummy_call 245 jsr dummy_call 246 move 1 n6 247 move r6 n6 248 move 1 n6 249 move x r6 ssh 250 tst a r6 n6 251 rts 252 253 endsec 254 255 section init_...

Page 105: ...2 313 please refer to the memory map documentation for more details 314 315 316 Program space reservations 317 318 reserve everything above the internal 20K program RAM 319 nothing else is writeable i...

Page 106: ...0x104000 356 endsec 357 358 we can t actually store anything in peripheral memory so 359 block it off 360 section gen_periph 361 org x 100000 starts at 0x100000 362 ds 4000 0x104000 0x100000 363 endse...

Page 107: ...8 3 QUEUES QUEUES ASM 95 8 3 Queues queues asm queues asm contains basic circular queue code This code is used mainly by the display code...

Page 108: ...queue 14 dequeue grabs the word from the front of the queue 15 16 17 Raymond Jimenez 18 EE CS 52 19 February 16 2011 20 21 Revision history 22 23 2011 2 16 Raymond Jimenez initial revision 24 25 26 2...

Page 109: ...ts None 77 78 Outputs None 79 80 Error Handling None 81 82 Algorithm None 83 84 Data Structures None 85 86 Registers changed None 87 88 Limitations None known 89 90 Known Bugs None 91 92 Special Notes...

Page 110: ...utputs None 135 136 Error Handling None 137 138 Algorithm None 139 140 Data Structures None 141 142 Registers changed None 143 144 Limitations None known 145 146 Known Bugs None 147 148 Special Notes...

Page 111: ...186 Return Values ZF set if queue is full 187 188 Global Variables None 189 190 Shared Variables None 191 192 Local Variables None 193 194 Inputs None 195 196 Outputs None 197 198 Error Handling None...

Page 112: ...the queue to return 254 255 Operation Dequeue takes the queue and calls queue_full to see 256 if it is full if so it waits for it to dequeue once that is checked 257 it then puts the value of the ite...

Page 113: ...311 START_CRITICAL 312 START OF CRITICAL CODE 313 314 move x r0 b grab the head pointer so that we can modify it 315 and do comparisons increments on it 316 move b1 n0 also put it in n0 so we can grab...

Page 114: ...he end of the queue and then increments the pointer and wraps it 362 as necessary to fit within the data block 363 364 Arguments a1 the data to place at the end of the queue 365 we don t use a0 a2 366...

Page 115: ...increment the pointer to the beginning of data 422 move r0 423 move r0 424 move a1 x r0 n0 grab from a0 and put it into the queue 425 move r0 and restore r0 to the start of the queue struct 426 move r...

Page 116: ...queues asm 2011 02 22 453 454 rts return from subroutine 455 end function 456 457 458 459 460 endsec 461 462 463 9...

Page 117: ...c display asm display inc contains important defines and constants for the display code located in display asm display asm contains the display code We assume a HD44780 compatible LCD that is connecte...

Page 118: ...0000 19 DISPLAY_ADDR EQU 100000 20 21 allocate 255 characters to be written to the LCD 22 at any given time 23 DISPLAY_TEMP_BUF EQU ff 24 25 26 we steal these from interfac h so that we can 27 use the...

Page 119: ...5 section display here s our declaration for our file 26 INCLUDE display inc 27 INCLUDE macros inc 28 29 we declare volatile data structures first 30 org x keep all the large stuff in sram dram x ram...

Page 120: ...eral constants corresponding to what to display 88 for a given status 89 status_play_str 90 dc Play 00 91 status_fastfwd_str 92 dc FF 00 93 status_reverse_str 94 dc Rev 00 95 status_idle_str 96 dc Sto...

Page 121: ...ty 135 136 check if there s any commands to be sent 137 jsr queue_empty 138 jeq display_update_done if empty don t do anything 139 140 display_update_process 141 jsr dequeue else we dequeue the comman...

Page 122: ...ed 205 move ssh x r6 save the return address 206 move r6 n6 allocate local stack space of size k 207 208 save all registers we use so we can restore later 209 move r0 ssh we use r0 only 210 move r1 ss...

Page 123: ...rts return from subroutine 256 end Fdisplay_init 257 258 259 display_write_string 260 Functional Specification 261 262 Description This takes an ASCII null terminated string and 263 writes it to the...

Page 124: ...se a0 so keep it on the stack 308 PUSH_ACC a 309 310 move r0 r1 we ll use r1 as the real counter 311 move display_queue r0 312 and r0 pointing to the queue for 313 the enqueue call 314 315 316 initial...

Page 125: ...6 There is no error handling if given an invalid address an unpredictable 367 result will occur 368 369 Operation display_set_loc enqueues the appropriate command bits 370 to set the LCD to the given...

Page 126: ...location for timing 421 clr a 422 jsr enqueue 423 424 end of body code now restore all registers 425 POP_ACC a 426 move ssh r0 427 428 rts return from subroutine 429 end display_set_loc 430 431 432 F...

Page 127: ...o change b so preserve it 487 PUSH_ACC b 488 489 we change the address to display in the upper top right corner always 490 since our strings are fixed length we can just rely on them to 491 mask the p...

Page 128: ...ation 532 then clears the location and then proceeds to write the string to the 533 location 534 535 Arguments 536 537 Return Values None 538 539 Global Variables None 540 541 Shared Variables None 54...

Page 129: ...g to write has to be in x space since the title is volatile 597 move r1 r0 move our string pointer back in place 598 jsr display_write_string 599 600 601 end of body code now restore all registers 602...

Page 130: ...n6 k is the amount of local space needed 659 move ssh x r6 save the return address 660 move r6 n6 allocate local stack space of size k 661 662 save all registers we use so we can restore later 663 mo...

Page 131: ...s then calls dec2string and displays it at the appropriate 708 spot This step is repeated for the next 2 subdivisions seconds and 709 tenths of seconds each division taking the remainder of the last 7...

Page 132: ...we compare if the time is equal to TIME_NOTIME 770 move b a 771 772 cmp TIME_NONE a 773 jeq display_time_done if it is equal do not display anything 774 775 now that we re cleared let s write the minu...

Page 133: ...rt_temp_buf r0 822 jsr dec2string 823 jsr display_write_string 824 825 and that s it for displaying the time 826 827 828 829 830 display_time_done 831 832 end of body code now restore all registers 83...

Page 134: ...ion History 2011 02 16 Raymond Jimenez first revision 886 887 global Fdisplay_volume 888 Fdisplay_volume C entry point 889 890 standard C prologue 891 move 0 n6 k is the amount of local space needed 8...

Page 135: ...y_write_string 919 920 this is followed by writing the dB 921 922 move atten_suffix r0 923 jsr display_write_string 924 925 926 927 end of body code now restore all registers 928 move ssh r0 929 POP_A...

Page 136: ...Keypad keyfunc inc keyfunc asm keyfunc inc contains important definitions for the keypad code mostly keyscan code definitions keyfunc asm contains the keypad processing code and the event handler ins...

Page 137: ...13 if our translated key value is equal to this don t 14 do anything 15 KEY_NOP EQU ffffff 16 17 we steal the definitions below from interfac h in order 18 to use them in our assembly 19 20 KEY_TRACK...

Page 138: ...r documentation 17 18 19 20 21 section keyfunc here s our declaration for our file 22 INCLUDE keyfunc inc 23 INCLUDE macros inc 24 25 we declare volatile data structures first 26 org x keep all the vo...

Page 139: ...ys otherwise 77 something is wrong 78 dc KEY_NOP key 16 don t do anything but it s 79 odd that it s even here 80 dc KEY_NOP key 17 don t do anything 81 dc KEY_NOP key 18 don t do anything 82 dc KEY_NO...

Page 140: ...7 reading from the keypad chip 138 move x0 x raw_key then into our variable 139 140 move HAVE_KEY x0 and then signal we have a key 141 move x0 x raw_havekey 142 143 restore registers 144 move ssh x0 1...

Page 141: ...y 200 201 restore registers 202 move ssh r0 203 204 standard C epilogue 205 move 0 1 n6 206 move r6 n6 deallocate local stack space set ccr flags 207 tst a 208 move x r6 ssh get the return address 209...

Page 142: ...address 260 move r6 n6 allocate local stack space of size k 261 262 save all of the registers we use 263 move r0 ssh save both r0 n0 264 move n0 ssl 265 266 move x raw_havekey a we check if we have a...

Page 143: ...ee if there is a key ready 305 if not it loops until there is It then grabs the value of raw_key clears 306 unnecessary bits and looks up that value in a table which is then put into 307 a1 308 309 Ar...

Page 144: ...nter 356 move x raw_key a move our key into a so we can clear 357 and KEY_VALID_MASK a clear extreneous high bits 358 move a1 n0 we use the key as an index 359 360 move p r0 n0 a grab the keycode into...

Page 145: ...IDE INTERFACE 133 8 6 IDE Interface ide inc contains important definitions for the IDE code mostly IDE standard definitions ide asm contains the IDE block reading code as well as the initialization c...

Page 146: ...E_ALT_STATUS_REG EQU 102e00 22 IDE_ALT_CONTROL_REG EQU 102e00 23 24 all registers are 8 bits long 25 IDE_REG_LENGTH EQU 8 26 27 28 now we define various commands 29 30 to enable LBA and device 0 write...

Page 147: ...hed and in the master 21 position 22 23 Operation It writes IDE_SELECT_0_LBA to address IDE_DEVHEAD_REG which 24 is the device head register It then loops until the drive is ready for 25 activity that...

Page 148: ...faster transfer mode 81 move IDE_SET_TRANSFER_MODE r0 82 move r0 x IDE_FEATURE_REG 83 84 move IDE_SET_FASTER_PIO r0 85 move r0 x IDE_SEC_CT_REG 86 87 move IDE_SET_FEATURES r0 88 move r0 x IDE_COMMAND_...

Page 149: ...or_ide 146 wait_for_ide assembly entry point 147 148 save all registers we use so we can restore later 149 move r0 ssh 150 151 wait_for_ide_loop 152 move x IDE_STATUS_REG r0 153 nop GDB delay 154 jset...

Page 150: ...one known 199 200 Known Bugs None 201 202 Special Notes 203 204 Revision History 2011 03 08 Raymond Jimenez first revision 205 206 global Fget_blocks 207 Fget_blocks C entry point 208 standard C prolo...

Page 151: ...ported back 249 jsr wait_for_ide 250 251 252 we now clear a and use it as our data word counter 253 clr a 254 255 we can get a maximum of b1 words so we start looping and comparing 256 get_all_blocks...

Page 152: ...91 nop 292 jmp get_all_blocks 293 294 get_all_blocks_end 295 296 297 restore registers 298 POP_ACC b 299 move ssl r1 300 move ssh r0 301 302 303 standard C epilogue 304 move 0 1 n6 305 move r6 n6 deal...

Page 153: ...most of the register definitions and command definitions for both the MP3 decoder VS1053b and the DAC WM8741 sound asm contains the DMA handling code the interrupt handling code and the interface cod...

Page 154: ...per DAC startup once we change clock freq up 20 we can do higher serial too 21 we also start with 16 bit words since we re writing to SCI initially 22 23 ESSI0_CRA_1ST EQU 100831 0001 0000 0000 1000 0...

Page 155: ...ormal mode we run at decoder 55MHz so since max serial is CLKI 7 we get to 60 run serial at 6 66MHz now 61 ESSI0_CRA_SCI EQU ESSI0_CRA_1ST M_PM 05 62 ESSI0_CRB_SCI EQU ESSI0_CRB_1ST 63 64 we switch mo...

Page 156: ...or data XDCS asserted byte wise 89 0 MSB shifted first 90 1 internal clock 91 1 SC2 is an output 92 0 SC1 is an output 93 0 SC0 is an output 94 95 96 ESSI0_PCRC_SCI EQU 00003a 0000 0000 0000 0000 0011...

Page 157: ...shifted over another 8 since they re the first 8 bits 135 SCI_WRITE_CMD EQU 02 ESSI_BYTE_SHIFT 136 SCI_READ_CMD EQU 03 ESSI_BYTE_SHIFT 137 138 register addresses 139 SCI_MODE EQU 00 ESSI_SCI_SHIFT 140...

Page 158: ...17 ESSI_SCI_SHIFT 176 177 I2S_CONFIG_ADDR EQU C040 ESSI_SCI_SHIFT 178 ENDFILLBYTE_ADDR EQU 1e06 ESSI_SCI_SHIFT 179 180 181 182 and we set these registers to enable I2S per the spec 183 184 GPIO_DDR_VA...

Page 159: ...SECTION 219 220 ESSI1_CRA EQU 100806 0001 0000 0000 1000 0000 0110 221 0 0 000 reserved 222 0 SC1 as flag 223 01 0 16b words 224 0 align left 225 0 0000 on demand mode 226 1 no prescaler 227 0000 011...

Page 160: ...0 1100 258 0000 0000 0000 0000 00 reserved 259 1 TX enabled 260 0 RX is GPIO 261 1 CLK enabled 262 1 SC2 enabled 263 0 SC1 is GPIO 264 0 SC0 is GPIO 265 266 see errata for mask 4H80G we find that GPIO...

Page 161: ...e with 296 DAC_VOL_CONTROL EQU 07 DAC_DATA_SHIFT 297 0001 0111 298 0 not muted 299 00 ZFLAG from both channels 300 0 no analog mute on ZFLAG 301 0 no mute 302 1 control both channels w left atten 303...

Page 162: ...curbuf 28 ds 1 a pointer to the current buffer we re playing 29 curbuflen 30 ds 1 length of the current buffer 31 32 nextbuf 33 ds 1 a pointer to the next buffer double buffering 34 nextbuflen 35 ds 1...

Page 163: ...e 80 81 Registers changed None 82 83 Limitations None known 84 85 Known Bugs None 86 87 Special Notes 88 89 Revision History 2011 02 16 Raymond Jimenez first revision 90 91 global Fsetup_mp3 92 Fsetup...

Page 164: ...so 138 12MHz clock is really slow 139 2 set the I2S output to enable 140 3 set volume to max DAC handles volume 141 4 in the future we ll add patches like FLAC decoder 142 143 1 we set the clock multi...

Page 165: ...ove SCI_WRITE_CMD SCI_WRAMADDR r0 we need to set where 196 to write to in 1053 197 move I2S_CONFIG_ADDR r1 198 jsr write_sync_mp3_sci 199 move SET_WRAMADDR_WAIT r0 200 jsr sleep 201 202 move SCI_WRITE...

Page 166: ...1 248 249 install the pair of DREQ handlers 250 move dreq_asserted_handler r1 251 move r0 p I_IRQB 252 move r1 p I_IRQB 1 253 254 move dreq_deasserted_handler r1 255 move r0 p I_IRQC 256 move r1 p I_I...

Page 167: ...nop 310 rts return from subroutine 311 312 end Fsetup_mp3 313 314 315 mp3_to_data_mode 316 Functional Specification 317 318 Description mp3_to_data_mode changes ESSI0 to enter data 319 mode so that we...

Page 168: ...e done 364 nop 365 nop 366 nop 367 jclr M_TDE x M_SSISR0 wait until transmitted 368 369 need to temporarily disable ESSI pins otherwise they retain functionality 370 move 0 r0 371 move r0 x M_PCRC 372...

Page 169: ...19 Inputs None 420 421 Outputs None 422 423 Error Handling None 424 425 Algorithm None 426 427 Data Structures None 428 429 Registers changed None 430 431 Limitations None known 432 433 Known Bugs Non...

Page 170: ...482 bset M_SSRE x M_CRB0 483 484 485 and that s it 486 487 end of body code now restore all registers 488 move ssh r0 489 490 nop pipeline cache issue see errata 491 rts return from subroutine 492 end...

Page 171: ...e require the strange bitfield structure of r0 1 in order to 543 prevent us from having to transfer into a and then rotate it s much faster 544 this way and since we mostly transmit constants to SCI w...

Page 172: ...ese words 581 so set up TX10 TX20 appropriately 582 move XCS_LOW r2 583 move r2 x M_TX02 584 585 586 and then we move in our words 587 588 nop wait for delay 589 nop 590 nop 591 jclr M_TDE x M_SSISR0...

Page 173: ...s None 646 647 Outputs None 648 649 Error Handling None 650 651 Algorithm None 652 653 Data Structures None 654 655 Registers changed a 656 657 Limitations None known 658 659 Known Bugs None 660 661 S...

Page 174: ...here until TDE is set 697 move r0 x M_TX00 transmit first 16 bits command address 698 699 we first want to make sure XCS is turned on for these words 700 so set up TX10 TX20 appropriately 701 move XCS...

Page 175: ...back system 754 755 Operation Faudio_play first calls Faudio_halt which synchronously 756 stops audio playback We then set up the registers again and then start 757 the file playing by setting up the...

Page 176: ...fusion 813 move r0 x nextbuflen 814 move r0 x usedbuf 815 816 move a1 x curbuf and move in our actual buffer values 817 move b1 x curbuflen 818 819 process the mp3 buffer 820 move a1 r0 prepare argume...

Page 177: ...ssh get return address 864 865 nop pipeline cache issue see errata 866 rts return from subroutine 867 868 end Faudio_play 869 870 Faudio_halt 871 Functional Specification 872 873 Description Faudio_ha...

Page 178: ...re on are synchronous 930 move x M_IPRC a move to a so we can clear out bits 931 and M_IBL M_ICL M_D2L a clear out bits there IRQB IRQC are DRQ 932 move a1 x M_IPRC 933 934 we switch to control mode t...

Page 179: ...ransmit 2052 bytes of endfillbyte again 975 976 jsr mp3_to_data_mode 977 978 do 2052 write_endfillbyte2 979 move a1 x M_TX00 write endfillbyte 980 nop account for pipeline delay 981 nop 982 nop 983 jc...

Page 180: ...edbuf 1022 1023 Arguments None 1024 1025 Return Values None 1026 1027 Global Variables None 1028 1029 Shared Variables None 1030 1031 Local Variables None 1032 1033 Inputs None 1034 1035 Outputs None...

Page 181: ...er 1086 1087 move x curbuf r0 we indicate this buffer s been used 1088 nop 1089 move r0 x usedbuf 1090 1091 let s check if there s more data in the next buffer 1092 move x nextbuflen a 1093 cmp NO_BUF...

Page 182: ...estore all registers 1143 move ssl r0 1144 move ssh x0 1145 POP_ACC a 1146 1147 nop pipeline cache issue see errata 1148 rti return from interrupt 1149 end end_mp3_dma_handler 1150 1151 dreq_asserted_...

Page 183: ...o_buffer 1202 1203 dreq_asserted_buffer 1204 bset M_DE x M_DCR2 set our DMA channel to go 1205 jmp dreq_asserted_done 1206 1207 dreq_asserted_no_buffer 1208 move NEEDS_KICKSTART a 1209 move a1 x mp3_k...

Page 184: ...M_DCR2 disable the current DMA transfer 1264 nop 1265 nop 1266 nop pipeline delays 1267 wait for it to finish its current word transfer 1268 jset M_DACT x M_DSTR 1269 1270 end of body code now restor...

Page 185: ...rue we ve used data and have space for more 1307 but don t do anything 1308 1309 case 5 curbuf is occupied nextbuf is empty somebuf is passed 1310 return false we are accepting new data 1311 we place...

Page 186: ...mpty_nextbuf if nextbuf is empty we have more options 1374 1375 update_full_buffers 1376 scenario 1 full nextbuf curbuf 1377 but if the buffer doesn t fit we must acquit 1378 we have no space to handl...

Page 187: ...e 1421 to differentiate the two we need to compare passed to curbuf 1422 update_occupied_curbuf 1423 move x curbuf b 1424 cmp x0 b 1425 jne update_occupied_curbuf_new 1426 1427 update_occupied_curbuf_...

Page 188: ...1 and left align the 1477 lower 8 bits in a1 16 bit shift left we then clear the top 8 bits of 1478 b1 and or in b1 with x1 in order to successfully swap order this is 1479 then written back out 1480...

Page 189: ...ps 1537 nop 1538 nop 1539 process_buffer_loop 1540 1541 1542 end of body code now restore all registers 1543 move ssl x0 1544 move ssh r0 1545 POP_ACC b 1546 POP_ACC a 1547 nop 1548 rts return from su...

Page 190: ...etup_dac 1599 Fsetup_dac C entry point 1600 1601 standard C prologue 1602 move 0 n6 k is the amount of local space 1603 move ssh x r6 save the return address 1604 move r6 n6 allocate local stack space...

Page 191: ...3 end of body code now restore all registers 1654 move ssl r1 1655 move ssh r0 1656 1657 standard C epilogue 1658 move 0 1 n6 1659 move r6 n6 deallocate local stack space set ccr flags 1660 tst a 1661...

Page 192: ...gs faster since we mostly deal with pre composed constants we can use 1714 macro shifts to pre calculate everything 1715 1716 Revision History 2011 03 25 Raymond Jimenez first revision 1717 1718 globa...

Page 193: ...ne 1763 1764 Data Structures None 1765 1766 Registers changed None 1767 1768 Limitations None known 1769 1770 Known Bugs None 1771 1772 Special Notes 1773 1774 Revision History 2011 03 27 Raymond Jime...

Page 194: ...16 now we transmit the high 5 bits and latch the changes 1817 move x0 a grab the old copy 1818 lsr 5 a dac volume register is 5 bits wide per 1819 and ATTEN_REG_MASK a clear out the top 5 bits 1820 ls...

Page 195: ...ged None 1876 1877 Limitations None known 1878 1879 Known Bugs None 1880 1881 Special Notes 1882 1883 Revision History 2011 03 27 Raymond Jimenez first revision 1884 1885 global Fvol_down 1886 Fvol_do...

Page 196: ...nges 1925 move x0 a grab the old copy 1926 lsr 5 a dac volume register is 5 bits wide per 1927 and ATTEN_REG_MASK a clear out the top 5 bits 1928 lsl DAC_DATA_SHIFT a shift as necessary for write_sync...

Page 197: ...1978 Error Handling None 1979 1980 Algorithm None 1981 1982 Data Structures None 1983 1984 Registers changed None 1985 1986 Limitations None known 1987 1988 Known Bugs None 1989 1990 Special Notes 199...

Page 198: ...TED CODE 8 8 Timing timing inc contains definitions for timing such as how many loop iterations cor respond to a minimum of 1 millisecond etc timing asm provides several timing functions such as Felap...

Page 199: ...timing inc 2011 03 24 1 TICKS_PER_MS EQU 1 2 SLEEP_CYCLES EQU 8 3 1...

Page 200: ...ber of milliseconds it has 22 been since it was last called 23 24 Operation It retrieves the value of the time_elapsed_counter divides 25 it by TICKS_PER_MS and then returns this value 26 27 Arguments...

Page 201: ...end of body code now restore all registers 80 move ssl x0 81 move ssh r0 82 83 standard C epilogue 84 move 0 1 n6 85 move r6 n6 deallocate local stack space set ccr flags 86 tst a 87 move x r6 ssh ge...

Page 202: ...k 141 142 143 end of body code now restore all registers 144 move ssh r0 and restore r0 to original state 145 146 rts return from subroutine 147 end time_elapsed_update 148 149 sleep 150 Functional Sp...

Page 203: ...save all registers we use so we can restore later 193 move r1 ssh 194 195 196 do r0 outer_sleep_loop 197 198 do SLEEP_CYCLES inner_sleep_loop 199 200 move x 0 r1 this instruction ensures at least one...

Page 204: ...192 CHAPTER 8 ANNOTATED CODE 8 9 Interrupts intrrpts asm contains the interrupt installation initalivation code...

Page 205: ...inc 17 INCLUDE display inc 18 INCLUDE macros inc 19 org x 20 21 22 org p we want to be located in program space 23 24 Fstart_intr_setup 25 Functional Specification 26 27 Description Fstart_intr_setup...

Page 206: ...routine 83 end Fstart_intr_setup 84 85 86 global Fsetup_timer0 prologue 87 Fsetup_timer0 C entry point 88 89 move 0 n6 k is the amount of local space 90 move ssh x r6 save the return address 91 move r...

Page 207: ...n6 138 move r6 n6 deallocate local stack space set ccr flags 139 tst a 140 move x r6 ssh get return address 141 nop 142 rts 143 144 145 global Fsetup_timer1 prologue 146 Fsetup_timer1 C entry point 1...

Page 208: ...ers used 192 move ssh x0 193 POP_ACC a 194 195 move 0 1 n6 196 move r6 n6 deallocate local stack space set ccr flags 197 tst a 198 move x r6 ssh get return address 199 nop 200 rts 201 202 203 204 205...

Page 209: ...R x M_TCSR2 245 246 Restore all registers used 247 move ssh x0 248 POP_ACC a 249 250 move 0 1 n6 251 move r6 n6 deallocate local stack space set ccr flags 252 tst a 253 move x r6 ssh get return addres...

Page 210: ...305 nop 306 nop 307 nop 308 nop 309 310 depend on BG to tell us when to stop reading 311 we are only returned control when the refresh is done 312 313 we first pulse our refresh pin 314 bset M_DO x M...

Page 211: ...ns None known 369 370 Known Bugs None 371 372 Special Notes 373 374 Revision History 2011 02 16 Raymond Jimenez first revision 375 376 global Fsetup_keypad_irq 377 Fsetup_keypad_irq assembly entry poi...

Page 212: ...return from subroutine 414 end Fsetup_keypad_irq 415 416 417 Fend_intr_setup 418 Functional Specification 419 420 Description Fend_intr_setup should be called after setting up interrupts 421 it unmask...

Page 213: ...dress 461 move r6 n6 allocate local stack space of size k 462 463 save all registers we use so we can restore later we don t use any 464 465 FORCE_INTERRUPTS_ON 466 467 end of body code now restore al...

Page 214: ...to include volume changing functions interfac h was modified to reflect our current system and was also updated to take into account the two volume up down keys mainloop c was modified to include vol...

Page 215: ...igital Audio Recorder Project 6 5 08 Glen George Added declarations for dec_FFRev_rate and inc_FFRev_rate functions 3 3 11 Raymond Jimenez Added declarations for do_VolUp and do_VolDown ifndef I__KEYP...

Page 216: ...from standard play enum status begin_RptPlay enum status start repeatedly playing from fast forward or reverse enum status start_FastFwd enum status start going fast forward enum status switch_FastFw...

Page 217: ...longer used 6 5 03 Glen George Added constant definitions of TIME_NONE PARENT_DIR_CHAR and SUBDIR_CHAR 4 29 06 Glen George Updated value of IDE_BLOCK_SIZE to be in units of words not bytes ifndef I__I...

Page 218: ...terfac h 2011 04 02 define SUBDIR_CHAR define STATUS_PLAY 0 define STATUS_FASTFWD 1 define STATUS_REVERSE 2 define STATUS_IDLE 3 define STATUS_ILLEGAL 4 define IDE_BLOCK_SIZE 256 256 words block endif...

Page 219: ...03 Glen George Moved static declarations to first keyword since the lame NIOS compiler requires it 5 15 03 Glen George Changed type on some variables to size_t for better portability and more accurate...

Page 220: ...ch the program is operating Data Structures None Shared Variables None Author Glen George Last Modified June 5 2003 extern void test_dram int main variables enum keycode key an input key enum status c...

Page 221: ...lay start_RptPlay cont_RptPlay begin_RptPlay begin_RptPlay Repeat Play start_FastFwd switch_FastFwd stop_FFRev begin_FastFwd Fast Forward start_Reverse switch_Reverse begin_Reverse stop_FFRev Reverse...

Page 222: ...k_time display_title get_track_title display_artist get_track_artist display_status xlat_stat cur_status display status display_volume the volume is also a part of the status infinite loop processing...

Page 223: ...returned as KEYCODE_ILLEGAL Algorithms The function uses an array to lookup the key types Data Structures Array of key types versus key codes Shared Variables None Author Glen George Last Modified Ma...

Page 224: ...ck Down KEY_PLAY Play KEY_RPTPLAY Repeat Play KEY_FASTFWD Fast Forward KEY_REVERSE Reverse KEY_STOP Stop KEY_VOLUP Volume Up KEY_VOLDOWN Volume Down int key an input key size_t i general loop index ge...

Page 225: ...p increase volume key processing function do_VolDown decrease volume key processing function The local functions included are none The global variable definitions included are none Revision History 6...

Page 226: ...eorge Last Modified Mar 5 1994 enum status no_action enum status cur_status variables none return the current status return cur_status do_TrackUp Description This function handles the Track Up key whe...

Page 227: ...the track information for this track display_time get_track_time display_title get_track_title display_artist get_track_artist done so return the current status return cur_status do_TrackDown Descrip...

Page 228: ...he track information for this track display_time get_track_time display_title get_track_title display_artist get_track_artist done so return the current status return cur_status stop_idle Description...

Page 229: ...status unchanged return cur_status no_update Description This function handles updates when there is nothing to do It just returns with the status unchanged Arguments cur_status enum status the curren...

Page 230: ...ling None Algorithms None Data Structures None Shared Variables None Author Raymond Jimenez Last Modified Mar 27 2011 enum status do_VolUp enum status cur_status variables none vol_up vol_up doesn t t...

Page 231: ...e Data Structures None Shared Variables None Author Raymond Jimenez Last Modified Mar 27 2011 enum status do_VolDown enum status cur_status variables none vol_down vol_down doesn t take any arguments...

Page 232: ...ned int DRAM_START DRAM_SZ DRAMptr BLOCK_SZ lfsr unsigned int DRAMptr for period 0 period BLOCK_SZ period taps at 24 23 22 17 lfsr lfsr 1 lfsr 0x1u 0xE10000u DRAMptr period lfsr for period 0 period BL...

Page 233: ...test_dram c 2011 06 14 2...

Page 234: ...stem defines such as critical memory addresses and register values general inc contains important definitons applicable to all code macros inc contains several important macros such as a x86 PUSH POP...

Page 235: ...EQU FFFFAD Port D ESSI1 GPIO Data Register 28 M_PCRE EQU FFFF9F Port E SCI Control register 29 M_PRRE EQU FFFF9E Port E SCI Direction Register 30 M_PDRE EQU FFFF9D Port E SCI Data Register 31 M_OGDB...

Page 236: ...3 84 85 86 Register Addresses 87 M_STXH EQU FFFF97 SCI Transmit Data Register high 88 M_STXM EQU FFFF96 SCI Transmit Data Register middle 89 M_STXL EQU FFFF95 SCI Transmit Data Register low 90 M_SRXH...

Page 237: ..._TX02 EQU FFFFBA ESSIO Transmit Data Register 2 146 M_TSR0 EQU FFFFB9 ESSI0 Time Slot Register 147 M_RX0 EQU FFFFB8 ESSI0 Receive Data Register 148 M_SSISR0 EQU FFFFB7 ESSI0 Status Register 149 M_CRB0...

Page 238: ...t 196 M_SSTE EQU 1C000 ESSI Transmit enable Mask 197 M_SSTE2 EQU 14 ESSI Transmit 2 Enable 198 M_SSTE1 EQU 15 ESSI Transmit 1 Enable 199 M_SSTE0 EQU 16 ESSI Transmit 0 Enable 200 M_SSRE EQU 17 ESSI Re...

Page 239: ...IRQD Mode Trigger Mode 259 M_D0L EQU 3000 DMA0 Interrupt priority Level Mask 260 M_D0L0 EQU 12 DMA0 Interrupt Priority Level low 261 M_D0L1 EQU 13 DMA0 Interrupt Priority Level high 262 M_D1L EQU C00...

Page 240: ...ntrol Status Register 310 M_TLR1 EQU FFFF8A TIMER1 Load Reg 311 M_TCPR1 EQU FFFF89 TIMER1 Compare Register 312 M_TCR1 EQU FFFF88 TIMER1 Count Register 313 314 Register Addresses Of TIMER2 315 M_TCSR2...

Page 241: ...Destination Address Register 370 M_DCO1 EQU FFFFE9 DMA1 Counter 371 M_DCR1 EQU FFFFE8 DMA1 Control Register 372 373 Register Addresses Of DMA2 374 M_DSR2 EQU FFFFE7 DMA2 Source Address Register 375 M...

Page 242: ...sfer Mode 1 420 M_DTM2 EQU 21 DMA Transfer Mode 2 421 M_DIE EQU 22 DMA Interrupt Enable bit 422 M_DE EQU 23 DMA Channel Enable bit 423 424 DMA Status Register 425 M_DTD EQU 3F Channel Transfer Done St...

Page 243: ...Bus Lock Hold 482 M_BRH EQU 23 Bus Request Hold 483 484 DRAM Control Register 485 M_BCW EQU 3 In Page Wait States Bits Mask BCW0 BCW1 486 M_BRW EQU C Out Of Page Wait States Bits Mask BRW0 BRW1 487 M_...

Page 244: ...rity bits in OMR 533 M_MA EQU 0 Operating Mode A 534 M_MB EQU 1 Operating Mode B 535 M_MC EQU 2 Operating Mode C 536 M_MD EQU 3 Operating Mode D 537 M_EBD EQU 4 External Bus Disable bit in OMR 538 M_S...

Page 245: ...imer Interrupts 599 600 I_TIM0C EQU I_VEC 24 TIMER 0 compare 601 I_TIM0OF EQU I_VEC 26 TIMER 0 overflow 602 I_TIM1C EQU I_VEC 28 TIMER 1 compare 603 I_TIM1OF EQU I_VEC 2A TIMER 1 overflow 604 I_TIM2C...

Page 246: ...54 SCI Transmit Data 629 I_SCIIL EQU I_VEC 56 SCI Idle Line 630 I_SCITM EQU I_VEC 58 SCI Timer 631 632 633 HOST Interrupts 634 635 I_HRDF EQU I_VEC 60 Host Receive Data Full 636 I_HTDE EQU I_VEC 62 Ho...

Page 247: ...general inc 2011 03 29 1 FALSE EQU 0 2 TRUE EQU 1 3 1...

Page 248: ...ACC 0 finish off with ACC1 18 19 ENDM 20 21 START_CRITICAL MACRO 22 grab the interrupt bits and toss it on the stack 23 movec sr ssh toss it on the stack 24 ori 03 mr set the interrupt mask bits 25 n...

Page 249: ...SRCDIR JUKEDIR SRCDIR TOOLDIR c DSP56K BIN key files CRT0 crt0 cln Compiler Flags CFLAGS I SYSDIR IC DSP56K include BC DSP56K lib DDSP56K mx memory Wall alo O ASMFLAGS Jukebox files JUKEFILES wildcar...

Page 250: ...fs h SYSDIR keyproc h SYSDIR updatfnc h SYSDIR trakutil h SYSDIR fatutil h playmp3 cln SYSDIR playmp3 c SYSDIR mp3defs h SYSDIR keyproc h SYSDIR updatfnc h SYSDIR trakutil h SYSDIR fatutil h ffrev cln...

Page 251: ...cln asm o OBJDIR display cln SYSDIR display asm SYSDIR display inc CC CFLAGS c patsubst cln asm o OBJDIR queues cln SYSDIR queues asm CC CFLAGS c patsubst cln asm o OBJDIR keyfunc cln SYSDIR keyfunc...

Page 252: ...240 CHAPTER 8 ANNOTATED CODE...

Page 253: ...taking care to prevent shorting out adjacent pins Once this is done carefully place the DRAM back in its slot and tilt it back until the latches lock in place The cause of this issue is believed to b...

Page 254: ...fter running makesong on it with a modification time equivalent to the length of the song after midnight In other words if the song is 4 minutes and 30 seconds long simply change the modification time...

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