Network and Remote Operation
R&S
®
FSW
760
User Manual 1173.9411.02 ─ 43
STATus:QUEStionable:ACPLimit Register
The STATus:QUEStionable:ACPLimit register contains information about the results of
a limit check during ACLR measurements. A separate ACPLimit register exists for
each active channel.
You can read out the register with
STATus:QUEStionable:ACPLimit:CONDition?
or
STATus:QUEStionable:ACPLimit[:EVENt]?
Table 13-11: Meaning of the bits used in the STATus:QUEStionable:ACPLimit register
Bit No.
Meaning
0
ADJ UPPer FAIL
This bit is set if the limit is exceeded in the
upper adjacent
channel
1
ADJ LOWer FAIL
This bit is set if the limit is exceeded in the
lower adjacent
channel.
2
ALT1 UPPer FAIL
This bit is set if the limit is exceeded in the
upper 1st alternate
channel.
3
ALT1 LOWer FAIL
This bit is set if the limit is exceeded in the
lower 1st alternate
channel.
4
ALT2 UPPer FAIL
This bit is set if the limit is exceeded in the
upper 2nd alternate
channel.
5
ALT2 LOWer FAIL
This bit is set if the limit is exceeded in the
lower 2nd alternate
channel.
6
ALT3 … 11 LOWer/UPPer FAIL
This bit is set if the limit is exceeded in one of the lower or upper alternate channels 3 … 11.
7
CACLR FAIL
This bit is set if the CACLR limit is exceeded in one of the gap channels.
8
GAP ACLR FAIL
This bit is set if the ACLR limit is exceeded in one of the gap channels.
9 to 14
Unused
15
This bit is always 0.
STATus:QUEStionable:EXTended Register
The
STATus:QUEStionable:EXTended
register contains further status information
not covered by the other status registers of the R&S
FSW. A separate
EXTended
reg-
ister exists for each active channel.
You can read out the register with
STATus:QUEStionable:EXTended:CONDition?
or
STATus:QUEStionable:EXTended[:EVENt]?
Remote Control Basics