R&S AFQ100A
Specifications of Digital Interfaces
1401.3084.32
8.14
E-3
Port 2
The memory data are output in two words with a width (length) of 16 bits each. Every word will be
passed over along with a clock signal.
Connector:
The pins are assigned as follows:
AFQ-B18 - Port 2: PARALLEL DATA
Signals for I
Signals for Q
LVDS "p"
LVDS "n"
LVDS "p"
LVDS "n"
Pin Pin
Pin Pin
Bit 0 (LSB)
1
35
Bit 0 (LSB)
18
52
Bit 1
2
36
Bit 1
19
53
Bit 2
3
37
Bit 2
20
54
Bit 3
4
38
Bit 3
21
55
Bit 4
5
39
Bit 4
22
56
Bit 5
6
40
Bit 5
23
57
Bit 6
7
41
Bit 6
24
58
Bit 7
8
42
Bit 7
25
59
Bit
8 10
44 Bit
8 27
61
Bit
9 11
45 Bit
9 28
62
Bit
10 12 46 Bit
10 29 63
Bit
11 13 47 Bit
11 30 64
Bit
12 14 48 Bit
12 31 65
Bit
13 15 49 Bit
13 32 66
Bit
14 16 50 Bit
14 33 67
Bit 15 (MSB)
17
51
Bit 15 (MSB)
34
68
Clock 9 43 Clock 26 60
LVDS "p" und LVDS "n" are a pair of wires (lines). The signals have to be transmitted at a differential
impedance of 100
Z
and terminated appropriately to avoid signal reflections.
Note:
Because of large clock rates and high slew rates a proper cabling is necessary: Avoid impedance
discontinuities and branch lines. The differential line should be terminated properly (100 ) and the
resistor must be as close as possible to the line end.
Clock and data are in phase, this means, the rising clock slopes (edge) coincide with the transitions
between two consecutive symbols. Furthermore, the clock can be inverted, hence the falling clock slope
coincides with the transitions between two consecutive symbols (see chapter 4, section "
").
