RadiSys EPS-6315, Hardware Reference Manual, Page: 64 / 123

EPC
®
-6315 Hardware Reference
54
RadiSys 82600 system controller
The 82600 is a highly integrated chipset. In an embedded Intel Architecture I/O
system, the 82600 replaces four components: North Bridge, South Bridge,
PCI-to-PCI Bridge and Super I/O. The chip includes:
• Processor/Host bus support
Compatible with Intel Pentium processors.
GTL bus driver technology.
Support for 66MHz, 100MHz, and 133MHz processor side and memory buses.
• Integrated SDRAM controller with direct Flash support :
Support for 256Mb or 512Mb SDRAM technology.
16MB to 2GB of main memory.
7.8, 15.6, and 125 microsecond refresh rates supported.
ECC support with automatic single bit error “scrub”, multiple bit error detect.
Flash BIOS allowed on SDRAM bus.
• Dual PCI bus architecture :
Independent local and backplane PCI buses with integrated virtual PCI to PCI bridge.
Provides isolation between local and backplane peripherals.
Asynchronous operation of both PCI buses.
Supports concurrent EPC-6315, local PCI and backplane PCI transactions.
• Local PCI bus :
33MHz interface.
3.3V and 5V, PCI 2.2 compliant.
5 BREQ/BGNT pairs.
• Backplane PCI (BPCI) bus :
PCI Rev. 2.2, 3.3V and 5V, 33/66MHz interface compliant.
7 BREQ/BGNT pairs.
May supply all PCI central resource functions; these functions can be disabled
for non-Monarch applications.
• Integrated core PC logic :
Includes all legacy PC/AT compatible peripherals.
Two 82C59 interrupt controllers.
Two 82C37 DMA controllers.
82C54 timer/counter.
74LS612 address mapper.
• Real-time clock :
256 byte battery backed CMOS SRAM.
• Integrated peripherals :
Ultra DMA/66 EIDE interface.
COM1 and COM2 support with 16550 compatible UARTs.
PS/2 compatible keyboard and mouse ports.
SMBus host interface.
• Power Management Support .