RadiSys EPS-6315, Hardware Reference Manual, Page: 120 / 123

EPC
®
-6315 Hardware Reference
110
SRAM
(Static Random Access Memory) A semiconductor RAM device in which the data
remains permanently stored as long as power is applied, without the need for
periodically rewriting the data into memory.
standoff
A mechanical device, typically constructed of an electrically non-conductive
material, used to fasten a circuit board to the bottom, top, or side of a
protective enclosure.
symmetrically
addressable
SIMM
A SIMM, the memory content of which is configured as two independent banks.
Each 16-bit wide bank contains an equal number of rows and columns and is
independently addressable by the CPU via twin row address strobe registers in the
DRAM controller.
SYSCLK
(ISAbus System Clock) The ~8.33MHz clock signal present on the ISAbus to which
all bus transactions are synchronized.
system
memory
See conventional memory .
TB or TByte
(Terabyte) Approximately one thousand billion (US) or one billion (Great Britain)
bytes. 2^40 = 1,099,511,627,776 bytes exactly.
UED
(User Editable Drive) A feature of the NY1210’s Phoenix NuBIOS. When a “User”
type hard disk drive setting shows in the IDE Adapter Sub-Menu the BIOS queries
the hard disk drive for the purpose of retrieving disk geometry. If the hard disk drive
is capable of providing this information, the BIOS uses it to automatically set up the
drive for use with the system.
VESA
(Video Electronics Standards Association) A group of hardware and software
vendors that define specifications for hardware and software interfaces for a variety
of devices.
VGA
(Video Graphics Adapter) A popular PC graphics controller and display adapter
standard developed by IBM. The standard specifies, among other things, the
resolution capabilities of the display device. Display devices meeting the VGA
standard must be capable of displaying a minimum resolution of 640 horizontal
pixels by 480 vertical pixels with at least 16 screen colors.
wait state
A period of one or more microprocessor clock pulses during which the CPU suspends
processing while waiting for data to be transferred to or from the system data or
address buses.