Radio Shack TRS-80 Reference Handbook Download

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Summary of Contents for TRS-80

Page 2: ...Ita I aeK A DIVISION OF TANDY CORPORATION One Tandy Center Fort Worth Texas 76102...

Page 3: ...to the use of the information contained herein Wh iie every precaution has been taken in the preparation of this book the publisher assumes no responsibility for errors or omissions Neither is any lia...

Page 4: ...eeing all in one place If you are a hobbyist who can convert Hex to Decimal in the blink of an eye and you ve entered 16K BASIC languages using front panel switches then this book will probably appear...

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Page 6: ...AMs 34 Video Processing 34 Keyboard 44 Input and Output Port 44 System Power Supply 52 Level II ROMs 55 ADJUSTMENTS AND TROUBLESHOOTING 57 THE OUTSIDE WOR LD 83 Memory Mapped External Device 86 Port B...

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Page 8: ...rds A NAND gate is shown like an OR gate and the OR gate looks like a NAND gate To top it all off the power supply consists of two large rectangles with transistors and resistors sticking out of them...

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Page 10: ...tem the ROM Read Only Memory could be considered the brains The ROM tells the CPU what to do how to do it and where to put it after it s done Without the ROM the CPU would just sit there and oscillate...

Page 11: ...TAPE INTERFACE IN DATA IN OUT 1 l v TAPE RECORDER PLAYER DATA IN OUT cs RAM DATA OUT KEYBOARD EN DATA IN OUT VIDEO cs RAM VIDEO PROCESSING VIDEO 1 TERMINAL VRAM ECT ISTER OCK VIDEO DIVIDER CHAIN DOT C...

Page 12: ...e data that is on the data lines Notice that only the CPU communicates with all other sections If the CPU is told by ROM to store something from ROM into RAM the CPU can t make the RAM receive ROM dat...

Page 13: ...is located from address 3800 to 38FF The Video Display is located from 3C00 to 3FFF The RAMs start at 4000 and depending on how much RAM is in the system can extend down to address 7FFF As we told yo...

Page 14: ...3800 To Keyboard 38FF 3900 To Not used 3BFF 3C00 To Video Display 3FFF 4000 To RAM Used by BASIC LEVEL 1 41 FF 4K 4200 Useable RAM starts here J RAM To 1 4FFF 8K 5000 RAM To RAM 1 5FFF 16K 6000 RAM To...

Page 15: ...ce pin 15 is the enable input to th is part of Z72 pins 12 and 11 will always be active 14 f peration Notice also pins 7 and 6 of Z56 These two pins enable the clear function for the counter When one...

Page 16: ...the CPU toward a known address to enable it to get on the right track An example of a lost CPU would be during a bad cassette load attempt If a cassette is loading and suddenly there is missing inform...

Page 17: ...are used Instead of the bar is because computer printouts write asterisks better than bars Throughout thiS book we use both methods of naming signals we ll use the method which appears on the Schemat...

Page 18: ...gate wh ich generates DB IN As you can see Z53 pin 6 is the major source of input or output data control If pin 6 is high DBOUT is high and DBIN is low Therefore the input buffers are enabled and the...

Page 19: ...d to WR Memory Write which is pin 22 of Z40 When we get a low at the MREO output and a low at the WR output then and only then will we get a low at WR OUT Output OUT is Output control This signal when...

Page 20: ...A13 A12 A11 A10 A9 A8 A12 through A15 form the most significant hex character A8 through A11 form the next most significant hex character A8 and A9 are the two bits we had to add to complete that last...

Page 21: ...B MEM 6 _ __ I __ 1 I t RAM 5V L A12 t 131A 16 r T 1 4 7K 4 7K 9 o 7 A13 10 1 I _ 8 3 I B Z21 I I 11 11 I 0 10 6 74LS156 12 A14 t Cl 7 2 l 5V 151 C2 I 15 6 3 I TR62 5 0 4 7K 4 I I 13 4 5 62 61 I 12 f1...

Page 22: ...which is called a DIP shunt A DIP shunt is like a shorting bar array except that the bars may be broken By breaking some bars and leaving the others intact the address decoder is programm ed to refle...

Page 23: ...e DBOUT and DBIN signals are switched the same way as if we had a ROM select Therefore Keyboard data will get to the CPU s data bus for processing 22 Video Display RAM Select In the binary breakdown f...

Page 24: ...n the output Instead the output transistors have open collectors It is the responsibility of ex ternal circuitry to pull them up The open col lector outputs may be tied together for a JJwire OR functi...

Page 25: ...data into RAM As shown on Line S MREQ will go low A short time lat r WR will go low Line D shows Z74 pin 3 gomg high at the same time WR went low The flip flops now have a logical high applied to the...

Page 26: ...ClK 69 PIN 3 B MREO it 40 PIN 19 C WR it 40 PI N 22 D MREO it 74 PIN 3 E NEXT 69 PIN 5 F OMUX it 69 PIN 9 H OCAS it 7f J PIN 6 J RAS it 72 PIN 5 K MUX 72 PIN 3 l CAS it 72 PIN 9 FIGURE 4 Waveform Cha...

Page 27: ...changes state it goes high The multiplexer Z35 and Z51 now switch and the high order addresses 26 are applied to the RAMs CAS will now go low CAS is applied to buffer Z67 pin 14 Pin 13 of Z67 passes C...

Page 28: ...d Z71 during the discus sion of the RAM Z71 is a DIP shunt It is used to program the size of memory in a system Find pin 13 on the RAM Follow it down and you will see that it is tied to two pins of DI...

Page 29: ...scillator supplies the divide by 12 counter with 28 a reference frequency in a 64 character format The D flip flop supplies the counter with the reference frequency in a 32 character format The multip...

Page 30: ...will be short ed to pins 4 7 and 9 respectively The elec tronic switch was flipped Now we have the frequency source from Z70 pin 9 tied to coun ter Z58 Pin 7 of Z43 is held low all the time and pin 9...

Page 31: ...t Conditioning Wavefonn The signals that changed are very important to the Video Processor section The first LATCH is used to delay a character between RAM and the character generator The second signa...

Page 32: ...of Z65 will be used later Pin 12 Pin 9 Pin 8 Pin 11 Output A Output B Output C Output D 1 o 1 1 which is equal to 14 But notice AND gate Z66 pins 3 4 and 5 These pins are tied to outputs B C and D The...

Page 33: ...e are 10 address lines that will be used to address Video RAM The chain conditioning logic supplies one address C1 Z65 supplies three addresses R1 C2 and C4 Z50 supplies three addresses C8 C16 and C32...

Page 34: ...an store data into the video RAMs by causing VWR to go low If the CPU wants to read data from video RAMs RD can pass through Z49 and activate VRD A low here will open data buffers Z60 and Z44 Addresse...

Page 35: ...r cuits have been accepting timing signals from the divider chain The Sync Circuits shape up the horizontal and vertical pulses serrate the verti cal interval and send it all out to video mixing in se...

Page 36: ...scanning one of the five scan lines between character lines The last piece of data comes into 227 at pin 13 Sourced at 230 pin 13 this is the sneaky bit that is derived from data contained in RAMs 263...

Page 37: ...that particu lar ASC II character The next ASCII character is applied 36 to Z29 It outputs the first five dots for that character This process goes on until the beam has scanned the entire width of t...

Page 38: ...ion of one of these inputs to Z8 determines which side of the center line the cell is located An input at pin 6 of Z8 speci fies a left hand graphic cell Input at pin 10 of Z8 specifies a right hand g...

Page 39: ...a low on Z26 pin 8 38 Upon the next clock pulse at pin 7 of Z10 dot data will be loaded into the shift register After LATCH goes back high one dot time after going 10wL the Shift Register starts cloc...

Page 40: ...etwork Here s how it works HDRV goes high causing Z6 pin 2 to go high in this case about 5 0 volts A current flows through R20 charging C20 While C20 charges the voltage at pin 3 of Z6 slowly increase...

Page 41: ...C Line C in Figure 8 is now used as a source to NAND the horizontal and vertical syncs once more Line D shows the result of NAN Ding Line C with Line A Line E shows the result of NAN Ding Line C with...

Page 42: ...oJ oJ z I z en 0 j 0 cr w cr w X 0 E r F r z z z z z z c U l U l U l U l U l N N N N N N w Z co 0 W U J 41...

Page 43: ...put buffer transistors So essentially we have the video and sync going to two transistors These transistors act as switches controlling current flow through resistor net work R28 R27 and R23 Figure 9A...

Page 44: ...T TOP OF SCREEN VOLTS lOVOLTsrIL f V 0 4 VOLTS 4 r SCAN LINE WHITE LEVEL VIDEO HORIZONTAL SYNC te VERTICAL SYNC i BOTTOM OF SCREEN FIGURE 9B Composite Video Output 43...

Page 45: ...h that out put is pressed With no key pressed there is no voltage applied to the KR Keyboard Row lines When a key is pressed the associated pull up resistor supplies voltage Then you will be able to s...

Page 46: ...The Recorder s motor will turn on If input 02 is low when QUTSIG goes high pin 10 of Z59 will go low and the Recorder s motor will be off Cassette Motor Control At the start of a CSAVE function the Ca...

Page 47: ...ne or 46 zero is dependent upon the presence or absence of a pulse between the start of two bit times For example when the CPU outputs a one bit it will generate a start pulse One millisecond later an...

Page 48: ...1 IF PULSE PRESENT 0 IF PULSE NOT PRESENT T1_ T3 T1 1 n n n 0 85 V U Ur Ur 0 46 V 0 0 V 1 1 ms 1 NOTE PULSE WIDTH NOT DRAWN TO SCALE BIT TIME 2ms _ 1 FIGURE 10 Idealized CASSOUT 47...

Page 49: ...ve filter 48 Once filtered the next section of Z4 is used as an active rectifier CR4 and CR5 together with the biasing resistors around pins 2 3 and 4 will full wave rectify the data pulses A typical...

Page 50: ...E LINE NOTE AMPLITUDE WILL VARY DEPENDING ON RECORDER VOLUME LEVEL B CR4 CATHODE C Z4 PIN 9 D CR7 CATHODE 2 0 V OV 2 4 V OV 1 GV OV FULL WAVE RECTIFIED AUDIO INVERTED I AMPLIFIED AUDIO FILTERED AUDIO...

Page 51: ...12 at Line A Line D the output of the latch goes high as soon as pin 9 goes low OUTSIG goes low after a short time delay shown on Line C The signal will reset the flip flop as Line D shows A short ti...

Page 52: ...INE BIT TIME 1 BIT TIME 2 BIT TIME 3 BIT TIME 4 1 0 1 11 O t I 1_ 0 1 A 224 PIN 9 u u u u u B c INSIG OUTSIG U u u u u u u D 224 PIN 8 FIGURE 12 Data Latch Timing NOTE PULSE WIDTH NOT DRAWN TO SCALE 5...

Page 53: ...ly is inputted at pin 2 of J1 When power switch Sl is closed C8 filters the voltage and the net resu It is approximately 20 volts which is applied to 06 and regulator Z2 Figure 13 shows a simpli fied...

Page 54: ...pin 10 means that the 12 volt supply is approaching its maximum design cur rent of 480 milliamps If a short develops across the 12V supply Ob will activate forcing Oa to shut down With Oa off 06 s ba...

Page 55: ...urn on the node at R3 and R9 supplies more voltage for base drive of Qb As Qb takes command of the regulator loop Oa is commanded to start cutting 03 off 03 54 begins to turn Q4 off and the circuit go...

Page 56: ...re is also a 4 conductor ribbon cable green orange red and yellow coming from the Level II Board The conductors connect to the CPU Board at A11 A12 A13 and ROM The con ductors enable a Level I to Leve...

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Page 58: ...djustments Troubleshooting 57...

Page 59: ...raser end of a pencil to push the LED down through the plastic Case Bend the LED leads slightly to prevent the retainer ring from getting lost B The second mounting technique has the LED soldered dire...

Page 60: ...CASE TOP i SCREW 6 32 X1 1 4 5cml LED SOCKET AND r T RETAINER RING CASE BOTTOM 1 J A I n SCREW THREAD SCREW 6 32 t1_ FORMING 1 2 5cml x2 5cml SCREW 6 32 x 1 1 4 5cml FIGURE 14 Exploded View 59...

Page 61: ...2 VOLT SUPPLY Measure the voltage present at the top side of power resistor R18 The top side would be the end closest to the edge of the PCB Voltage shou Id be 12 0 volts 5 12 6 to 11 4 volts If the v...

Page 62: ...J3 TAPE J2 VIDEO CR2 FIGURE 2 LOGIC BOARD COMMON R10 5 R18 12 VDC RESET FIGURE 15 Logic Board 61...

Page 63: ...62 Section Isolation Flowchart Figure 16 is a Flow Chart of Section Isolation by part removal You start the process in the parallelogram block 1 This is the basic prob lem Block 2 instructs you to dis...

Page 64: ...POWER SWITCH 2 4 INTERCONNECT CABLE SOLDER BALL SHORT 15 11 14 TURN OFF POWER 5 WAIT 10 SECONDS TURN ON POWER 7 6 YES TURN OFF POWER S REMOVE DIP SHUNT AT 271 TURN ON POWER 10 9 16 TURN OFF POWER REMO...

Page 65: ...state 64 logical 1 It is held high by resistor R50 Another example is the logical 0 at pins 6 and 7 of Z56 the CPU clock divider Z42 pin 8 is always low unless resistor R67 is grounded Floating is def...

Page 66: ...ORT CPU ClK SOURCE BAD POWER UP CLEAR lOGIC DEFECTIVE CHECK SWITCH S 2 AND RESET lOGIC OPEN PCB ETCH NO NO NO NO YES MAY NOT BE CPU PROBLEM SECTION ISOLATE REPLACE 240 CPU CAS RAS lOGIC FIGURE 17 CPU...

Page 67: ...ssing data or chip select problems 66 Addressing problems can be associated with open or shorted address lines going to the ROM sockets Early versions of the Boards may have jumper modifications on th...

Page 68: ...ou suspect one of the memory locations keep in mind that the address decoder sources the memory selects The select inputs to the different memories should be the very first thing you check Failure of...

Page 69: ...ion Tool 773 10023 68 Interconnect Cable When replacing the Interconnect Cable be sure that you install the cable correctly Insert the contacts from the top side of the Board Bend the contacts 90 to f...

Page 70: ...encies for Divider Chain Figure 18 shows a chart of frequencies that can be expected at each chain output Slight devia tions from the frequencies shown should be ex pected The chart was drawn up using...

Page 71: ...getting to the multi plexer 70 If you suspect a multiplexer is not switching properly test it First make sure the address line going to the multiplexer is OK Then monitor the suspected output pin of t...

Page 72: ...Z8 while a graphic cell with vertical streaks indicates a problem with Z11 Unstable Flashing Graphics Usually harder to detect and not as common as unstable dots But same type of fix replace Z11 No I...

Page 73: ...t working 72 One important gate to consider when working with the Address Decoder is Z73 pin 6 If you do not get activity at pin 6 the whole decoder is going to be screwed up Z73 pin 6 enables Z21 the...

Page 74: ...activity at Z4 pin 10 Try loading a long program into the Computer while monitoring pin 10 It should be normally high and go low on the audio pulses So long as the pin is active and there are at leas...

Page 75: ...pect a defective OUTSIG line For some rea son OUTSIG must be active all the time or noise is triggering Z59 due to an open etch 74 Power Supply Most of the problems that result in loss of power supply...

Page 76: ...st 01 s base or emitter lead Depending on the force it might have sheared one or more leads from the PCB If you find a loose heat sink shorted or not retighten it Problems with the AC adapter are usua...

Page 77: ...test equipment the memory listing looks like some unknown language and the Relay keeps time with the garbage on the display The only logical choice you have is to burn it in Set up the computer in som...

Page 78: ...many times it is repeated The gate may not generate the same type of signal that another one did two inches away but the out put does respond in the same way under the same input conditions One of th...

Page 79: ...rted Latch signal to 226 If you want pins 13 or 5 of 226 to go high short 29 pin 3 to ground Y ou can also short the inputs to Latch 227 and cause some highs on pins 12 or 4 of Z26 If you tried the gr...

Page 80: ...ns when trouble shooting take care that you do not over cut If you do re flow solder cut marks you accidentally made in the runs with the iron to melt the splinters Never NEVER NEVER try to clean sold...

Page 81: ...ated unless the Test input is grounded at the expansion connector After finding the two bad lines you can follow one around the Board until you find an area where the two runs come close to each other...

Page 82: ...t s necessary to fix a malfunction ing unit DIP Shunts It s been said before but it needs to be said again Be careful when programming DIP shunts If undue stress is applied to a DIP shunt while progra...

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Page 84: ...he utsid orld 83...

Page 85: ...ardware for your special task you should have defined the software already How you design your hardware will be deter mined by the instructions you will use to operate it There are two approaches you...

Page 86: ...that you will not interfere with your in system RAM If you have maximum memory you may not be able to go high enough to be free from RAM But if you have only 16K or less of RAM you have thousands of p...

Page 87: ...e as SF FF goes low Therefore the output at Z2 C will go high This signal is called the WRITE and is applied to Z6 a latch 02 in Hex is 0000 0010 in binary Therefore at the same time that WRITE goes h...

Page 88: ...4lS367 D1D I I W R D q RD D I q o K1 Vee ITO com o AO_ D A4 A5 A6 A7D 74LS30 74LS02 Vee IPOWER SUPPl E AC A12 SFFF A13C q A14r AsD A9D A1OD A11 A15 Z3 74lS30 00 J FIGURE 20 Memory Mapped Coffee Pot Co...

Page 89: ...ws a logic diagram of a port based coffee pot control system Notice from Z2 to the right the circuit is the same as Figure 20 Only the reference designators have changed The major difference is how a...

Page 90: ...Vee TO 00 m K1 o 1 Vee 74LS367 74LS04 f 0 WRITE 74LS74 74LS02 READ IN c I I d OUT D 74LS30 A7D A6C A5 A4 1 A3C A2 A1 21 l FE Vce I r POWER SUPPLY AC FIGURE 21 Port Based Coffee Pot Control...

Page 91: ...low only when the CPU is outputting the column portion of an address It too is used to address Dynamic RAMS See text for operation 90 Multiplexer Control Output This output is labeled MUX It is used...

Page 92: ...ctional Data Bus 21 INT Interrupt I ut Maskable I 22 DI Bidirection Data Bus 23 TEST A Logic 0 on TEST Input Tri States A0 A15 D0 D7 WR RD IN OUT RAS CAS MUX 24 D6 Bidirectional Data Bus 25 A0 Address...

Page 93: ...y go anywhere in memory you want but this function cannot be used in the TRS 80 due to internal circuits See a Z 80 technical manual for more information on this input Interrupt Acknowledge INTAK goes...

Page 94: ...s ist 93...

Page 95: ...2 C32 0 1 I1F 10 50V Disc 1500053 C33 0 1 tIF 10 12V Disc 1500052 C34 0 1 tIF 10 50V Disc 1500053 C35 0 1 I1F 10 12V Disc 1500052 J _l__I_Co_n_n_ec_to_r _S_o_ck_et_ _0_1 N_ _5_P_in__12100033 Part Symb...

Page 96: ...106 R26 1Megohm 1 4W 5 4704102 R27 330 ohm 1 4W 5 4704036 R28 270 ohm 1 4W 5 4704034 R29 1 8 K 1 4W 5 4704052 R30 47 ohm 1 4W 5 4704019 R31 10 ohm 1 4W 5 4704011 R32 10 K 1 4W 5 4704068 R33 360 K 1 4W...

Page 97: ...C Socket 2100034 Z32 74LS93 Divide by 8 Binary Counter X33 24 Pin I e Socket 2100034 Selector Multiplexer 3102017 X39 40 Pin I C Socket 2100035 Z33 2 Kx 8 ROM A 450 ns 2 Patterns 3108011 X71 16 Pin I...

Page 98: ...STATE Hex Buffer 3102024 Z61 2102 AN 4L 1 K Static RAM 3108002 Z62 2102 AN 4L 1 KStatic RAM 3108002 Z63 2102 AN 4L 1 K Static RAM 3108002 Z64 74LS157 Quad 2 Line to 1 Line Data SelectoriMuItiplexer 31...

Page 99: ...1 4W 5 4704061 R9 330 ohm 1 4W 5 4704036 INTEGRATED CIRCUITS Zl Z2 Z3 Z4 74LS05 Hex Buffer with open col lector High Voltage outputs 74LS05 Hex Buffer with open col lector High Voltage outputs 74LS36...

Page 100: ...h m ti s 99...

Page 101: ...on the right side are connections in the Video Hori zontal and Vertical Sync generation areas The wire modifications to the left are changes in the Board to use the Intel EPROMs Whenever a Board uses...

Page 102: ...9 RAM sourced at 221 pin 7 23 not used To Pin 3 of 235 271 4K 1 14 0 0 r o o A6 0 0 7 8 To Pin 13 of all RAM s RAM 0 0 To Pin 15 r o o GND of 67 0 0 Version 0 Board ROM and RAM sourced at 23 as shown...

Page 103: ...a for ROM B The reason you need to know the differences between ROM A and ROM B is in trouble shooting Certain software troubleshooting aids may fail ROM A and pass ROM B You need to identify ROM A to...

Page 104: ...ced in either 233 s or 234 s socket Motorola 7800 Series ROMs Single Chip Set The last ROM supplied to the factory was a single Motorola ROM It may be packaged in either ceramic like a few of the Nati...

Page 105: ...t mount directly onto the CPU Board are used on Revision G Boards These revision letters are stamped on one side of the CPU Board Refer to Changes to the TRS 80 Schematic Diagram Figure 28 for the cha...

Page 106: ..._0_R_O_M_A_0_4 i V f 4 i A8 1 3 _t_ i __ A9 f Hl CS r I j j _t_ HH J CS 1 _0_ 1 t 1 1 1 m 1 1 07 16 t I 06 t 5 I 05 04 22 HH 1 A7 __ t t H t t i 11 A H i 11_ 3 AS tI H i I t j 4 A4 __ H i i t I 5 A3 1...

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Page 108: ...I I A7 vee 24 T T 2 A6 A8 23 3 A5 22 A9 4 A4 es 21 5 A3 es 20 6 A2 AIO 19 7 AI Z2 All 18 8 AO 17 9 16 01 10 02 06 15 03 05 14 GND ROM B 04 vee 241 I A7 2 A6 A8 23 A5 22 RI A9 4 7K 5 A4 es 21 A3 es 20...

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Page 110: ...Al0 7 Al Zl All 18 8 AO 08 17 c 9 16 10 01 07 15 02 06 03ROM A BOS 14 l GND 04 13 L 1 A7 vec 24 2 A6 23 A8 3 A5 A9 22 Rl 4 A4 21 _ 4 7K es 5 A3 es 20 r 6 A2 Z2 Al0 19 7 Al All 18 8 AO 08 17 9 16 01 RO...

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Page 112: ...C56 I L Revision D and after ROM 74LS011l R62 47K L JVV v _ _ 5v Is 14 13 qRJ Z3 I 4 I 1 74 b 6 M E Mc le 8 S j f I 74LSe0 I I I I I __ J I L _ J RD 13 RAM A Pins 5 and 4 of Z74 connect directly to si...

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Page 115: ...LI i30 74LS02 I I I I l O 2 3 t O 7 i r I I 7 1 L SPARE GAT l 2 4LS02 r J 1 I 13 BIT6 41 5 061 1 r II i 30 P _ __ il BIN L C I iH I 0 i A A r L 3 9 l6 0 17 4LS367 I 1 13 I r I L r t 1l61 r 7 _ o 5 1 l...

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