Radio Shack 26-3861 User Manual Download

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Summary of Contents for 26-3861

Page 1: ...Tandy 200 Technical Reference Manual 26 3861 ...

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Page 3: ...NISHED BY RADIO SHACK INCLUDING BUT NOT LIMITED TO ANY INTERRUPTION OF SERVICE LOSS OF BUSINESS OR ANTICIPATORY PROFITS OR CONSEQUENTIAL OAMAGES RESULTING FROM THE USE OR OPERATION OF THE EQUIPMENT OR SOFTWARE IN NO EVENT SHALL RADIO SHACK BE LIABLE FOR LOSS OF PROFITS OR ANY INDIRECT SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF ANY BREACH OF THIS WARRANTY OR IN ANY MANNER ARISING OUT OF OR CON...

Page 4: ...ss written permission from Tandy Corporation and or its licensor of any portion of this manual is prohibited While reasonable efforts have been taken in the preparation of this manual to assure its ac curacy Tandy Corporation assumes no liability resulting from any errors or omissions in this manual or from the use of the information contained herein Tandy and Radio Shack are registered trademarks...

Page 5: ...Serial Interface Circuit 2 20 LCD 2 30 Power Supply and Auto Power ON OFF Circuit 2 39 APPENDIX A INSTALLATIONS A 1 Installation of Operational RAMs and ROM A 1 Installation of Nickel Cadmium Batteries A 1 APPENDIX B KEYBOARD LAYOUT CONNECTOR PIN ASSIGNMENTS AND CHARACTER CODE TABLE B 1 Keyboard Layout B 1 Connector Pin Assignments B 2 Character Code Table B 7 APPENDIX C TECHNICAL INFORMATION C 1 ...

Page 6: ...Reader Interface Circuit 2 15 21 Buzzer Control Circuit 2 15 22 RP5C01 Internal Block Diagram 2 16 23 Flowchart for the TIMER IC 2 18 24 Functional Block Diagram of the Serial Interface 2 21 25 RS 232C MODEM Selection Circuit 2 23 26 RS 232C Interface Circuit 2 24 27 MODEM IC and Peripheral Circuit 2 25 28 Transmission Filter Circuit 2 26 29 Reception Filter Circuit 2 27 30 MODEM Connector Interfa...

Page 7: ...onal Block Diagram C 1 C 12 Pin Configuration of 82C51A C 20 C 13 Function Setting Sequence C 24 C 14 Bit Configuration of Mode Instruction Asynchronous C 25 C 15 Bit Configuration of Mode Instruction Synchronous C 26 C 16 Bit Configuration of Command C 27 C 17 Bit Configuration of Status Word C 28 C 18 Construction of LCD Panel C 29 C 19 Operation Theory of LCD Panel C 30 List of Tables TABLE PAG...

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Page 9: ...w 1 Keyboard Can be used like the standard typewriter However the Tandy 200 does have a few special keys See Appendix B of this manual for more details 2 LCD Unit The Tandy 200 display has sixteen lines that allows 40 characters on each line 3 POWER Switch Push this switch to turn the power ON or OFF To conserve the batteries the Tandy 200 automatically turns the power off if you do not use it for...

Page 10: ...Figure 1 Front View ...

Page 11: ... or transmit serial information When communicating directly with another Radio Shack computer a Null MODEM Adapter 26 1496 is required An 8 Cable Extender 26 T497 may also be required SYSTEM BUS Connector Connect this connector to the Disk Video Interface 26 3606 using the system bus cable PRINTER Connector For hard copy printouts of information attach any Radio Shack parallel printer to this conn...

Page 12: ...y 200 capabilities 3 Battery compartment When not connected to an AC power source the Tandy 200 gets its power from four AA size batteries that must be installed in this compartment If the Tandy 200 has the modification jumper module installed Bar Nickel Cadmium batteries the battery cover is fixed by a tapping screw and covered by a black sticker Internal View The Tandy 200 consists of four print...

Page 13: ...P Amp for Power Supply Figure 5 LCD PCB Standard RAMs 8 K byte x 3 xtal for Timer IC Timer IC Reserved through Holes for Modification Jumper Module IC Sockets for IC Socket for Optional ROM Memory Power Switch Optional RAMs Figure 6 Memory PCB 1 5 ...

Page 14: ...ries Batteries Four type AA Alkaline manganese batteries Operation time 7 days at two hours day Note Without I O units at normal temperature Memory protection battery on Main PCB Battery Rechargeable battery Back up time About 15 days 24 KB About 5 days 72 KB Recharge method Trickle charge by AC adapter or operation batteries LSIs CPU ROM RAM Dimensions Weight 80C85A Code and pin compatible with 8...

Page 15: ...tions Audio cassette interface Data Rate Printer interface Conforms to Centronics interface standards Handshake Signal TXR Transmit Data RXR Receive Data RTS Request to Send CTS Ciear to Send DSR Data Set Ready DTR Data Terminal Ready 6 7 or 8 bits NON EVEN ODD or IGNORE 1 or 2 bits 75 110 300 600 1200 2400 4800 9600 19200 BPS 5 meters 5 volts 3 5 volts 18 volts 3 volts 6 7 or 8 bits NON EVEN ODD ...

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Page 17: ...s section describes the theory of operation for the Tandy 200 Figure 7 shows how this section is organized and highlights significant areas I CO CJJ III ji til lis id 11 6 u 5_ HI So li r h Q J b I si i l si i i 91 1 ii j c I O s 2 1 ...

Page 18: ...rface 82C51AUSART This is the Universal Synchronous Asynchronous Receiver Transmitter which controls the serial interface such as the RS 232C and MODEM SLA5080FOU Gate Array This LSI consists of the large number of general purpose gates which are used for the I O addressing bank selection and other control circuits The input output for a cassette recorder and the interruption from the BCR for the ...

Page 19: ...J D DON TROLL Eft E 8 m 3 en 2 3 ...

Page 20: ...t in the SLA5080FOU is shown in Figure 9 AL E TNTA o H x D Q H h Figure 9 Functional Block Diagram of Bus Separation Circuit Memory The Tandy 200 uses a 32K byte ROM for the MSPLAN 40K byte ROM for BASIC and the other application programs and 24K byte static RAM to store the data and programs The 40K byte ROM consists of an 8K byte ROM M13 and 32K byte ROM M15 The 24K byte RAM consists of three 8K...

Page 21: ...QQDD RDM 9 NK JOKE 3EK 9 W J J FFF ADPP DFFF EGDQ 8HS_ RAM 8KB 24K_B 8KB 8KB JKB SAW AANK 5 JKB JK _ _2jlK_B _3KB STANDARD Figure 10 Memory Map 2 5 ...

Page 22: ...Si go 04 1 HC _L end vcc 29 m T AD Al A2 4 Al i A2 4 A3 S A4 Ab AS AT AB A9 A 10 An A12 4 A5 J AG 35 A7 Ijwr AID aii Nt nn N9 r nc S I mc a c Q2A 028 0 X Figure 11 Internal Wiring diagram of RAM package 2 6 ...

Page 23: ...cuit in the SLA5080FOU The latch AA0036 stores the bank selection data sent from the CPU with the Y5 and WR signal The decoder AA0038 is enabled by the memory address 0O00H to 9FFFH for ROMs and the decoder AA0037 is enabled by the memory address A00OH to FFFFH for RAMs JD M AJS A02 AD3 T O AAD03G ID 10 20 2ti 2D 3B 40 40 o f 4 4 fl BAHKfS A 0037 Figure 12 Bank Selection Circuit 2 7 ...

Page 24: ...024 with the IO M signal At the latch AA0063 the chip enable terminals G1 and G2 are connected to the ALE signal passing through the inverter because the AD0 AD7 signals are the multiplexed bus The I O map and I O port description are shown In Figure 14 The port assignment of the 81C55 is shown In Table 1 H 3 n O u Q Q JtQ Q Q ln a 0 CM a a SI o o a a n CM goo T3 Q ID a a I 3 2 8 ...

Page 25: ... a T 7 1 H o a o a o O u 0 a a K t z z Ul t ut a r H o o X t z 8 w t a o Ul w z o u X _JI in ui z t S o o o J JO 5 Q o 3 in z o H CO D z Ctun UJ i_ 5 CO IS V Ul si a _l U o t oo U O U O U O u o U O U O LLO n CD m j ua Ul Ulli u Figure 14 I O Map and I O Port Description 2 9 ...

Page 26: ...5 CD CD ti B Q s 1 1 1 Q 2 O O CD CD a CD CD CD CD CD CD 3 CZ Q CZ O O ti o m m 0 4 1 cr m to r CO CO CO 0 to j j j i CO eg X CO 3 a 3 CI LU g co Zl CL CL O o c c ZJ a c t3 Q co m CO CO CO CO 0 CO to rS o o E m 0 o O Q Q O Q Q D D LU CO D _l CL a k_ CD c cz cz cz cz c cz c cz S _r T3 J J CO CO EC t t L l w t h V h l 3 CO o LU o 5 o D D o 0 fl a 0 a a a a a Cu O Q CC CL CQ 2 Q _j CQ CQ CO O o o O O...

Page 27: ...o the CPU The STB K signal is generated in the SLA5080F0U when the CPU assigns EO EFH to the I O port address The CPU starts the key scan operation when the RST 7 5 interruption is accepted This interruption TP signal is generated about every 3 3 msec at M34 by dividing the CLK signal 2 4576 MHz Condition ol pressing T key is shown in Figure 15 I fl I a I fl i o_ a a a a Hf m u y c y Jj uij l _L 3...

Page 28: ...a cassette recorder AUX jack Figure 16 shows the write circuit of the cassette interface oo I SI OD PUI rLTLTLn Figure 16 Write Circuit of Cassette Interface Read Circuit The signal input from the earphone jack of the cassette recorder passes through the clamp circuit consisting of D1 and D2 and then is input to the comparator circuit consisting of M2 Finally the signal is converted into the digit...

Page 29: ...e 8 bit parallel data PA0 PA7 from 81C55 is sent to the printer Then by writing in data 1 into bit 1 of the output port specified by I O address EO EFH the PSTB signal is generated in the SLA5080FOU and sent to the printer As soon as the printer receives this PSTB signal the BUSY signal is changed to H indicating that the printer is busy The CPU then waits lor a while until this BUSY signal become...

Page 30: ... of the CPU When the bar code reader reads the first white part of the bar code a L level signal is generated then inverted by M1 As soon as RST 5 5 interruption occurs the CPU starts the data input operation passing through the PCS of the 81C55 As the bar code reader is moved across the bars H and L signals which correspond to white and black bars respectively are generated continuously and Inver...

Page 31: ... to sound the buzzer with the specified frequency by emitting a signal from the PB5 terminal of the 8iC55 and the other by using timer output TO and the BUZZER signal P82 of the 81C55 In addition the BELL signal also acts as the control signal of the DC DC converter circuit during the power up sequence refer to the Power Control Circuit BELL PB2 BUZZER Figure 21 Buzzer Control Circuit 2 15 ...

Page 32: ...the PBS is L How long the sound is heard depends on the second parameter of SOUND command in BASIC Clock Control Circuit A TIMER IC RP5C01 on the memory PCB is used in the clock control circuit so that the current time and alarm time can be set and read by the commands in BASIC To set and read the time the CPU assigns 90 9FH to the I O port address In addition because the back up power VB is suppl...

Page 33: ...S T _J o o LU o o s o o TestO Alarm Reset a X i Testi Timer Reset C J o X XX z UJ E IN O V X 1 ic CO a X X XX X X Z UJ Si E i 2 o a t en a One sec Counter Ten sec Counter One min Counter Ten min Counter One hour Counter Ten hours Counter Day Counter One day Counter Ten days Counter One month Counter Ten month Counter One year Counter Ten years Counter w tc m o S Test Register Reset Controller etc ...

Page 34: ... REGISTER TO fla L A3 2 A A d3 02 onto ftOrfft js_ 1 Q 1 Q X i 1 o ftfSFT THF TlUFfl _3_M aJ ArJ 01I02 dsIdo S WRITE THE CUfiflEMT TIME anG OaT 1 1 AZAI AD jo o jo f a 2 AL AC D3Jcjjpj VALUE U H ACH 3TEk START THF TJfciFR J jJ p I I li in I I In I PEAD The TIME ANO UA E AdAdAiJAfjl j D Dljoa a Jq o VALUE OF EACH time 3a mUd mo j Figure 23 Flowchart for the TIMER IC 2 18 ...

Page 35: ... TO Dl ff SFT TrtE ALApu PEG1 TER Id 3 L Hfj u WRITE THF ALARM TTME Mti DA 1 E A AH D3jDg pi Dq qj VALUE QF EACH ITEk kJAJA AtJ ENABLE T HE A AfiM QljTRljT l klU C f FNn J READ THE ALARW TJME ANQ DATE fiojwfil 2 D2 Dt DD JALUE DF EACH TiriE ALjA A i Ag Figure 23 Flowchart for the TIMER IC continued 2 19 ...

Page 36: ...diagram of the serial interface circuit In this figure the TO signal basic timing clock for the USART defines the transmission reception baud rate To transmit and receive the serial data from externa devices the RS232C signal selects either MODEM or RS 232C interface During the MODEM operation the ORGIS signal switches either the originate mode or answer mode for the MODEM IC The serial interface ...

Page 37: ...lj i 2 i S 3 pS f i 9 I J V7 2 IAW SI r i i a o z i f o Q D 4 1 U LI Vft t WMs r 1 Vh t L i _ g w o 1 y O 3 i I 5 8 1 n E IL 5 3 u o ini 5 s 1 3 a o V n o O J 2 J r iu a o j D S o u Q o a 3d Figure 24 Functional Block Diagram of the Serial Interface 2 21 ...

Page 38: ...is not used To make this condition pin 14 of M23 is connected to the ground During the MODEM mode the RTS signal is used as the self loopback signal and it is sent back to the CTS terminal The DSR signal is not used in the Tandy 200 USA version since the TD signal is always fixed to H level by the hardware The CD signal selects the CDD signal from the RXCAR terminal of the MODEM IC Because the CPU...

Page 39: ...by the inverters connected in parallel and then are output as RS 232C transmission signals In the RS 232C reception circuit the DSRR CTSR and RXR signals from the external RS 232C line are subjected to waveform shaping and inverted by M33 and then converted to 5V or ground level signals by the diodes The signals are then demultiplexed at M23 and converted to CTS DSR and RXD signals which are input...

Page 40: ...S s k I i I L A MW W in tt S Kf fe Kf fc V CO o Cl CVJ VJ a to w _ M 1 c m Q O 1 C I O CO fO CM N 5 2 s s Figure 26 RS 232C Interface Circuit 2 24 ...

Page 41: ...put to MODE input terminal and it switches between the originate mode or the answer mode This signal is output from the PB1 terminal of the 81C55 R7I I5M VDO TO TRANSMISSION FILTER CIRCUIT uuinr FROM RECEPTION FILTER CIRCUIT i RS 232C MODEM SELECTION CIRCUIT RESET MS MC 14412 Figure 27 MODEM IC and Peripheral Circuit Transmission Filter Circuit The DC component of the carrier output from the TXCAR...

Page 42: ...inal of MC14412 Also to check a carrier signal this signal is input to the demultiplexer M23 as the CDD signal in the RS 232C interface circuit Intermediate frequencies of the 3 stage active filter are shown below The switching of intermediate frequency for the originate and answer modes is accomplished by switching T1 T2 and T3 ON or OFF according to ORIG ANS parameter in TELCOM mode thus changin...

Page 43: ...ted to the secondary side of the driver transformer The primary side of this transformer is connected to the telephone line via the connector TXMD RXMD The ACP DIR switch is used in the MODEM mode relay RY2 separates the telephone receiver audio inut signal TL to prevent interference RY3 another relay separates the modem circuit and the telephone at the conclusion of use in the MODEM mode and is a...

Page 44: ...D li fe o J CD O Figure 30 MODEM Connector Interface Circuit 2 28 ...

Page 45: ...e SC TCM5089 The enable TNE signal input to this IC is created by NANDing the DTR signal and RS232C signal That is when the DTR signal becomes H during MODEM mode this IC will be in the enable state Then the CPU writes the data to be dialed to the I O port assigned by AOH AFH 1 CM 3ZX r i 10 i jfM im ftf u i iui f i y r im h or r m O S Si 8 g to n o L_ r j A O O Q Q O O O j rn in id n ro a Figure ...

Page 46: ... LCD Control Circuit of the Tandy 200 consists of the LCDC HD61830B and 8K byte RAM The LCDC generates driving signals for LCD by receiving the instructions and data from the CPU The driving signals for LCD are divided into two groups one is the timing signal for the segment driver and common driver another is the data to display The CLKL signal divided 2 4576 MHz clock signal by two at M34 is sup...

Page 47: ...o 5z z 3x3 idI inn Z 3 wo u uia a _ o 1 CO j ilLs a u n l a A o a Q iS ij o s o h 01 o M 3 ft o ft o O S u u u o J CD L a r Z u o g s 1 O UJ 3 Q O CD _ o 1 r t o 0 1 1 1 Z o J CK a m at 2jS a o a Z r I J C3 L 1 id 2 33V3M31NI 0 1 f t Figure 32 Internal Block Diagram of HD61830B 2 31 ...

Page 48: ... the periodic frequency of one screen display and determines 80 Hz for the Tandy 200 The MB signal is used for changing the driver signal to AC because the continuous application of DC to the LCD would shorten the LCD element life The CL1 signal is used for the shift clock of the internal shift register Figures 33 and 34 show the internal block diagram of HD61 103 and output waveform of HD61103 2 ...

Page 49: ...Figure 33 Internal Block Diagram of HD61103 2 33 ...

Page 50: ...Figure 34 Output Waveform of HD61103 2 34 ...

Page 51: ...ta are output The CL2 signal is used for the shift clock of the display data The MB signal changes output signals to AC The D1 signal is the data to display on the upper half of the LCD screen and the D2 signal is the data to display on the lower half of the LCD screen Figures 35 and 36 show the internal block diagram of HD61 100 and output waveform of HD61100 VILV2LV3LV Y1Y2 Yen VmVwVwVm M MB DL ...

Page 52: ...n n Figure 36 Output Waveform of HD61100 2 36 ...

Page 53: ...The maximum voltage applied to the common electrode and segment electrode is the potential difference between V1 and V2 In addition a is the bias coefficient which determines from the standpoint of contrast the maximum ratio between the illumination voltage and the non illumination voltage When that ratio is greatest in relation to the effective ON and OFF voltages a 9 0 Thus for V1 V2 V3 V4 V5 an...

Page 54: ...VI V2 1J VE V5 COMMON LINE V3 V3 V V NON ILLUMINATION SEGMENT LINE ILLUMINATION SEGMENT LINE Figure 37 Driving Waveform of LCD 2 39 ...

Page 55: ...used for the input voltage to the DC DC converter circuit When the internal circuit is modified for use of Nickel Cadmium batteries VIN is supplied to the four Nickel Cadmium batteries installed into the battery compartment This power source charges the Nickel Cadmium batteries whenever an AC adapter is connected to the Tandy 200 Power Distribution Figure 38 shows the power distribution of the Tan...

Page 56: ...Figure 38 Power Distribution 2 40 ...

Page 57: ...d at the base coil Then when the base potential progresses to a half cycle of the oscillation voltage it is biased in the forward direction T20 and T21 are switched ON once again In this way AC voltage corresponding to the number of windings is generated at the secondary side of the converter and this voltage is rectified and smoothed by D13 D14 D15 C62 C63 and C64 Low Power Detection Circuit The ...

Page 58: ...Figure 39 DC DC Converter and Low Power Detection Circuit 2 42 ...

Page 59: ...e same time the LPS signal becomes H and is sent to the TRAP terminal of the CPU after inverted at M35 g When VDD reaches a constant DC level to operate the CPU T28 is switched on and T29 is switched off The RESET signal becomes H then the CPU begins the Warm Start process After completion of the Warm Start the CPU drops the BELL signal h The output pin 10 of the gate M24 becomes H and the output ...

Page 60: ... signal if the automatic Power Off limit reaches the value corresponding with the 1st parameter of the POWER command in BASIC The remaining sequence follows the Power Down using the POWER switch Reset Circuit This circuit supplies the CPU RESET signal and also the RAMRST signal as the RAM protecting signal when the power decreases R113 and C66 delay the introduction of input power so that T28 is s...

Page 61: ...Figure 40 Power Control and Reset Circuit 2 45 ...

Page 62: ... CA J i i l a s n M x X ET LU CM E 10 CM to VJ L _ t V o O o o C J W CM 1 i Figure 41 Power Up Down Sequence 2 46 ...

Page 63: ...M 2 Insert the optional ROM into the IC socket marked M308 Installation of Nickel Cadmium Batteries Remove the memory PCB Refer to Section II Disassembly Instruction Install the modification jumpers into the through holes marked J301 and J302 Re assemble the unit IC Socket for Optional RAM 2 _ is stsN i wt fws m2 w SN s I C3CM 4 1 7 777777 OPTION Rv j 7 S f r i o rsc Rv1M 1 M302 _ V ii IC Socket f...

Page 64: ... Cadmium batteries into the battery compartment Drill the screw hole on the battery cover using the tapping screw and secure the battery cover and bottom case Stick the red iabel on the battery cover Figure A 2 Installation of Nickei Cadmium Batteries A 2 ...

Page 65: ...D CHARACTER CODE TABLE Keyboard Layout f r I I a A HZ D r C T 1 j 1 r ESC 12 3 4 At J 5 s tg U 91 1 1 DEL 8KSP TAB W E R T Y U n l B B P ENTEER CTRL A s D G H J K H L B CAPS LOCK SHIFT Z X C v e n m f J SHIFT GRPH CODE NtJM J Figure B 1 Keyboard Layout B 1 ...

Page 66: ...dress Address Address and data and data and date and dala and data and data and data and data signal bit signal bit signal bit signal bit signal bit signal bit signal bit signal bit signal bitO signal bit 1 signal bit 2 signal bit 3 signal bit 4 signal bit 5 signal bit 6 signal bit 7 8 9 10 11 12 13 14 15 Read enable signal Write enable signal I O or memory select signal Status signal Address latc...

Page 67: ... RS 232C Interface Pin No Symbol Description 1 GND 2 TXR Transmit Data 3 RXR Receive Data 4 RTS Request to send 5 CTS Clear to send 6 OSR Data set ready 7 GND 8 CD Carrier detect 9 NC 10 NC 11 NC ia NC 13 NC 14 NC 15 NC 16 NC 17 NC 18 NC 19 NC 20 DTR Data terminal ready 21 NC 22 NC 23 NC 24 NC 25 NC Table B 2 RS 232C Connector Pin Assignments B 3 ...

Page 68: ...t Data 4 GND 5 PD1 Bit 1 of Print Data 6 GND 7 PD2 Bit 2 of Print Data a GND 9 PD3 Bit 3 of Print Data 10 GND 11 PD4 Bit 4 of Print Data 12 GND 13 PD5 Bit 5 of Print Data 14 GND 15 PD6 Bit 6 of Print Data 16 GND 17 PD7 Sit 7 of Print Data 18 GND 19 NC 20 GND 21 BUSY Busy signa for Computer 22 GND 23 NC 24 GND 25 BUSY Select signal 26 NC Table B 3 Printer Connector Pin Assignments B 4 ...

Page 69: ...HHS 25 23 21 19 17 15 13 11 9 7 5 3 1 26 24 22 20 18 16 14 12 10 8 6 4 2 HHBHHHHHHEBHH Figure B 4 Printer Connector Cassette Interface Figure B 5 Cassette Connector MODEM Interface Figure B 6 MODEM Connector B 5 ...

Page 70: ...ode Reader Interface Ptn No Symbol Description 1 NC 2 R x DB Receive data from bar code reader 3 NC 4 NC 5 NC 6 NC 7 GND 8 NC 9 VDD 1 2 3 4 S O G O O O O O O 6 7 8 9 Figure B 7 Bar Code Reader Connector B 6 ...

Page 71: ...01 0010 jCTBt R 19 13 OOO 10011 S 20 14 0O01010O c T 21 15 00010101 c U 22 IB 0O01O110 V 23 17 00010111 W 24 IS 00011000 B Decimal Hn Binary Dilplayid CiiBricter Keyboard Character 26 19 00011001 Y 26 tA 00011010 pjT z 27 te 00011011 28 1C 00011100 29 ID 00011101 B 30 IE 00011110 t 31 IF 00011111 t 20 00100000 32 p CI i 33 21 00100001 1 34 22 001 OOO 10 II 35 23 001 OOO 11 ft 36 24 00100100 37 26 ...

Page 72: ...E 70 46 010O011O F F 71 47 010001 11 G G n 48 01001000 H H 73 49 01001001 I I 4A 01001010 Decimal Max Binary Display Character Keyboard Character 75 4B 01001011 K K 76 4C 010O110O L L 77 40 O1OO1101 M M 78 4F 01001110 N N 79 4F 01001111 60 50 0101DO00 P P 81 51 01010001 Q O 82 52 01010010 R R S3 53 01010011 S S 84 54 01010100 T T 85 55 01010101 U tl 86 56 01010110 y V 87 57 01010111 u VI 88 SB 010...

Page 73: ...19 77 01110111 w w 120 7B 01111000 X X 121 79 01111001 y y 122 7A O111101O z 123 7B 01111011 s 124 7C 01111100 1 1 Decimal Hai Binary Diiplayed Cheractar Keyboard Character 12b 70 01111101 126 7E 01111110 V i 127 7F 01111111 S 128 80 100O0O0O 8 p 129 81 10O0O001 a 130 62 10O0O01O 131 83 1O0O0O1 1 132 84 1OOOO10O Q 133 85 100001 01 ft a 134 86 10ODO11O Q h 136 67 10000111 a 1 136 38 10001000 Tt B 1...

Page 74: ...3 1O1O10O0 10101001 10101010 1 B 171 AB 10101011 13 y 17 AC 10101 100 K p 173 AO 1010110 K 174 AE 10101110 Decimal Hen Binary Ditplayad Character KeybodrtJ Character 175 AF 1 01 01 1 1 n 176 BO 10110000 177 B1 10110001 Q 178 B2 10110010 B 179 83 10110011 u 180 B4 10110100 e 181 B5 10110101 Y 182 B6 10110110 a 1 183 B7 10110111 6 184 B8 B9 1 01 1 1 ooo u fatij U 185 10111001 S 186 BA 101 11010 T m ...

Page 75: ... A 217 09 11011001 1 B K 21B DA 11011010 6 B L DB DC B B 221 DD 11011101 s M 222 D 11011110 fe B c 223 DF 11011111 B z 224 Ef t 1 1 00000 B z Decimal rtax Binary Displayed Character Kayboard Character 226 El 111OO001 I B 220 E2 1 1 1 0001 B 227 E3 11100011 I B 235 237 E4 5 EB IllOtOOO E9 11101001 EA 11101010 EB EC ED 11101101 1 B 230 EG 11100110 B 231 E7 11100111 B e I B s B D 23B EE 11101110 J B ...

Page 76: ...Binary Jtplav d K ytoirri Character Chwactw 250 FA 11 11010 B K 251 FB 1 1 1 1 or i r H 252 FC ntnoo A T 253 FD 1111101 a a 254 FF 1111110 k 255 FF mini m c B 12 ...

Page 77: ...ed in silicon gate C MOS technology and compatible with 8085A It is designed with same processing speed and lower power consumption compared with 8085A thereby offering a high level of system integration The 80C85A uses a multiplexed address data bus The address is split betweer the 8 bit address bus and the 8 bit data bus C 1 ...

Page 78: ... o lTi e2 fit d LiZ a a z C3 o v 4 k Figure C 1 Functional Block Diagram C 2 ...

Page 79: ...ine cycle It then becomes the data bus during the second and third clock cycles ALE Output Address Latch Enable It occurs during the first clock state of a machine cycle and enables the address to get latched into the on chip latch of peripherals The falling edge of ALE is set to guarantee setup and hold times for the address information The falling edge of ALE can also be used to strobe the statu...

Page 80: ...CPU has received the HOLD request and that it will relinquish the bus in the next dock cycle HLDA goes low after the Hold request is removed The CPU takes the bus one half clock cycle after HLDA goes low INTR Input INTERRUPT REQUEST Is used as a general purpose interrupt tt is sampled only during the next to the last clock cycle of an instruction and during Hold and Halt states If it is active t h...

Page 81: ...t Can be used as a system reset The signal is synchronized to the processor clock and lasts an integral number of clock periods Xi X2 Input Xi and X2 are connected to a crystal to drive the internal clock generator X can also be an external clock input from a logic gate The input frequency is divided by 2 to give the processor s internal operating frequency CLK Output Clock Output for use as a sys...

Page 82: ...O O CO c tr a X X X C o K o C 5 0 t X X x X f O o CD t J O CO eg CD U S 05 f X3 5 o i C i CO in l_ Q e 0 in in in r CO 1 in t rr co w K rr tx r cn a a s o J f O 0 Q I C g 5 u o o u o sz r u c rn u X3 O C a i 0 nC o I T3 m d Tl r X ci o D n 1_ T a a JJ g en w u Cfl w c m 0 J o o i a TO CL CO CD CD o z Table C 1 Interrupt Priority Restart Address and Sensitivity C 6 ...

Page 83: ...dition to these features 80C85A has three maskable vector interrupt pins and one nonmaskable TRAP interrupt Interrupt and Serial I O The 80C85A has 5 interrupt inputs INTR RST 5 5 RST 6 5 RST 7 5 and TRAP INTR is identical in function to the 8080A INT Each of the three RESTART inputs 5 5 6 5 and 7 5 has a programmable mask TRAP is also a RESTART interrupt but it is nonmaskable The three maskable i...

Page 84: ...due to noise or logic glitches Figure C 3 illustrates the TRAP interrupt request circuitry within the 80C85A Note that the servicing of any interrupt TRAP RST 7 5 RST 6 5 RST 5 5 INTR disables all future interrupts except TRAPs until an El instruction is executed The TRAP interrupt is special in that it disables interrupts but preserves the previous interrupt enable status Performing the first RIM...

Page 85: ...ed by the status of the three status lines IO M Si So and the three control signals RD WR and INTA See Table C 2 The status line can be used as advanced controls for device selection for example since they become active at the Ti state at the outset of each machine cycle Control lines RD and WR become active later at the time when the transfer of data is to take place so are used as command tines ...

Page 86: ...Ice o o o CO o o O 1 O to o o O 12 g o o o _ o O c c o 0 o o U D XJ O O o 5 0 D ec o E 0 2 0 o E CD 2 O a CD oc O o S o z DC l z o 0 TJ CD o c J o Bus idle Bl DAD ACK OF RST TRAP HALT Table C 2 80C85A Machine Cycle Chart C 10 ...

Page 87: ... co i CO i X X X X X X X co CO is X X X X o o co to CO to CO X X X X X o X CD co CD C xz u a H 1 h H 1 H 4 1 1 CO w u 1 t X t a o X 1 o to T3 CD Q c o o c Q Q w 0 u o U E o J nj o c o V a co c M T3 l CD t 2 en o E c P 3 CJ CJ o o x o z y I II O i w o CD d in c 8 X Table C 3 80C85A Machine State Chart C 11 ...

Page 88: ... IS o uJ r U _l U p a i ls i i Figure C 4 80C85A Basic System Timing C 12 ...

Page 89: ...l I O consists of two 8 bit ports and one 6 bit port both general purpose The MSM81C55RS GS also contains a 14 bit programmable counter timer which may be used for sequence wave generation or terminal countpulsing I0 M ADo 7 ZZ CE ALE RD WR RESET A 256x8 STATIC RAM B PORT A TIMER TIMER CLK TIMER 0UT POR1 C PBo 7 PORT C Vcc 5 V GND OV Figure C 5 Functional Block Diagram pcs T pc E Ha TIMER INE RESE...

Page 90: ...ry RD Input If this pin in low data from either the memory or ports is read onto the ADo 7 lines depending on the state of the IO M line WR Input If this pin is low data on lines ADo 7 is written intoeither the memory or into the selected port depending on the state of the IO M line PAo 7 PBo 7 Input Output General purpose I O pins Input output directions can be determined by programming the comma...

Page 91: ...ata Bus X Com mand Status PC 6 bits I Z PA Timer MSB Timer LS8 Boits a bits Figure C 7 Internal Register of 81 C55 A6 i O Address Selecting Register AT AS A4 A3 A2 A1 AO X X X X X internal command status register X X X X X 1 Universal i O port A PA X X X X X 1 Universal I O port B PB X X X X X 1 1 I O port C PC X X X X X 1 Timer count lower position S bits LS6 X X X X X 1 1 Timer count upoer posit...

Page 92: ...timer if it is running NOP if Hie timer is not running 10 STOP AFTER TC Stops the timer when li reaches TC NOP it Ihe timer is not running 11 START If the timer is not running loads the mode and the count length and immediately starts timer operation it the timer is run ning loads a new mode and the count length and starts timer operation imme diately after TC is reached Figure C 8 Programming the...

Page 93: ...ode I O address of the PA register xxxxxOOl I O address of the PB register xxxxxCMO 4 PC Register The PC register may be used as an input port output port or control register depending on the programmed contents of the C S register The I O address of the PC register is xxxxxO1 1 5 Timer The timer is a 14 bit counter which counts TIMER IN pulses The low order byte of the timer register has an I O a...

Page 94: ... the second period of four Note 2 if an internal counter of the 81C55 receives a reset signal count operation stops but the counter is not set to a specific initial value or output mode When restarting count operation after reset the START command must be executed again through the C S register 6 Standby Mode __ The 81C55 is placed in standby mode when the high level at CE input is latched during ...

Page 95: ... CPU after conversion Thus the device is used for serial data communication 82C51A configures a fully static circuit using silicon gate CMOS technology Therefore it operates on an extremely low power supply at 100 A max of standby current by suspending all the operations 82C51A is functionally compatible with 8251 A D7 a DATA A K BUS BUFFER j 1 RESET Cl K CD RD WR CS Dsr DTR CTS n READ WRITE CONTR...

Page 96: ...et status The device waits for the writing of mode instruction The min reset width is six clock inputs during the operating status of CLK CLK Input CLK signal is used to generate an internal device timing CLK signal is independent of RXC or TXC However the frequency of CLK must be greater than 30 times the RXC and TXC at Synchronous mode and Asynchronous x1 mode and must be greater than 5 times at...

Page 97: ...and Note TXRDY of status word indicates that transmit data character is receivable regardless of CTS or command If CPU write a data character TXRDY will be reset by the leading edge or WR signal TXEMPTY Output This is an output terminal which indicates that 82C51A transmitted all the characters and had no data character In synchronous mode the terminal is at high level if transmit data characters ...

Page 98: ... at high level if sync characters are received and synchronized If status word is read the terminal will be reset In external synchronous mode this is an input terminal If High on this input forces 82C51A starts receiving data character In asynchronous mode this is an output terminal which generates high level output upon the detection of break character if receiver data contained low level space ...

Page 99: ...state X 1 1 Data bus 3 state 1 1 Status CPU 1 1 Control word CPU 1 Data CPU 1 Data CPU Table C 6 Operation between 82C51A and CPU It is necessary to execute a function setting sequence after resetting on 82C51A Figure C 13 shows the function setting sequence If the function was set the device is ready to receive a command thus enabling the transfer of data by setting a necessary command reading a ...

Page 100: ...et or externa reset That is the writing of control word after resetting will be recognized as mode instruction Items to be set by mode instruction are as follows Synchronous Asynchronous mode Character hronous mode Character length Parity bit Baud rate factor asynchronous mode Internal external synchronization synchronous mode No of synchronous characters synchronous mode The bit configuration of ...

Page 101: ...Fifl C 16 tK 16x Six Character length 1 1 1 1 5 bits a bits 7 bits 8 bits arity check 1 i j 1 1 1 Disable Odd parity Disable Even panty Stop bit length 1 t 1 1 f Inhibit 1 bit 1 S bits 2 bits Figure C 14 Bit Configuration of Mode Instruction Asynchronous C 25 ...

Page 102: ...t Configuration of Mode Instruction Synchronous 2 Command Command is used for setting the operation of 82C51A It is possible to write a command whenever necessary after writing mode instruction and sync characters Items to be set by command are as follows Transmit Enable Disable Receive Enable Disable DTR RTS Output of data Resetting of error flag Sending of break characters Interna resetting Hunt...

Page 103: ... break character Normal operation t Reset error flag 0 rr IMorrfiaJ operation RTS 1 RTS 0 RT 1 1 Infernal reset Normal operation Nata Search mode for aynchronoirs characters jn synchronous mode 1 Hunt mode Note Q formal operation Figure C 16 Bit Configuration ol Command C 27 ...

Page 104: ... asyn chronous mode Stop bu cannot be detected Figure C 17 Bit Configuration of Status Word Standby Status It is possible to put 82C51A in standby status for the complete static configuration of CMOS When the following conditions have been satisfied that 82C51A is in standby status CS terminal shall be fixed at VCC level _ Input pins other than CS DO to D7 RD WR and C D shall be fixed at VCC or GN...

Page 105: ... an electric shutter that controls the passage of light If voltage is applied the transmission of light is blocked otherwise light is allowed to pass so that letters and numbers can be displayed Figure C 19 demonstrates how the LCD operates The liquid crystal display element is sandwiched between the two polarization plates The polarized axes of the upper and lower plates are placed at right angle...

Page 106: ... Light b Voltage is app e W Front Polarizer Front Glass Electrode Twisted 90 L j wfom J Rear Glass Electrode Rear Polarizer Reflector mm YON Light is passed Bright Light is interrupted Dark Figure C 19 Operation Theory of LCD Panel C 30 ...

Page 107: ...e BLOCK DIAGRAM ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Unit Terminal Voltage Vl 0 5 to 7 0 V Power Dissipation Pr 1 0 W Operating Temperature Topr to 70 C l tn r iturc j 55 to 125 C Storage Temperature Under Bias 7 ias 10 to 85 c 0 FP 28 PIN ARRANGEMENT nc T 28 fee A d 27 WE A 7 26 CS a 7 25 A A T mJa A I 1E a ii A T 22 5E A f 2l A10 A 7 2 CS a To 19 l 0 i o TT 71 I O i o n TJ i o i o n IS i ...

Page 108: ...Input Output Capacitance Q o Vno 0V pF Note This parameter is sampled and not 100 tested AC CHARACTERISTICS Vcc 5V 10 Ta to 70 C AC TEST CONDITIONS Input Pulse Levels 0 8 to 2 4V Input Rise and Fall Times 10ns Input and Output Timing Reference Level 1 5V Output Load 1TTL Gate and C _ 100pF including scope and jig READ CYCLE Item Symbol HM6264LFP 12 HM6264LFP 15 min max min max Rejdi i lr lime RC 1...

Page 109: ...le Time wc 120 150 ns Chip Selection to End of Write cw 85 100 ns Address Setup Time AS ns Address Valid to End of Write aw 85 100 ns Write Pulse Width wp 70 90 ns Write Recovery Time CST WE WRI 5 10 ns CS2 WR2 15 15 ns Write to Output in High Z WHZ 40 50 ns Data to Write Time Overlap dw 50 60 ns Data Hold from Write Time dh ns OE to Output in High Z OHZ 0 40 50 ns Output Active from End of Write ...

Page 110: ...oing high to the end of write 3 AS s measured from the address valid to the beginning of write 4 t wr is measured from the end of writejo thejiddress change t WRi applies in case a write ends at CSI or WE going high wr 2 aPPfie s in case a write ends at CS2 going low 5 During this period I O pins are in the output state therefore the input signals of opposite phase to the outputs must not be appli...

Page 111: ... IRC m VIL min 0 3V 20jiA max at ra 0 40 C RC Read Cycle Time LOW Vcc DATA RETENTION WAVEFORM 11 CS1 ControlM Data Retention Mode CSl fcc 0 2V 0V LOW Vcc DATA RETENTION WAVEFORM 2 CS2 Controlladl Data Retention Mode CS2 0 2V NOTE In Data Retention Mode CS2 controls the Address WE CSl OE and Din buffer If CS2 controls data retention mode Vin for these inputs can be in the high impedance state If CS...

Page 112: ......

Page 113: ...2764 BLOCK DIAGRAM PIN ARRANGEMENT ABSOLUTE MAXIMUM RATINGS Item Symbol Rating Unit Terminal Voltage VT 0 5 to 7 0 V Power Dissipation Ft 1 0 W Operating Temperature 7opr to 70 C Storage Temperature T t 55 to 125 C Storage Temperature Under Bias Tbits 10 to 85 C nc T A n A T A T A T A A 7 A T A a T5 i o n i o u i o n gnd h 28 I CC 13 WE 26JCS 25 A 24 A 23 A 22 OE 2l A1 m cs 19 1 0 Ta no n i o6 16 ...

Page 114: ...d from the address valid to the beginning of write 4 twR s measured from the end of write to the address change ty m applies in case a write ends at CS1 or WE going high twR2 applies in case a write ends at CS2 going low 5 During this period I O pins are in the output state therefore the input signals of opposite phase to the outputs must not be applied _____ 6 If CS1 goes low simultaneously with ...

Page 115: ... pF Note This parameter is sampled and not 100 tested AC CHARACTERISTICS Vcc 5V 10 Ta to 70 CI AC TEST CONDITIONS Input Pulse Levels 0 8 to 2 4V Input Rise and Fall Times 10ns Input and Output Timing Reference Level 1 5V Output Load 1TTL Gate and CL 100pF including scope and jig READ CYCLE Symbol HM6264LP 10 HM6264LP 12 HM6264LP 15 Unit min max min max min max Read Cycle Time IRC 100 120 150 ns Ad...

Page 116: ...s Chip Selection to End of Write lew 80 85 100 ns Address Setup Time IAS ns Address Valid to End of Write IAW 80 85 100 ns Write Pulse Width twp 60 70 90 ns Write Recovery Time CS1 WE IWR1 5 5 10 ns CS2 tWR2 15 15 15 ns Write to Output in High Z tWHZ 35 40 50 ns Data to Write Time Overlap IDW 40 50 60 ns Data Hold from Write Time IDH ns OE to Output in High Z tOHZ 35 40 50 ns Output Active from En...

Page 117: ...r CS2 going high to the end of write 3 t AS is measured from the address valid to the beginning of write 4 twR is measured from the end of writejo the address change l WRl applies in case a write ends at CSl or WE going high f u r 2 applies in case a write ends at CS2 going low 5 During this period I O pins are in the output state therefore the input signals of opposite phase to the outputs must n...

Page 118: ... lR rc ns VIL min 0 3V 20 A max at ra 0 40 C RC Rea Cycle Time LOW Vcc DATA RETENTION WAVEFORM 1 CS1 Controlled Data Retention Mode CS12CCC 0 2V LOW Vcc DATA RETENTION WAVEFORM 2 CS2 Controlled Data Retention Mode CS2 i 0 2V NOTE In Data Retention Mode CS2 controls the Address WE C5I OEand Din buffer If CS2 controls data retention mode Vta for these inputs can be in the high impedance state If CS1...

Page 119: ...ge Vcc V Vcc 5 0 V Ambient Temperature Ta C SUPPLY CURRENT vi FREQUENCY ACCESS TIME vi LOAD CAPACITANCE 200ni 150n I20n lOOn Ta 25 C VCC M1N Frequency MHz Load Capacitance C pF ACCESS TIME v SUPPLY VOLTAGE Tfl 25 C ACCESS TIME vs AMBIENT TEMPERATURE Vcc 5 0 V Supply Voltage Vcc V Ambient Temperature T C C 43 ...

Page 120: ...ltafe Vcc V Supply Voltage Vcc V OUTPUT CURRENT vs OUTPUT VOLTAGE OUTPUT CURRENT vs OUTPUT VOLTAGE Vce 5V Output High Voltage VOH V Output Low Voltage VOL V STANDBY CURRENT vs AMBIENT TEMPERATURE STANDBY CURRENT vs SUPPLY VOLTAGE 5 E S B i TD 25 C Ambient Temperature Ta C Supply Voltage Vcc V C 44 ...

Page 121: ...Maximum Access Time 250ns Low Power Standby and Low Power Operation Standby 5 iW typ Operation 50mW typ Pin Compatible with EPROM BLOCK DIAGRAM PIN ARRANGEMENT HN613286P AO Al A2 A3 A4 AS A6 Address A Decoder A8 A9 A10 All A12 A13 A14 CS Memory Matrix 3 State Output Buffer DS D6 Active level defined by the user ABSOLUTE MAXIMUM RATINGS Item Symbol Value Unit Supply Voltage Vcc 0 3 to 7 0 V Input V...

Page 122: ...tput High Level Leakage Current hoH CE 0 8V CF 2 4V V 2 4V 5 Mk Output Low Level Leakage Current h L v o v 5 Mk Supply Current In stand by h SS fc iV Vec 5 5V 1 30 pk In operation 7cc art 3 0 1 5 3 0 mA Input Capacitance C 10 pF Output Capacitance C 12 5 pF Steady Ute c Vcc 5V r 25X AC OPERATING CONDITION AND CHARACTERISTICS READ SEQUENCE VCC 5V 10 Vss 0V 7a 0 f 75 C i 20ns Item Symbol min max Uni...

Page 123: ...0 75 C t t 20ns Item Symbol min max Unit Read Cycle Time tRC 200 ns Address Access Time tAA 200 ns Chip Select Access Time IACS 200 ns Chip Selection to Output in Low Z tCLZ 10 ns Output Enable to Output Valid tOE 100 ns Output Enable to Output in Low Z IOLZ 10 ns Chip Deselection to Output in High Z ICHZ 100 ns Chip Disable to Output in High Z OHZ 100 ns Output Hold from Address Change IOH 10 ns ...

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Page 125: ...elect and Output Enable TTL Compatible Maximum Access Time 250ns Low Power Standby and Low Power Operation Standby OfiW typ Operation 50mW typ Pin Compatible with EPROM BLOCK DIAGRAM Manor Matrja 191 JSlata Buff 3 B D Active lt t definad by the a a ABSOLUTE MAXIMUM RATINGS with respect to Vgg RECOMMENDED DC OPERATING CONDITIONS Item Symbol Value Unit Supply Voltage Vcc 0 3 to 7 0 V Input Voltage K...

Page 126: ...dy state current Vcc 5V Ta 25 C RECOMMENDED AC OPERATING CONDITIONS READ SEQUENCE Vcc 5V 10 Vss OV To 20 to 75 C 20ns Item Symbol min max Unit Read Cycle Time rc 250 ns Address Access Time Ua 250 ns Chip Select Access Time lACS 250 ns Chip Selection to Output in Low Z CLZ 10 ns Output Enable to Output Valid OE 100 ns Output Enable to Output in Low Z OLZ 10 ns Chip Deselection to Output in High Z C...

Page 127: ...0 600 bps Post Detection Filter TTL or CMOS Compatible Inputs and Outputs CMOS LSI LOW POWER COMPLEMENTARY MOS UNIVERSAL LOW SPEED 0 600 bps MODEM Jfp jflP L SUFFIX CERAMIC PACKAGE CASE 620 P SUFFIX PLASTIC PACKAGE CASE 648 ORDERING INFORMATION MC144XX ___ S t x Denotes h L Ceramic Package L P F Plastic Package 4 75 to 15 Vdc V 4 75 to 6 0 Vdc BLOCK DIAGRAM USS Enable J Transmit p Data Mode 10O TT...

Page 128: ... 40 1 6 Vql 0 5 lOL 10 53 45 10 36 mA Vql 1 6 15 15 13 35 10 Input Current iPm 15 Vdd l tn 0 00001 0 l A Input Pull Up Resistor Source Current Pin15 V SS Vm 2 4 Vdc Pins 1 2 5 6 10 11 Ip 5 285 250 460 205 P A 12 13 14 Input Capacitance C tn 50 pF Total Supply Current 5 45 1 1 40 35 IPm 15 Vdo it 10 15 __ 13 27 40 80 12 25 11 23 mA Modulator Demodulator Frequency Accuracy ACC 5to 15 05 Excluding Cr...

Page 129: ...format to the modulator for conversion to FSK signals for transmission over the telephone network The modulator output is buf fered amplified before driving the 600 ohm telephone line The FSK signal from the remote modem is received via the telephone line and filtered to remove extraneous signals such as the local Transmit Carrier This filtering can be either a bandpass which passes only the desir...

Page 130: ...can be obtained from the following Motorola publica tions AN 731 Low speed Modem Fundamentals AN 747 Low speed Modem System Design Using the MC6860 8 49 Application Performance ol the MC6860 MODEM FIGURE 2 MC14412 INPUT OUTPUT SIGNALS CRYSTAL SPECIFICATION Crystal Mode Parallel Frequency 1 MHz 0 1 RS 540Q typ C 7 pF typ Temperature Range 40 C io Test Level 1 mW Suggested Crystal Suppliers Tyco CTS...

Page 131: ...MOS or TTL compatible logic level input see TTL pull up disable at a duty cycle of 50 2 that is a square wave resulting from a signal limner RECEIVE DATA RATE Rx Rate Pin 6 The demodulator has been optimized for signal to noise performance at 300 and 600 bps Data Rate Rx Rate O 30Obps 0 600 bps 1 0 SELF TEST 1ST Pin 2 When a high level ST 1 I is placed on this input the demodulator is switched to ...

Page 132: ...MC14412 FIGURE 4 TRANSMIT CARRIER SINEWAVE Rj iCCk V DD bV T Ca l FIGURE 5 TYPICAL TRANSMIT CARRIER FREQUENCY SPECTRUM C 56 ...

Page 133: ...ackup It can therefore be used as a non volatile RAM cs QT vcc W cs T 1 OSCOUT ADJ T O OSCIN A0 T ai QT A2 W o o U ALARM IJ D2 A3 E g DI RD H 11 DO GND E H WR Features Direct connection to CPU 4 bit bidirectional bus D0 D3 4 bit address inputs A0 A3 Internal counters for time hours min sec and date 100 years leap years months days and days of the week Choice of 24 hour or 12 hour AM PM system All ...

Page 134: ...Terminal connection diagram Block diagram 1Hz 16Hz OSCIN OSCOUT C 58 ...

Page 135: ... 2 5 5 V fXT Oscillation frequency of crystal oscillator 32 768 kHz DC electrical characteristics Ta 0 70 C Vcc 5V 10 unless otherwise specified Symbol I tern Measurement conditions Values Min TYP Max Units VI H input voltage 2 0 Vcc V VI L input voltage 0 3 0 8 V VOH H output voltage IOH 400jiA 2 4 J V vol L output voltage IOL 2mA 0 4 V H Input current VI 0 5 5V 10 MA ioz Output leakage current _...

Page 136: ...ata delay time after Wft trailing edge TYP Data hold time after WR leasing edge J Max 20 AC electrical characteristics are as follows when Vcc 5v 10 Measuremen conrii t ions Symbol tAC Addresr RD WR delay time RD WR pulse width Address val id time af ter d WR leading edge tfto Data delay time after WU trail ing edge Da ta hold time atter RD lead i ng edge tRDH tWDL Da ta delay time atter WR trail ...

Page 137: ... ADJ is set to high when the second counter registers 30 59 t the seconds are set to and the minutes are incremented This ter minal is designed not for edge detection but for level detection A tnin imuin of 100 j sec is required for high level adjustments Address terminals Connected to address bus of CPU I O control terminal is read by CPU V Low when RP5C01 I O control terminal Low when P5CQI is w...

Page 138: ...J x X X El 1 year coun ter C 1 0 year counter MODE ftegi ster Timer EN Al arm EN MODE sel eetor M l MO E Test Register RESET Controller i Test 3 Test 2 Te s t 1 Tinier RESET Tes t F 1Hz ON _ _ _ i IfcHz ON Alarm RESET X indicates that the counter may take any value during write operations but always be when read out Note 1 MODE CO is set by writ i riq data X r X 0 r 0 to address D Note 2 Bit 1 of ...

Page 139: ...egister X X 6 Al arm day of the wee register X X 7 Alarm 1 doy register B 9 Alarm 10 day register X X X X X Timer EN Test 3 THz 5N X X X X A i2 1 hour 2 4 hour selector Leap year counter X B X X X C X D Mode Register Alarm EN Test 2 16Hz 5fl MODE 3 Ml Test I MO Test E Test Register F Re set Controller Timor RESET Alarm RESET Note 1 MODE 01 is set by writing data X x 0 l to address D C 63 ...

Page 140: ...imer EN Alarm EN MODE t Ml elector Timer EN Alarm EM MODE selector MO Mi MO E Test 3 Test 2 Test 1 Timer RESET Test J Test 3 Test 2 Test 1 Test L J 2 Hz ON 16 Hz ON Alarm RESET nil ow 16Hz ON Timer RESET Alarm RESET Note 1 MODE ID is set to by writing data X X 1 0 to address D MODE 11 is set by writing data x K l lt to address D MODE 10 and 11 are in RAM areas C 64 ...

Page 141: ...DO 0 It simultaneously counts with the year counter The 1 2 hour 24 bour selector sets the 12 hotir system when DO and the 24 hour system when DO I PM or AM is selected when Dl in the 10 hour counter is 1 or 0 respectively see page 4 7 Reset controller I6HZ IH2 clock register A3 A2 A1 A0 1 1 1 1 F DO 3 resets all alarm registers and internal Alarm F Fs Dl 1 resets the 15 stage dividers before the ...

Page 142: ...he CS CS WR signal For details see the block diagram o the RP5C01 or Section 4 of these Application Motes READ CVCLE CS H CS Note 2 AO A3 DO D3 RD MO te 2 f XT tAC tRD Jv Notts 2 The RP5CG1 accepts an RD signal when both CS low and CS high in the saw way as for a WR signal Tho RL signal in the above d lag ram should t her e fore be t ikt n the C5 CS RD s gnsl in the sarae way as the WR signai For ...

Page 143: ...h the 1 6H2 signal Address A3 A2 Al r AG 1 1 1 1 Data 1 r 0 Q G When adjusting with the 1H2 signal Address A3 A2 Al AO U 1 1 1 Data 0 1 0 0 CJSCIN Note 3 CI 10FF 3UPFr C2 30PFr j K lOOkft Crystal oscillator Nihon penpa Kogyo MX3AT Fig Note 3 Different values of ill T C2 and R may be used and the crystal osci 11 ator is not definitely specified The values of Cl r C2 and R noted above are the best v...

Page 144: ...ed the arrangement shown in Figs 2 a and 2 b below should be adopted The OSCIN terminal is not TTL cfjmp tible but CMOS compa tible 1 With CMOS inverter CMOS MC4069UB RP5C01 Fig 2 a 2 Ki r h TTL inverter Kp 32 768kHz T 5 u Vv 7Q A l scout TTL 74LS04 Fig 2 bJ C 68 ...

Page 145: ... C CS J OSCOUT ie 30ADJ OSCIN A RD RD RD RD i 9 J Gll l ALARK 03 KuppJ y circuit itJ VA h h E5 16HT r c 15j t See tote 5 on page 55 14J Rp a 1 3 5 Rp Kp 11 12 t r i J Rp i 1 t 5V RD lOOkft 3G0kn Rp 4 7kO 471 0 J n ermi u s Iwo I i p ssf ect r iii i na I s arc vj rov i di d The C i x v v r i rinT i 1 1 be connected r o L he Ow r oown oe Lee tloji i y y ii r trrriirK is Lc the CPU CS is active ahjn ...

Page 146: ...O or inpu t terminals However it is recoisni ended that pull up resistors be used for ClS RT and W since if pull down resistors are used for these terminals they wi 1 1 become active when the CPU is on hold e g at DMA cycle control lines of Cs RD t and WR start to float instantaneously and this may lead to problems The arrangement o resistors shown in Fig 3 is an example on y and may be altered Fo...

Page 147: ...cation Entry conditions D x coordinate 1 40 E y coordinate 1 16 Exit condition none 8D6A PLOT Turn on pixel at specified location Entry conditions D x coordinate 0 239 E y coordinate 0 1 27 Exit condition none 8D76 UNPLOT Turn off pixel at specified location Entry conditions D x coordinate 0 239 E y coordinate 0 127 Exit condition none 8D77 POSIT Set cursor position Entry conditions H column numbe...

Page 148: ...Lock display no scrolling 4F5E V UNLOCK Unlock display scrolling 4F63 w CURSON Turn on cursor 4F68 p CURSOF Turn off cursor 4F6D Q DELLIN Delete line at current cursor position 4F72 M INSLIN Insert a blank line at cursor position 4F77 L ERAEOL Erase from cursor to end of line 4F7C K ENTREV Set Reverse character mode 4F88 P EXTREV Turn off Reverse character mode 4F8D P Variable and Status Locations...

Page 149: ...7 F8 8 LABEL 9 PRINT OA SHI FT PRINT OB PASTE Wait and get character from keyboard Entry conditions none Exit conditions A character code Carry set if special character reset if norma character F1 F8 return preprogrammed strings CHSNS Check keyboard queue for characters Entry conditions none Exit conditions Z flag set if queue empty reset if keys pending 12F7 1404 KEYX Check keyboard queue for cha...

Page 150: ...d driver when processing F1 F8 keys The strings have maximum length of 1 characters and are terminated by a 80 Hex code If the last character of the string is OR ed with 80 the character will also serve as a terminator The entire string will be placed in the keyboard buffer when the appropriate strings for all 8 keys are pressed You must specify character strings for all 8 function keys use the te...

Page 151: ...s none OUTDLP Print a character expanding tabs to spaces Entry conditions A character to be printed Exit conditions 4FC4 ERAFNK Erase function key display Entry conditions none Exit conditions none 4FA9 FNKSB Display function table if enabled Entry conditions none Exit conditions none 6E42 Printing Routines Function Name Description Hex Entry Address PRINTER Send a character to the line printer 84...

Page 152: ...tions HL ph number address Exit conditions none 622B RCVX Check RS232C queue tor characters Entry conditions none Exit conditions A number of characters in queue Z flag set if no data reset if characters pending 8508 RV232C Get a character from RS232 receive queue 8519 Entry conditions none Exit conditions A character received Z flag set if O K reset if error PE FF or OF Carry set if BREAK pressed...

Page 153: ...EAK pressed else reset BAUDST Set Baud rate for RS232 C 86AD Entry conditions 1 1 Baud rate 1 9 M Exit conditions none 86DE INZCOM Initialize RS232 C and Modem Entry conditions H Baud rate 1 9 L USART configuration code USART 8251 Carry set if RS232 C reset if modem Exit conditions none BITfS Description 0 1 Baud rate 00 None 10 X1 01 X16 fix 1 1 X64 2 3 Word length 00 5 10 6 01 7 11 8 4 Parity en...

Page 154: ... Name Description Hex Entry Address DATAR Read character from cassette no checksum Entry Conditions none Exit conditions D character from cassette Carry Set if BREAK pressed else reset 88B3 CTON Turn motor on Entry conditions none Exit conditions none 15C0 CTOFF Turn motor off Entry conditions none Exit conditions none 15C2 CASIN Read a character from cassette and update checksum Entry conditions ...

Page 155: ...nditions Carry set if BREAK pressed else reset RAM Files Routines The Directory Table located at F252 contains all file location type and status information Each file is managed by an 1 1 bytes directory entry in the format Byte 1 Directory Flag for file type and status Byte 2 3 Address of file Byte 4 11 8 Byte filename The Directory Flag contains the following information Bit 7 MSB Bit 6 Bit5 Bit...

Page 156: ...ns HL address of directory entry for file Exit conditions HL TOP start address of file 6E8C KILASC Kill a text DO file Entry conditions DE file TOP start address HL address of directory entry flag Exit conditions none INSCHR Insert a character in a file Entry conditions A character to insert HL address to insert character Exit conditions HL 1 Carry set if out of memory MAKHOL insert a specified nu...

Page 157: ...USIC Make tone see owner s manual tor frequency and duration information Entry conditions DE frequency 0 16383 B duration 0 255 Exit conditions none 8BC0 Read system TIME Entry conditions HL address of 8 byte area for TIME Exit conditions HL TIME hh mm ss 1A7E Read system DATE Entry conditions HI address of 8 byte area for DATE Exit conditions HL DATE mm dd yy 1A9E Read system DAY of the week Entr...

Page 158: ...04 86 SWCC 874 9939 Printed in U S A ...

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