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When the doubler is used, the duty cycle of the clock becomes a critical parameter. The
duty cycle should be measured at the separate clock output pin (pin 2). The minimum
period must be increased by any amount that the clock high time is greater or less than
specified in the duty-cycle requirement.
For example, consider a design where the spreader and doubler are enabled, with 8 ns
nominal delay in the doubler. The high and low clock are equal to within 1 ns. This violates the
duty cycle requirement by 3 ns since (clock low - clock high) can be as small as -1 ns, but
the requirement is that it not be less than 2 ns. Thus, 3 ns must be added to the minimum
period of 21 ns, giving a minimum period of 24 ns and a maximum frequency of 41.6 MHz
(commercial).
Table 28-11. Preliminary Maximum Clock Speeds
(V
DD
±10%, Temp. -40°C to +85°C)
Conditions
Industrial Ratings
Duty Cycle
Requirements
(ns)
Minimum
Period
(ns)
Maximum
Frequency
(MHz)
No Doubler or
Spreader
17
58.8
Spreader Only
Normal
20
50.0
Spreader Only
Strong
21
47.6
Doubler Only
(8 ns delay)
19
52.6
1 > (clock low -
clock high) > 0
Doubler Only
(internal 50%
clock)
20
50
1 > (clock low -
clock high) > -1
Spreader
Normal with
Doubler
(8 ns delay)
21
47.6
4 > (clock low -
clock high) > 2
Spreader
Normal with
Doubler (8 ns
delay), Internal
50% Clock
24
41.6
1 > (clock low -
clock high) > -1
Spreader Only
Strong
21.5
46.5
Spreader Strong
with Doubler
(8 ns delay)
23
43.5
8 > (clock low -
clock high) > 6
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