Rabbit Rabbit 4000, User Manual

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Chapter 19 DMA Channels 179
8. The initial address registers (DyIAnR) should be loaded with the physical address of
the first buffer descriptor.
9. The buffer descriptor can be loaded and the DMA transfer started by writing to the
appropriate bit of DMALR.
19.3.1 Handling Interrupts
The DMA interrupt request is cleared automatically when the interrupt is handled. A DMA
interrupt will occur at the end of a transfer for any buffer descriptor that has bit 4 of DyCR
set.
19.3.2 Example ISR
A sample interrupt handler is shown below.
dma_isr::
push af
; do something with the data in the current buffer
; the interrupt request is automatically cleared
pop af
ipres
ret
19.3.3 DMA Priority with the Processor
Since the Rabbit 4000 DMA uses the memory management unit to perform transfers,
normal code execution cannot occur while the DMA is active. This includes handling
interrupts, so it is important to limit the amount of time that the DMA can operate.
This is handled in several ways. First of all, the DMA transfers can be set to take place
whenever the processor is operating at one of the four priority levels, 0–3 (note that there
is a single priority level for all DMA transfers). Setting an interrupt priority to something
greater than the DMA transfer priority will ensure that no DMA activity occurs during that
interrupt handler. Note that when both an interrupt and a DMA transfer are pending, the
DMA transfer will be selected for execution first (provided its priority is equal or greater
than the current processor priority level).
Table 19-2. DMA Transfer Priority
DMA Transfers at Operation
Priority 0
DMA transfers only allowed when
processor priority at 0
Priority 1
DMA transfers only allowed when
processor priority at 0 or 1
Priority 2
DMA transfers only allowed when
processor priority at 0, 1, or 2
Priority 3 DMA transfers allowed at any time