Rabbit 3000, User Manual

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User’s Manual 77
the duty cycle of the built-in oscillator can be as asymmetric as 52-48, the clock generated
by the clock doubler will exhibit up to a 4% variation in period on alternate clocks. This
does not affect the no-wait states memory access time since two adjacent clocks are
always used. However, the maximum allowed clock speed must be slightly reduced if the
clock is supplied via the clock doubler. The only signals clocked on the falling edge of the
clock are the memory and I/O write pulses and the early option memory output enable.
The spectrum spreader either stretches or shrinks the low plateau of the clock by a maxi-
mum of 3 ns for the normal spreading and 4.5 ns for the strong spreading. If the clock dou-
bler is used this will cause an additional asymmetry between alternate clock cycles.
Figure 7-2. Effect of Clock Doubler
Oscillator
Oscillator delayed
and inverted
Doubled clock
Delay
time
48% 52%
P
0.48P 0.52P 0.48P 0.52P
Data out
Example
Write
Cycle
write pulse
early write pulse
option
Example
Read
Cycle
Address / CS
Address / CS
output enb
early output enb
option
data out from mem